1270114 九、發明說明： • · 【發明所屬之技術領域】 ,. 本發明係有關於半導體製程領域，特別是古關从 寸⑺疋有關於一種能夠降低 淺溝絕緣化學機械研磨製程造成的晶圓傷宝的 防ϋ的牛導體製程方法， 藉此提昇良率。 φ 【先前技術】 如該行業者所熟知，半導體積體電路係製作在如單晶石夕晶圓等 半導體晶_表面上，而在晶圓表面上通常又分割區隔成不同的 晶方區域，在各晶方區域内以半導體製程例如微影及侧技術等 形成元件以及電路之後，再經由測試、切割以及封裝後始構成單 一晶片。在半導體製程中，例如熱氧化製程或清洗製程等，有時 可以同時處理多片晶圓，又稱為批次晶圓處理，而在某些製程步 驟中，例如光學微影製程或電漿蝕刻製程，則是以單片晶圓進行 之。 為確保晶圓的品質以及辨識上的方便，通常在每一片晶圓上都 會提供有晶圓雷射刻號(laser marking)，可包含晶圓的批次編號以 及晶圓身份辨識號碼等肉眼可見之訊息，其通常是以雷射方式繞 結在晶圓的正面，也就是積體電路形成的相同面。 請參閱第1圖以及第2圖，其中第1圖繪示的是習知晶圓1〇 6 1270114 的上視圖，特別顯示包括雷射刻號區域12、積體電路晶方區域22、 晶邊曝光區域(wafer edge exposure，WEE)以及晶邊清洗區域(edge bead removal，EBR);第2圖繪示的是靠近第1圖中雷射刻號區域 12附近的晶圓10之放大示意圖。如第1圖以及第2圖所示，晶圓 10通常有V字型切口 14,而雷射刻號區域12通常位在V字型切 口 14附近位置，且設在晶圓10的正面。雷射刻號區域12與圍繞 在積體電路晶方區域22周圍的切割道24相鄰接，且雷射刻號區 • 域12與切割道24的界面通常距離晶圓的邊緣40大約6·5釐米左 右。雷射刻號區域12設於晶圓邊緣的用意在避免影響到積體電路 晶方區域22内的積體電路的製作。 在第2圖中，以環形界線3〇表示前述之晶邊清洗區域，其通 常為距離晶圓的邊緣40大約U Μ米左右，而以環形界線2〇表示 別述之晶邊曝光區域，其通常為距離晶_邊緣⑽大約b羞米 左右。如該行業者所知，在環形界線3〇與晶圓邊緣4〇之間的環 =區域内的光阻以及抗反射層可以在微影製織財被清除掉， 猎此降低製蹄染的可紐。在環料線％與·邊緣如之 的環形區域⑽纽，則是在曝絲影後被去除。此外，在雷^ 刻號區域η左右兩側的過剩晶_域26以及π内則通常不二 成有任何的積體電路圖案。 曰/ 構，圖^絕緣結 回刀ΛΗ方向所視之剖面示意圖。在製作淺溝絕 1270114 此^ 時也定料積體電路晶方輯22⑽絲區域，因 細奸、先阻又稱為主動區域(ΑΑ)光阻。如第3圖所示，在雷 100 =身㈣識號碼的晶圓雷射刻號5G。首先，在半導體基底雇 ^面上職魏骑62。鮮，雜祕層62 墊氮切 增64 〇 如第4圖所示，接著進行微影製程，於墊氮化石夕層料上形成 /光阻圖案70，其包合開口 72，暴露出積體電路晶方區域^内 待餘刻至半導縣底_巾的趙絕賴域，以關口 ％ ,暴露 出全部的f射職區域12。通常，雷射職區域12與前述的晶邊 曝光區域同時在顯影後被打開。 如第5圖所示，利用aa光阻圖案7〇作為蝕刻硬遮罩，進行 乾餘刻製程，蝕刻經由AA光阻圖案7〇的開口 72以及74所暴露 出來的墊氮化秒層64、墊氧化層62以及半導體基底1〇〇，以於積 體電路晶方區域22 淺溝82，同時，於雷射刻號區域 12形成大面積的凹陷區域84。接下來，將剩下的aa光阻圖案7〇 去除。如第6圖所示，隨後再將溝渠填充材料88，例如化學氣相 沈積石夕氧層(CVD oxide)，沈積於半導體基底100的表面上，並且 填滿STI淺溝82以及凹陷區域84。 如第7圖所示，接著利用墊氮化矽層64作為研磨停止層，進 1270114 行化學機械研磨(CMP)製程，藉以研磨掉在STI淺溝外的多餘溝渠 真充材料88。進行上述STI化學機械研磨過程中，必須將墊氮化 .夕㈢64上的屢渠填充材料88完全去除掉，否則容易造成後續進 ,—灯墊氮化矽層64剝除步驟時，無法完全剝除墊氮化矽層64，而在 曰曰圓表面產生不必要的殘留物。 為了嫁保墊氮化矽層64上的溝渠填充材料88可以完全被去除 • 掉，省知技藝STI化學機械研磨過程中通常會使用化學機械研磨 或電水餘刻(plasma etch)實施過研磨(οΜ-ρο^)或姓刻步驟。然 而，過研磨的結果卻造成在晶圓表面上如墊氮化矽層的過度消 耗、淺溝内絕緣層損失以及晶圓傷害等等缺陷，如標號92所指位 置。在實際的晶圓製造過程中，特別是在如第2圖中所標示的虛 線區域90内，常會發現有嚴重的晶圓傷害，猶待進一步的改善。 【發明内容】 本發明之主要目的在提供一種改良之半導體積體電路的製作 方法，以解決上述習知技藝的問題。 • 本發明之另一目的在提供一種能夠降低淺溝絕緣化學機械研 磨製程造成的晶圓傷害的半導體製程方法，藉此提昇良率。 本發明之另一目的在提供一種半導體積體電路的製程中增加 淺溝絕緣化學機械研磨製程餘裕度的方法。 9 1270114 為達本發明之上述目的，本發雜佳實施例提供-種降低淺溝 絕緣化學機械研磨製程造摘晶圓傷麵方法，包含有提供一晶 0其包各複數個積體電路晶方區域、圍繞各該積體電路晶方區 域周圍的切割道以及-提供有晶圓批次編號以及晶圓身份辨識號 碼的晶圓雷射舰的雷_號區域，其中該雷射舰區域係設於 該晶圓之邊緣並與該_道相祕；_晶圓上形成—塾氧化 層’於該墊氧化層上形成-魏化補；於雜氮化⑦層上形成 -主動區域光關案’其巾社祕域光阻_具有暴露出該積 體電路晶方區域崎侧至該晶gj之基底以形成絕緣淺溝之一溝 渠開口，以及僅暴露出該雷射刻號區域内的—過度區域的一虛設 開口；利用該主動區域光阻_作為—_硬遮罩，進行一乾餘 刻製程’侧經由該主動區域光阻_的該溝渠開σ以及該虛設 開口所暴露出來的該墊氮化石夕層、該墊氧化層以及該基底，以於 該積體電路晶方區域内形成-絕緣淺溝，同時，於該雷射刻號區 域的該過賴域⑽成-虛設淺溝；去除魅祕域光阻圖案； 於該晶圓表面沈積-溝渠填充材料，並填滿該絕緣淺溝以及該虛 设淺溝；在進行化學機械研磨製程前，於該溝渠填充材料上利用 游標對準鍵(align accuracy vernier)上的矽氧層去除步驟或反相罩 幕蝕刻法(reverse mask etch)所形成之光阻硬遮罩，使其具有一開 口，暴露出該雷射刻號區域；經由該遮罩之該開口，蝕刻該溝渠 填充材料，藉此降低該溝渠填充材料在該晶圓雷射刻號上方的厚 度’去除該逆遮罩，以及利用該塾氮化;5夕層做為一研磨停止層， 進行一化學機械研磨製程，研磨該溝渠填充材料。 1270114 為了使胃審查委員能更進一步了解本發明之特徵及技術内 谷明夢閱以下有關本發明之詳細說明與附圖。然而所附圖式僅 ‘供參考鋪助說明用，並非用來對本發明加以限制者。 【實施方式】 明參閱第8圖’其緣示的是本發明較佳實施例晶圓⑺的雷射 刻號區域12附近的上視圖，其中顯示包括積體電路晶方區域^、 晶邊曝光區域(wafer edge exposure，WEE)以及晶邊清洗區域(edge beadrem〇val，EBR)。如第8圖所示，晶圓1〇具有v字型切口 14, 而雷射刻號區域12通常位在v字型切口 14附近位置，且設在晶 圓10的正面。在雷射刻號區域12内則提供有包含晶圓的批次編 號以及晶圓身份辨識號碼的晶圓雷射刻號5 〇。雷射刻號區域i 2 與圍繞在積體電路晶方區域22周圍的切割道24相鄰接，且雷射 刻號區域12與切割道24的界面通常距離晶圓的邊緣4〇大約6.5 屋米左右。雷射刻號區域12設於晶圓邊緣的用意在避免影響到積 體電路晶方區域22内的積體電路的製作。此外，本發明在晶圓雷 射刻號50與積體電路晶方區域22之間的雷射刻號區域12内定義 有過渡區域112。 " 在第8圖中，同樣以環形界線3〇表示晶邊清洗區域，其通常 為距離晶圓的邊緣40大約1·5釐米左右，而以環形界線2〇表示晶 邊曝光區域，其通常為距離晶圓的邊緣4〇大約2·5釐米左右。如 該行業者所知，在環形界線30與晶圓邊緣40之間的環形區域内 11 1270114 的光阻以及抗反射層可以在微影製程過程中被清除掉，藉此降低 製程污染的可能性。在環形界線2〇與糊邊緣4G之間的環形區 --域内的光阻，則是在曝光顯影後被去除。此外，在習知技藝中， I射刻號區域12左右兩侧的過剩ΒθΒ®ϋ域26以及28内則通常不 會形成有任何的積體電路圖案。 清參閱第9圖至第14圖，其緣示的是本發明較佳實施例製作 • 絕緣結構’沿著第8圖中切線Π-Π方向所視之剖面示意圖。 ' 在製作淺溝絕緣結構時，同時也定義出積體電路晶方區域22内的 主動區域，因此所使用的光阻又稱為主動區域(ΑΑ)光阻。如第9 圖所示，在雷射刻號區域12 _半導體基底励中形成有紀錄晶 圓批次編號及晶圓身份辨識號碼的晶圓雷射刻號5〇。首先，在半 導體基底1〇〇的表面上形成塾氧化層62。接¥，在塾氧化層62 上沈積墊氮化矽層64。 .如第9圖所示’接著進行微影製程，於塾氮化石夕層糾上形成 ΑΑ光阻圖案7〇。形成从光阻圖案％的步驟首先是在晶㈣ ^面上㈣光阻液’在旋塗光崎之前可先形成抗反射層，以提 昇微影製程的解析度。由於以旋塗方式形成光阻層容易在晶邊累 積車又多的光阻’其可能剝落而產生微粒污染問題，因此，在晶邊 位置上的光阻’亦即在前述之晶邊清洗區域以及晶邊曝光區域内 會被進—步地被去除(以化學清洗或曝光方式）。隨後， 晶圓被送至曝光機台’進行曝光以及_轉移。最後，根據光阻 12 1270114 (例如正光阻或負光阻)’被曝光的區域或者未被曝光的區域 ^齡除，完賴影步驟。通常，在完成顯影製程之後，晶圓 曰二4查以確錢否有缺陷發生。這些缺陷可能是光阻或抗反 老^塗佈的缺曝光輕不準問題或者顯影過程巾由於污染或 處理不當所產生的缺陷。 / AA光阻圖案7G包含開σ 72，暴露出積體電路晶方區域μ内 •待軸1至轉體基底1⑻巾嶋，以及開口 74a，其僅 僅暴露出部份的過渡區域112。根據本發明之較佳實施例，雷射刻 就區域12内除了過渡區域112之外，雷射刻號區域_其它區 域並不會與前述的晶邊曝光區域同時在顯影後被打開。 如第10圖所示，利用AA光阻圖案70作為蝕刻硬遮罩，進行 乾钱刻衣私’飯刻經由AA光阻圖案7〇的開口 72以及74a所暴 ，露出來的墊氮化石夕層64、墊氧化層62以及半導體基底励，以於 積體電路晶方區域22内形成STI淺溝82，同時，於雷射刻號區域 12的過渡區域112内形成虛設淺溝84a。接下來，將剩下的aa 光阻圖案70去除。 ， 如第11圖所示，隨後，再將溝渠填充材料88，例如化學氣相 沈積矽氧層(CVD oxide)，沈積於半導體基底100的表面上，並且 填滿STI淺溝82以及虛設淺溝84a。此時，由於雷射刻號區域12 的大部分區域並未被打開，在雷射刻號區域12正上方的溝渠填充 13 1270114 材料88的表面會比在積 88的表面來得…而左〜曰曰方區域22上方的溝渠填充材料 高度落差。 在田射刻號區域12的過渡區域m附近形成 畢220，不’接者在溝渠填絲料路的表面上形成一逆遮 12之Η 僅暴路出除了過渡區域112以外的雷射刻號區域 汗σ 2 〇隨後’利用化學機械研磨前所形成的遮罩挪作 為侧^遮罩，進行偷刻製程，經由遮罩⑽的開口 222向下 制广Γ木真充材料88。11個步驟1以確保在後續的化學機械研磨 ’ If _號_ 12 ^^方㈣渠填充材料88可以完全 2墊虱化韻64的絲上被去轉，而不需要進行過度的過研磨 或蝕刻步驟。接著，將遮罩220去除。 如第13圖所示，接著利用墊氮化石夕層64作為研磨停止層，進 行化學機械研磨_>)製程，藉以研磨掉在STI、淺溝外的多餘溝渠 填充材料88。如前所述，進行上述STI化學機械研磨過程中，必 須將墊氮化石夕層64上的溝渠填充漏88完全去除掉，否則容易 造成後續進統㈣M 步，科，無法完全嫌魏化石夕 層64，而在晶圓表面產生不必要的殘留物。為了雜墊氣化石夕層 64上的溝渠填充材料88彳以完全被絲掉，通常會實施過研磨步 驟。此時’由於雷射刻號區域^的大部分區域(除了過渡區域112 以二卜)被塾氮化石夕層64覆蓋住，因此，進行化學機械研磨之後不會 在罪近替射刻號區域12之積體電路晶方區域22内發生晶圓傷害 14 1270114 現象。 -· ^第14圖所不，接下來的步觀是糊餘_氮切層64以 ._ ^祕層62從晶81表面絲。本㈣之主要特徵姐在以光阻 定義淺溝絕緣區_時候，僅僅打開部分的雷射刻號區域Η(過渡 區域U2) ’紐將與積體電路晶方區域22部分相_電路圖宰 (sti溝渠圖案)曝於雷射刻號區域12的過渡區域ιΐ2内，其中過 •渡區域112内的電路圖案或™溝渠圖案並不與晶圓雷射刻號50 重疊。 根據本發明之另-較佳實施例，如第8圖所示，在通常不會形 成有任何的積體電路圖案的雷射刻號區域12左右兩侧的過剩^圓 區域26以及28 _可以形成與積體電路晶方區域22部分相同的 電路圖案(STI溝渠圖案）。 ’ 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍 所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 弟1圖緣示的是習知晶圓的上視圖，特別顯示包括雷射刻號區 域、積體電路晶方區域、晶邊曝光區域以及晶邊清洗區域。 第2圖繪示的是雷射刻號區域附近的晶圓之放大示意圖。 15 1270114 第3圖至第7 _示的是f知技藝製作淺溝絲結構之剖面示 意圖。 •、第8®絲岐本發陳佳實補晶®的職區域附近的 上視圖顯不積體電路晶方區域、晶邊曝光區域以及晶邊清洗區 域。 第賴U圖繪示的是本發明較佳實施例製作淺溝絕緣結 構’沿者“财域IWI麵所視之麻示意圖。 【主要元件符號說明】 10 晶圓 12 雷射刻號區域 14 V字型切口 20 環形界線 22 積體電路晶方區域 24 切割道 26 過剩晶圓區域 28 過剩晶圓區域 30 環形界線 40 晶圓邊緣 50 晶圓雷射刻號 62 墊氧化層 64 塾氮化石夕層 70 主動區域光阻層 72 開口 74、 74a 開口 82 STI淺溝 84 凹陷區域 84a 虛設淺溝 88 溝渠填充材料 90 虛線區域 92 缺陷 100 半導體基底 112 過渡區域 220 遮罩 222 開口1270114 IX. Description of the invention: • · The technical field of the invention belongs to the invention. The present invention relates to the field of semiconductor manufacturing, in particular to the ancient wafer from the inch (7), which relates to a wafer capable of reducing the chemical mechanical polishing process of shallow trench insulation. Injury's anti-mite cattle conductor process method, thereby improving yield. φ [Prior Art] As is well known in the industry, semiconductor integrated circuits are fabricated on a semiconductor crystal surface such as a single crystal wafer, and are usually divided into different crystal regions on the surface of the wafer. After forming components and circuits in a semiconductor region by a semiconductor process such as lithography and side technology, a single wafer is formed after testing, cutting, and packaging. In semiconductor processes, such as thermal oxidation processes or cleaning processes, sometimes multiple wafers can be processed simultaneously, also known as batch wafer processing, and in some process steps, such as optical lithography or plasma etching. The process is carried out on a single wafer. In order to ensure the quality of the wafer and the convenience of identification, a wafer laser marking is usually provided on each wafer, which can include the batch number of the wafer and the wafer identification number. The message is usually laser-wrapped to the front side of the wafer, that is, the same surface formed by the integrated circuit. Referring to FIG. 1 and FIG. 2 , FIG. 1 is a top view of a conventional wafer 1 〇 6 1270114, particularly including a laser marking region 12, an integrated circuit crystal region 22, and a crystal edge exposure region. (wafer edge exposure, WEE) and edge bead removal (EBR); FIG. 2 is an enlarged schematic view of the wafer 10 near the vicinity of the laser engraved area 12 in FIG. As shown in Figs. 1 and 2, the wafer 10 usually has a V-shaped slit 14, and the laser-marked region 12 is usually positioned near the V-shaped slit 14 and provided on the front side of the wafer 10. The laser engraved area 12 is adjacent to the scribe line 24 surrounding the integrated circuit crystal area 22, and the interface of the laser engraved area•domain 12 and the scribe line 24 is typically about 6 from the edge 40 of the wafer. 5 cm or so. The laser marking region 12 is provided at the edge of the wafer to avoid affecting the fabrication of the integrated circuitry within the integrated circuit region 22. In Fig. 2, the aforementioned edge cleaning region is generally indicated by an annular boundary line 3, which is usually about U Μ m from the edge 40 of the wafer, and the edge boundary exposed region is indicated by a ring boundary 2 ,. Usually about the distance from the crystal edge (10) is about b shame. As is known to the industry, the photoresist and the anti-reflective layer in the ring=region between the ring boundary 3〇 and the wafer edge 4〇 can be removed in the lithography, and the hunting can be reduced. New Zealand. In the annular region (10) of the loop line % and the edge, it is removed after exposure to the shadow. Further, in the excess crystal regions 26 and π on the left and right sides of the horn region η, there is usually no integrated circuit pattern.曰 / structure, Figure ^ Insulation knot The schematic view of the knives in the direction of the knives. In the production of shallow trenches 1270114 this ^ is also fixed in the integrated circuit crystal series 22 (10) silk area, because the fine, first resistance is also called the active area (ΑΑ) photoresist. As shown in Figure 3, the laser laser is numbered 5G in the mine 100 = body (four) identification number. First of all, in the semiconductor substrate hired on the surface of Wei Wei 62. Fresh, mysterious layer 62 pad nitrogen cut 64, as shown in Fig. 4, followed by a lithography process, forming a photoresist pattern 70 on the pad nitride layer, which covers the opening 72, exposing the integrated body The crystal area of the circuit is left to the bottom of the semi-conductor county, and the Zhao’s area is covered by the gate. Typically, the laser job area 12 is opened simultaneously with the aforementioned grain edge exposure area after development. As shown in FIG. 5, the aa photoresist pattern 7 is used as an etching hard mask, and a dry etching process is performed to etch the pad nitride layer 64 exposed through the openings 72 and 74 of the AA photoresist pattern 7 The pad oxide layer 62 and the semiconductor substrate 1 are formed so as to form the shallow trenches 82 of the integrated circuit region 22, and a large-area recessed region 84 is formed in the laser-marked region 12. Next, the remaining aa photoresist pattern 7 is removed. As shown in Fig. 6, a trench fill material 88, such as a chemical vapor deposited CVD oxide, is subsequently deposited on the surface of the semiconductor substrate 100 and fills the STI shallow trench 82 and the recessed region 84. As shown in Fig. 7, the pad nitride layer 64 is then used as the polishing stop layer, and a 1270114 chemical mechanical polishing (CMP) process is performed to grind away the excess trench true charge material 88 outside the STI shallow trench. During the above-mentioned STI chemical mechanical polishing process, the repeated channel filling material 88 on the mat Nitrile (III) 64 must be completely removed, otherwise it is easy to cause subsequent advancement, and the stripping step of the tantalum nitride layer 64 cannot be completely stripped. The tantalum nitride layer 64 is removed to create an unnecessary residue on the rounded surface. In order to ensure that the trench fill material 88 on the tantalum nitride layer 64 can be completely removed, the STI chemical mechanical polishing process is usually performed using chemical mechanical polishing or plasma etch. οΜ-ρο^) or surname steps. However, over-grinding results in defects such as excessive wear of the pad nitride layer, loss of insulating layer in the shallow trench, and wafer damage on the wafer surface, as indicated by reference numeral 92. In the actual wafer fabrication process, particularly in the dashed area 90 as indicated in Figure 2, severe wafer damage is often found and further improvements are needed. SUMMARY OF THE INVENTION A primary object of the present invention is to provide an improved method of fabricating a semiconductor integrated circuit to solve the above-described problems of the prior art. • Another object of the present invention is to provide a semiconductor process method capable of reducing wafer damage caused by shallow trench insulating chemical mechanical polishing processes, thereby improving yield. Another object of the present invention is to provide a method of increasing the margin of the shallow trench insulating chemical mechanical polishing process in the process of a semiconductor integrated circuit. 9 1270114 In order to achieve the above object of the present invention, the present invention provides a method for reducing wafer surface damage by shallow trench insulating chemical mechanical polishing process, which comprises providing a crystal 0 package of a plurality of integrated circuit crystals. a square area, a scribe line around the crystal area of each integrated circuit, and a Ray_No. area of the wafer laser ship provided with the wafer batch number and the wafer identification number, wherein the laser ship area It is disposed at the edge of the wafer and is intimate with the _ channel; _ forming a 塾-oxide layer on the wafer to form a Wei-Fu on the pad oxide layer; forming an active region on the 7-layer of the nitriding layer The 'the towel's secret field photoresist _ has exposed the crystal circuit area of the integrated circuit to the base of the crystal gj to form one of the insulating shallow trenches, and only exposes the area of the laser marking a dummy opening of the excessive region; using the active region photoresist _ as a hard mask, performing a dry-cut process s s s σ via the active region photoresist _ and the exposed portion of the dummy opening Pad nitride layer, the pad oxide layer and a substrate for forming a shallow trench in the crystal region of the integrated circuit, and at the same time, forming a shallow trench in the overlying region (10) of the laser marking region; removing the photoresist pattern of the charm domain; a round surface deposition-drain fill material fills the insulating shallow trench and the dummy shallow trench; prior to performing the chemical mechanical polishing process, utilizing the oxygen on the aligning precision vernier on the trench fill material a photoresist removal mask formed by a layer removal step or a reverse mask etch having an opening exposing the laser marking region; etching the trench through the opening of the mask Filling the material, thereby reducing the thickness of the trench fill material above the laser mark of the wafer 'removing the reverse mask, and using the tantalum nitride; the 5th layer as a polishing stop layer, performing a chemical mechanical polishing The process grinds the trench fill material. 1270114 In order to enable the Appetite Review Committee to further understand the features and techniques of the present invention, the following detailed description of the present invention and the accompanying drawings. However, the drawings are only for the purpose of reference and are not intended to limit the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to Figure 8, there is shown a top view of a vicinity of a laser-marked area 12 of a wafer (7) in accordance with a preferred embodiment of the present invention, wherein the display includes an integrated circuit crystal area, and a crystal edge exposure. Wafer edge exposure (WEE) and edge beadrem〇val (EBR). As shown in Fig. 8, the wafer 1 has a v-shaped slit 14, and the laser-marked region 12 is usually positioned near the v-shaped slit 14 and is provided on the front side of the wafer 10. A wafer laser mark 5 包含 containing the batch number of the wafer and the wafer identification number is provided in the laser marking area 12. The laser engraved area i 2 is adjacent to the scribe line 24 surrounding the integrated circuit crystal area 22, and the interface of the laser engraved area 12 and the scribe line 24 is typically about 6.5 from the edge of the wafer. Around the meter. The laser marking region 12 is provided at the edge of the wafer to avoid affecting the fabrication of the integrated circuitry within the integrated circuit crystal region 22. Furthermore, the present invention defines a transition region 112 within the laser-engraved region 12 between the wafer laser mark 50 and the integrated circuit crystal region 22. " In Fig. 8, the edge cleaning region is also indicated by the annular boundary 3〇, which is usually about 1. 5 cm from the edge 40 of the wafer, and the edge boundary is indicated by the annular boundary 2 ,, which is usually It is about 2·5 cm from the edge of the wafer. As is known to those skilled in the art, the photoresist and anti-reflective layer of 11 1270114 in the annular region between the annular boundary 30 and the wafer edge 40 can be removed during the lithography process, thereby reducing the likelihood of process contamination. . The photoresist in the annular region between the annular boundary 2 and the paste edge 4G is removed after exposure and development. Further, in the prior art, in the excess ΒθΒ® regions 26 and 28 on the left and right sides of the I-mark region 12, any integrated circuit pattern is usually not formed. Referring to Figures 9 through 14, the accompanying drawings illustrate a cross-sectional view of the preferred embodiment of the present invention. The insulating structure is viewed along the tangential Π-Π direction of Figure 8. When the shallow trench isolation structure is fabricated, the active region in the crystal region 22 of the integrated circuit is also defined, and thus the photoresist used is also referred to as an active region (ΑΑ) photoresist. As shown in Fig. 9, a wafer laser mark 5 纪录 having a wafer lot number and a wafer identification number is formed in the laser mark region 12 _ semiconductor substrate. First, a tantalum oxide layer 62 is formed on the surface of the semiconductor substrate 1A. Next, a pad nitride layer 64 is deposited on the tantalum oxide layer 62. As shown in Fig. 9, the lithography process is followed by forming a tantalum photoresist pattern 7〇 on the tantalum nitride layer. The step of forming the photoresist pattern % is first to form an anti-reflection layer on the crystal (four) surface (four) photoresist solution before the spin coating, to enhance the resolution of the lithography process. Since the photoresist layer is formed by spin coating, it is easy to accumulate more photoresist at the crystal edge, which may peel off and cause particle contamination problem. Therefore, the photoresist at the edge position is also in the aforementioned edge cleaning region. And the edge-exposed areas are removed step by step (by chemical cleaning or exposure). Subsequently, the wafer is sent to the exposure station for exposure and transfer. Finally, the area to be exposed or the area that is not exposed is removed according to the photoresist 12 1270114 (e.g., positive photoresist or negative photoresist), and the shadow step is completed. Usually, after the development process is completed, the wafer is checked to see if there is a defect. These defects may be defects in the lack of exposure of photoresist or anti-aging coatings or defects in the development process towel due to contamination or improper handling. The /AA photoresist pattern 7G includes an opening σ 72 exposing the integrated circuit crystal region μ • the to-be-axis 1 to the swivel substrate 1 (8) frame, and the opening 74a, which exposes only a portion of the transition region 112. In accordance with a preferred embodiment of the present invention, in addition to the transition region 112 within the laser engraved area 12, the laser engraved area_other areas are not simultaneously opened after development as described above. As shown in FIG. 10, the AA photoresist pattern 70 is used as an etching hard mask, and the dry etching is performed on the opening 72 and 74a of the AA photoresist pattern 7 ,, and the exposed pad nitride is etched. The layer 64, the pad oxide layer 62, and the semiconductor substrate are formed to form the STI shallow trench 82 in the integrated circuit crystal region 22, and the dummy shallow trench 84a is formed in the transition region 112 of the laser marking region 12. Next, the remaining aa photoresist pattern 70 is removed. As shown in FIG. 11, a trench fill material 88, such as a CVD oxide, is deposited on the surface of the semiconductor substrate 100 and fills the STI shallow trench 82 and the dummy shallow trench. 84a. At this time, since most of the area of the laser engraved area 12 is not opened, the surface of the ditch filled 13 1270114 material 88 directly above the laser engraved area 12 will be compared to the surface of the product 88. The ditch fill material height difference above the crotch region 22 is. A cross 220 is formed in the vicinity of the transition region m of the field marking region 12, and a non-sinker forms a reversed cover 12 on the surface of the trench filling material path. Only the violent road exits the laser marking other than the transition region 112. The area sweat σ 2 〇 subsequently 'uses the mask formed before the chemical mechanical polishing as a side mask, and performs a stealing process to make the eucalyptus real filling material 88 through the opening 222 of the mask (10). 11 steps 1 to ensure that the subsequent chemical mechanical polishing 'If _ _ 12 ^ ^ square (4) canal filling material 88 can be completely rotated on the wire of the 虱 虱 韵 64 without the need for excessive over-grinding or etching steps. Next, the mask 220 is removed. As shown in Fig. 13, the pad nitride layer 64 is used as a polishing stop layer to perform a chemical mechanical polishing process, whereby the excess trench filling material 88 outside the STI and shallow trenches is ground. As mentioned above, in the above STI chemical mechanical polishing process, the trench filling leak 88 on the pad nitride layer 64 must be completely removed, otherwise it is easy to cause subsequent follow-up (four) M steps, the section, can not completely dispel the Weihuashi layer 64, while creating unnecessary residue on the wafer surface. In order to fill the trench fill material 88 on the fossilized layer 64 to be completely removed, a grinding step is usually performed. At this time, 'because most of the area of the laser marking area ^ (except the transition area 112 is doubled) is covered by the tantalum nitride layer 64, therefore, after chemical mechanical polishing, it will not be in the vicinity of the marking area. A wafer damage 14 1270114 phenomenon occurs in the crystal region 22 of the integrated circuit of 12. -· ^ Figure 14 is not, the next step is the paste _ nitrogen cut layer 64 with ._ ^ secret layer 62 from the surface of the crystal 81 wire. The main feature of this (4) is that the shallow trench insulation zone is defined by the photoresist _ when only part of the laser marking area Η (transition area U2) 'News will be combined with the integrated circuit crystal area 22 part circuit diagram The sti trench pattern is exposed to the transition region ι 2 of the laser engraved area 12, wherein the circuit pattern or TM trench pattern in the over-exit region 112 does not overlap the wafer laser mark 50. According to another preferred embodiment of the present invention, as shown in Fig. 8, the excess rounded areas 26 and 28 on the left and right sides of the laser engraved area 12 in which any integrated circuit pattern is not normally formed are formed. A circuit pattern (STI trench pattern) identical to the portion of the integrated circuit crystal region 22 is formed. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be covered by the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows a top view of a conventional wafer, particularly including a laser marking area, an integrated circuit crystal area, a crystal edge exposure area, and a crystal edge cleaning area. Figure 2 is an enlarged schematic view of the wafer near the laser engraved area. 15 1270114 Figures 3 through 7 show the cross-sectional views of the shallow groove structure made by F. • The top view near the 8® wire 岐 发 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳 佳The U-shaped diagram of the first embodiment of the present invention is a schematic diagram of the micro-insulation structure of the shallow trench insulation structure along the IWI surface of the financial domain. [Main component symbol description] 10 wafer 12 laser marking area 14 V Font cut 20 Ring line 22 Integrated circuit crystal area 24 Cut track 26 Excess wafer area 28 Excess wafer area 30 Ring boundary 40 Wafer edge 50 Wafer laser marking 62 Pad oxide layer 64 Tantalum nitride layer 70 active area photoresist layer 72 opening 74, 74a opening 82 STI shallow groove 84 recessed area 84a dummy shallow groove 88 trench filling material 90 dashed area 92 defect 100 semiconductor substrate 112 transition region 220 mask 222 opening