CN101924045A - Method of forming connecting salient points on semiconductor device - Google Patents

Method of forming connecting salient points on semiconductor device Download PDF

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Publication number
CN101924045A
CN101924045A CN2009101490647A CN200910149064A CN101924045A CN 101924045 A CN101924045 A CN 101924045A CN 2009101490647 A CN2009101490647 A CN 2009101490647A CN 200910149064 A CN200910149064 A CN 200910149064A CN 101924045 A CN101924045 A CN 101924045A
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CN
China
Prior art keywords
salient point
photoresistance
area
metal level
over against
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CN2009101490647A
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Chinese (zh)
Inventor
林世雄
黄柏辅
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AU Optronics Corp
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AU Optronics Corp
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Priority to CN2009101490647A priority Critical patent/CN101924045A/en
Publication of CN101924045A publication Critical patent/CN101924045A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention provide a method of forming connecting salient points on a semiconductor device, comprising the following steps: depositing a first salient point limited metal layer on a protecting layer of the semiconductor device to fill in a through hole; forming a photoresist layer on a substrate; exposing and developing the photoresist layer by using a grey scale photomask so as to simultaneously form a plurality of photoresist cores corresponding to a connecting cushion of the semiconductor device and a photoresist protecting layer arranged at the center of the semiconductor. In the method of forming the connecting salient points on the semiconductor device, the photoresist cores and photoresist protecting layers are simultaneously formed on the semiconductor device in the exposing and developing etching processes by using the grey scale photomask; the method simplifies the manufacturing technique. The photoresist cores are used for subsequently forming the connecting salient points; the photoresist protecting layer can protect the semiconductor device from etching or scrapping in the subsequent process.

Description

On semiconductor device, form the method that connects salient point
Technical field
The present invention relates to semiconductor fabrication process, relate in particular to a kind of method that connects salient point that on semiconductor device, forms.
Background technology
Various semiconductor devices (for example integrated circuit (IC) chip) generally include a plurality of metal connection gaskets that expose (for example aluminium pad) after completing, the internal circuit of this metal connection gasket and this semiconductor device electrically connects.Upward also with between the carrier realize being electrically connected for semiconductor device being installed in carrier (a for example circuit board), need on the connection gasket of semiconductor device, make forming connection salient point (Bump) usually.In existing manufacture craft, connect salient point and generally adopt gold to make.Can (Anisotropic Conductive Film ACF) engages (bonding) to carrier with this semiconductor device by various anisotropy conducting films after au bump completes.
Consider gold and ACF material unit price height, industry is developed the use polyimides, and (Polyimide, PI) part replaces the connection salient point of gold, promptly uses PI to be kernel, coats the usefulness of PI kernel as the signal conduction with gold again.
On the other hand, in connecting the salient point processing procedure, can make thick approximately 3.5 a microns protective layer (generally also being the PI protective layer) in the semiconductor device center, as protection circuit, with avoid it to be corroded or in successive process by the usefulness of scratch.Yet in existing manufacture craft, the PI kernel and this PI protective layer that connect in the salient point form separately, and complex manufacturing technology and cost are higher.
In view of this, be necessary to provide the manufacture method of the connection salient point that a kind of manufacture craft more simply has the PI kernel.
Summary of the invention
The object of the present invention is to provide a kind of manufacture craft more simply to have the manufacture method of the connection salient point of PI kernel.
The object of the invention to solve the technical problems is to adopt following technical scheme to realize.
A kind of method that connects salient point that on semiconductor device, forms, this semiconductor device comprises a substrate, a connection gasket and a protective layer, this connection gasket exposes from one of being formed in this protective layer through hole, and this method comprises: the deposition first salient point limited metal level is to insert this through hole on this protective layer; Form photoresist layer in this substrate, this photoresist layer comprises first area and second area, and this first salient point limited metal level is covered under this first area; Remove this first area except that the part over against this through hole, thereby form a plurality of photoresistance kernels, and remove this second area of part, thereby form a photoresistance protective layer; Deposit the second salient point limited metal level at those photoresistance core surfaces; Connect metal level at this second salient point limited layer on surface of metal deposition salient point; Removing this salient point of part connects metal level and keeps the part that coats those photoresistance kernels; And remove this first, second salient point limited metal level of part and keep the part that comprises those photoresistance kernels, thereby obtain a plurality of connection salient points that are separated from each other on the surface of this semiconductor device.
In the above-mentioned method that on semiconductor device, form to connect salient point, by using gray tone mask, in once exposure, development etch process, on semiconductor device, formed photoresistance kernel and photoresistance protective layer simultaneously, simplified manufacture craft.This photoresistance kernel is used for follow-up formation and connects salient point, and the photoresistance protective layer can protect the circuit in the semiconductor device not to be etched or scratched in successive process.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1 is the method flow diagram that forms the connection salient point on semiconductor device that the technical program provides.
Fig. 2 is the end face schematic diagram of the semiconductor device that provides of the technical program.
Fig. 3 is the generalized section of the semiconductor device of Fig. 2 along I-I ' line.
Fig. 4 is the schematic diagram that forms the first salient point limited metal level on the semiconductor device surface of Fig. 3.
Fig. 5 is the schematic diagram that forms photoresist layer on the first salient point metal level of Fig. 4.
Fig. 6 is the end face schematic diagram of the photoresist layer among Fig. 5
The gray tone mask schematic diagram that adopts when Fig. 7 is exposure.
Fig. 8 is the schematic diagram that forms a plurality of photoresistance kernels after the photoresist layer development etching after the exposure.
Fig. 9 is the schematic diagram that forms the second salient point limited metal level at the photoresistance core surface of Fig. 8.
Figure 10 forms the schematic diagram that salient point connects metal level on the second salient point limited metal level of Fig. 9.
Figure 11 is the schematic diagram after the salient point among part removal Figure 10 connects metal level.
Figure 12 is the schematic diagram after part is removed first, second salient point limited metal level among Figure 11.
1: semiconductor device 10: substrate
11: connection gasket 12: protective layer
13: 21: the first salient point limited metal levels of through hole
22: photoresist layer 221: first area
222: second area 23: the photoresistance kernel
24: photoresistance protective layer 30: gray tone mask
32: the second reticle field of 31: the first reticle field
33: the three reticle field 21a: the second salient point metal level
25: salient point connects metal level 26: connect salient point
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, to its embodiment of module backlight, structure, feature and the effect thereof that foundation the present invention proposes, describe in detail as after.
Consult Fig. 1, the method that connects salient point that forms on semiconductor device that technical solution of the present invention provides may further comprise the steps:
Step 110 is consulted Fig. 2 and Fig. 3, and semiconductor device 1 is provided, and it comprises substrate 10, a plurality of connection gasket 11 and protective layer 12, and connection gasket 11 exposes in the corresponding through hole 13 from being formed in the protective layer 12.Substrate 10 can be silicon base, the GaAs based end or is formed by other semi-conducting material manufacturings.Connection gasket 11 can be made by aluminium, copper or other similar metals and form.Protective layer 12 can be polymer, oxide, oxide (for example silicon nitride, silicon oxynitride) or the carbide (for example carborundum, silicon oxide carbide) of polyimides, silicon dioxide, other insulation.In the present embodiment, protective layer 12 is formed at the surface of substrate 10 via coating by polyimides.Through hole 13 can be formed in the protective layer 12 by the mode by exposure, development.
Step 120 is consulted Fig. 4, and the deposition first salient point limited metal level 21 covers connection gasket 11 to insert through hole 13 on protective layer 12.The first salient point limited metal level 21 is used to prevent the directly contact and react or produce unnecessary counterdiffusion mutually and influence the performance of connection gasket 11 of follow-up formation material thereon and connection gasket 11.The first salient point limited metal level 21 can be metal (for example copper), alloy (for example titanium-tungsten, chrome copper (CrCu)) or other conductive compounds (for example nickel sulfide (NiS), titanium nitride (TiN), carbon tungsten nitride (WCN), tantalum nitride (TaN)).Also can be the complex metal layer that multilayer material deposits formation successively.In the middle of the present embodiment, the first salient point limited metal level 21 is the titanium-tungsten layer, and it can adopt the mode of sputter to deposit.
Step 130 is consulted Fig. 5 and Fig. 6, forms photoresist layer 22 in substrate 10, and photoresist layer 22 comprises first area 221 and second area 222, and the first salient point limited metal level 21 is covered in the first area 221 times.In the present embodiment, photoresist layer 22 is a polyimides.
Step 140 is consulted Fig. 7 and Fig. 8, removes first area 221 except that the part over against through hole 13, thereby forms a plurality of photoresistance kernels 23, and remove part second area 222, thereby form a photoresistance protective layer 24.Particularly, at first, simultaneously overall optical resistance layer 22 is carried out exposure-processed, wherein first area 221 is different with the exposure of second area 222 over against the part of through hole 13; Secondly, photoresist layer 22 is carried out development treatment, thereby form a little photoresistance kernels 23 and photoresistance protective layer 24.
Above-mentioned different exposure can realize by adopting gray tone mask 30 exposures.Gray tone mask 30 comprises first reticle field 31 over against through hole 13, over against photoresist layer 22 first areas 221 except that second reticle field 32 of the part over against through hole 13, and over against the 3rd reticle field 33 of second area 222, and the light transmittance of second reticle field 32 is greater than the light transmittance of the 3rd reticle field 33, and the light transmittance of the 3rd reticle field 33 is greater than the light transmittance of first reticle field 31.By the control time for exposure, make over against first area 221 and expose fully except that the part over against through hole 13, this moment exposes over against the part and second area 222 parts of through hole 13 in first area 221, and the depth of exposure of second area 222 is darker over against the part of through hole 13 than first area 221.Therefore behind process development etch process, make over against first area 221 except that the part over against through hole 13 is removed fully, first area 221 is fallen over against the part of through hole 13 and second area 222 are partially-etched, and the etch depth of second area 222 is darker over against the part of through hole 13 than first area 221.
Certainly, if the thickness of photoresist layer 22 with want can make first reticle field 31 light tight fully under the identical situation of the thickness of the photoresistance kernel 23 that obtains, at this moment, photoresist layer 22 is not etched over against the part of through hole 13.
Usually, the etch depth of the second area 222 of photoresist layer 22 greater than first area 221 over against 4 to 8 microns of the etch depths of the part of through hole 13.The thickness of photoresistance kernel 23 is 7 to 10 microns.The thickness of photoresistance protective layer is 2 to 3 microns.
Step 150 is consulted Fig. 9, at the photoresistance kernel 23 surface depositions second salient point limited metal level 21a.The second salient point limited metal level 21a can be used for preventing that follow-up formation material thereon from directly contacting with photoresistance kernel 23 and react, perhaps produce unnecessary phase counterdiffusion and influence final making and the performance of connection salient point.The second salient point limited metal level 21a can be metal (for example copper), alloy (for example titanium-tungsten, chrome copper (CrCu)) or other conductive compounds (for example nickel sulfide (NiS), titanium nitride (TiN), carbon tungsten nitride (WCN), tantalum nitride (TaN)).Also can be the complex metal layer that multilayer material deposits formation successively.In the middle of the present embodiment, the second salient point limited metal level 21a is the titanium-tungsten layer, and it can adopt the mode of sputter to deposit.
Step 160 is consulted Figure 10, connects metal level 25 at the second salient point limited metal level 21a surface deposition salient point.Salient point connects metal that metal level 25 can adopt high conductivity for example gold, silver or copper, and what adopt in the middle of the present embodiment is the gold layer.
Step 170 is consulted Figure 11, removes the part salient point and connects metal level 25 and keep the part that coats photoresistance kernel 23.Removing when part connects metal level 25 to adopt Wet-type etching to remove.
Step 180 is consulted Figure 12, removes first, second salient point limited metal level 21 of part, 21a and keeps the part that comprises a little photoresistance kernels 23, thereby obtain a plurality of connection salient points 26 that are separated from each other on the surface of semiconductor device 1.Removing when part connects first, second salient point limited metal level 21 of metal level part, 21a to adopt Wet-type etching to remove.
In the above-mentioned method that on semiconductor device, form to connect salient point, by using gray tone mask, in once exposure, development etch process, on semiconductor device, formed photoresistance kernel and photoresistance protective layer simultaneously, simplified manufacture craft.The photoresistance kernel is used for follow-up formation and connects salient point, and the photoresistance protective layer can protect semiconductor device not to be etched or scratched in successive process.
In the above-described embodiments, because what photoresist layer 22 adopted is positive photoresistance, yet be appreciated that, also can adopt negative photoresistance, this moment, correspondingly the gray tone mask that is used to expose will be made corresponding change equally, promptly and the light transmittance of first reticle field 31 greater than the light transmittance of the 3rd reticle field 33, the light transmittance of the 3rd reticle field 33 is greater than the light transmittance of second reticle field 32, and second reticle field 32 is light tight fully.Owing to be negative photoresistance, photoresist layer over against first area 221 except that the part over against through hole 13 because unexposed and etched away fully, first area 221 is fallen over against the part of through hole 13 and second area 222 are partially-etched, and the etch depth of second area 222 is darker over against the part of through hole 13 than first area 221.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be not break away from the technical solution of the present invention content, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.

Claims (10)

1. method that on semiconductor device, form to connect salient point, this semiconductor device comprises a substrate, a connection gasket and a protective layer, this connection gasket exposes from one of being formed in this protective layer through hole:
The deposition first salient point limited metal level is to insert this through hole on this protective layer;
Form photoresist layer in this substrate, this photoresist layer comprises first area and second area, and this first salient point limited metal level is covered under this first area;
Remove this first area except that the part over against this through hole, thereby form a plurality of photoresistance kernels, and remove this second area of part, thereby form a photoresistance protective layer;
Deposit the second salient point limited metal level at those photoresistance core surfaces;
Connect metal level at this second salient point limited layer on surface of metal deposition salient point;
Removing this salient point of part connects metal level and keeps the part that coats those photoresistance kernels; And
Remove this first, second salient point limited metal level of part and keep the part that comprises those photoresistance kernels, thereby obtain a plurality of connection salient points that are separated from each other on the surface of this semiconductor device.
2. according to the method for claim 1, it is characterized in that the method for removing this photoresist layer of part comprises:
Simultaneously whole this photoresist layer is carried out exposure-processed, wherein this first area is different with the exposure of this second area over against the part of this through hole; And
This photoresist layer is carried out development treatment, thereby form those photoresistance kernels and this photoresistance protective layer.
3. according to the method for claim 2, it is characterized in that, this photoresist layer is positive photoresistance, and when being carried out exposure-processed, adopts this photoresist layer gray tone mask, this gray tone mask comprises first reticle field over against this through hole, over against this first area except that second reticle field of the part over against this through hole, and over against the 3rd reticle field of this second area, and the light transmittance of second reticle field is greater than the light transmittance of the 3rd reticle field, and the light transmittance of the 3rd reticle field is greater than the light transmittance of first reticle field.
4. according to the method for claim 2, it is characterized in that, this photoresist layer is negative photoresistance, and when being carried out exposure-processed, adopts this photoresist layer gray tone mask, this gray tone mask comprises first reticle field over against this through hole, over against this first area except that second reticle field of the part over against this through hole, and over against the 3rd reticle field of this second area, and the light transmittance of second reticle field is less than the light transmittance of the 3rd reticle field, and the light transmittance of the 3rd reticle field is less than the light transmittance of first reticle field.
5. according to the method for claim 1, it is characterized in that this first salient point limited metal level and the second salient point metal level are the titanium-tungsten layer.
6. according to the method for claim 5, it is characterized in that this first salient point limited metal level and the second salient point metal level adopt the mode of sputter to deposit.
7. according to the method for claim 1, it is characterized in that this photoresist layer is a polyimides.
8. according to the method for claim 1, it is characterized in that, the etch depth of this photoresist layer second area greater than this first area over against 4 to 8 microns of the etch depths of the part of this through hole.
9. according to the method for claim 1, it is characterized in that the thickness of this photoresistance kernel is 7 to 10 microns.
10. according to the method for claim 1, it is characterized in that the thickness of this photoresistance protective layer is 2 to 3 microns.
CN2009101490647A 2009-06-15 2009-06-15 Method of forming connecting salient points on semiconductor device Pending CN101924045A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103809103A (en) * 2012-11-08 2014-05-21 中芯国际集成电路制造(上海)有限公司 Chip failpoint positioning method
US9704818B1 (en) * 2016-07-06 2017-07-11 Nanya Technology Corporation Semiconductor structure and manufacturing method thereof
CN107275380A (en) * 2017-06-14 2017-10-20 厦门市三安集成电路有限公司 A kind of metal level of compound semiconductor and preparation method thereof
US10103114B2 (en) 2016-09-21 2018-10-16 Nanya Technology Corporation Semiconductor structure and manufacturing method thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103809103A (en) * 2012-11-08 2014-05-21 中芯国际集成电路制造(上海)有限公司 Chip failpoint positioning method
CN103809103B (en) * 2012-11-08 2017-02-08 中芯国际集成电路制造(上海)有限公司 Chip failpoint positioning method
US9704818B1 (en) * 2016-07-06 2017-07-11 Nanya Technology Corporation Semiconductor structure and manufacturing method thereof
US10103114B2 (en) 2016-09-21 2018-10-16 Nanya Technology Corporation Semiconductor structure and manufacturing method thereof
US10431559B2 (en) 2016-09-21 2019-10-01 Nanya Technology Corporation Method for manufacturing a semiconductor structure
CN107275380A (en) * 2017-06-14 2017-10-20 厦门市三安集成电路有限公司 A kind of metal level of compound semiconductor and preparation method thereof

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Application publication date: 20101222