CN106803482A - A kind of method for reducing crystal round fringes yield test problem - Google Patents
A kind of method for reducing crystal round fringes yield test problem Download PDFInfo
- Publication number
- CN106803482A CN106803482A CN201710079115.8A CN201710079115A CN106803482A CN 106803482 A CN106803482 A CN 106803482A CN 201710079115 A CN201710079115 A CN 201710079115A CN 106803482 A CN106803482 A CN 106803482A
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- photoresistance
- crystal round
- round fringes
- wafer
- test problem
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
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- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention provides a kind of method for reducing crystal round fringes yield test problem, including：First step：Obtain and the photoetching patterned photomask to be used and patterning photoresistance are performed to the passivation layer of wafer；Second step：The patterned photomask is become anti-phase to obtain anti-phase patterned photomask, and in the positive and negative attribute change for keeping causing the patterning photoresistance in the case that photoresistance pattern is constant to obtain opposite patterning photoresistance；Third step：Using the anti-phase patterned photomask and the opposite patterning photoresistance, photoetching is performed to wafer.In the method for reducing crystal round fringes yield test problem of the invention, the light shield and photoresistance of passivation layer are all become anti-phase, so both maintained in wafer, remove the predetermined portions that marginal position starts, other parts figure is constant；And predetermined portions are played from edge, passivation layer is remained, and will not thus produce the problem of the false failure of test.
Description
Technical field
The present invention relates to field of semiconductor manufacture and semiconductor test field, it is more particularly related to a kind of
Method for reducing crystal round fringes yield test problem.
Background technology
Wafer-level test (CP Test, also referred to as wafer-level test) is an important step of semiconductor fabrication process.Adopt
The device feature of early stage can be obtained with wafer-level test.
But, some products can run into the problem of the low yield of crystal round fringes, or even some when wafer yield test is carried out
The big product yield of single chip area is low to 5%.This is undesirable appearance.
In fact, this low yield of crystal round fringes is relevant with test acupuncture treatment.Specifically, the incomplete core of crystal round fringes
Other complete chips of (multi-chip is tested simultaneously) are not due directly to complete when piece (partial die) can cause once to have an acupuncture treatment
Whole chip stitch electric leakage, is thus directly judged failure.
Fig. 1 schematically show according to the metal level of prior art and the wafer edge exposure of passivation layer and side washing away from
From knot schematic diagram.As shown in figure 1, in the prior art, side washing (WEE (the wafer edge of metal level and passivation layer
Exposure, wafer edge exposure)/EBR (edge bead remove, crystal round fringes side washing during photoetching)) distance is from side
The scope of genesis 2.8mm, the photoetching side washing of via layer is the scope of the 1.0mm from edge.During through hole tungsten plug film, machinery sets
Put to be risen in crystal round fringes and do not grown in the range of 1.5mm.So, risen in the range of 1.5mm to 2.8mm at edge, physics material
It is the dielectric layer and tungsten plug between metal, after the tungsten plug of through hole is by wafer edge exposure, crystal round fringes 0-2.8mm portions
The passivation layer for dividing is removed.Thus, the low yield of this crystal round fringes relevant with test acupuncture treatment as described above can be caused.
Thus, in semiconductor test field, it is desirable to be able to which providing one kind can efficiently reduce the survey of crystal round fringes yield
The method why inscribed.
The content of the invention
The technical problems to be solved by the invention are directed to and there is drawbacks described above in the prior art, there is provided one kind can be reduced
The method of crystal round fringes yield test problem.
In order to realize above-mentioned technical purpose, according to the present invention, there is provided one kind is asked for reducing the test of crystal round fringes yield
The method of topic, including：
First step：Obtain and the photoetching patterned photomask to be used and patterning light are performed to the passivation layer of wafer
Resistance；
Second step：The patterned photomask is become anti-phase to obtain anti-phase patterned photomask, and is being kept
Cause the positive and negative attribute change of the patterning photoresistance to obtain opposite patterning photoresistance in the case that photoresistance pattern is constant；
Third step：Using the anti-phase patterned photomask and the opposite patterning photoresistance, light is performed to wafer
Carve.
Preferably, in the method for reducing crystal round fringes yield test problem, using the patterned photomask
Photoetching is performed to the passivation layer of wafer with the patterning photoresistance, the brilliant to distance from crystal round fringes of the passivation layer of wafer will be caused
Passivation layer region at the radius of rounded edge preset distance between annulus is removed.
Preferably, in the method for reducing crystal round fringes yield test problem, the preset distance is
2.8mm。
Preferably, in the method for reducing crystal round fringes yield test problem, the patterned photomask is formed
Mask pattern become the openwork part of the anti-phase patterned photomask.
Preferably, in the method for reducing crystal round fringes yield test problem, the anti-phase patterning light
Cover the openwork part that the mask pattern for being formed is the patterned photomask.
Preferably, in the method for reducing crystal round fringes yield test problem, the patterning photoresistance is just
Photoresistance, the opposite patterning photoresistance is negative photoresistance.It is further preferred that described for reducing the test of crystal round fringes yield
In the method for problem, in the second step so that the patterning photoresistance becomes negative photoresistance from positive photoresistance.That is, in the pattern
In the case that change photoresistance is positive photoresistance, in the second step so that the patterning photoresistance becomes negative photoresistance from positive photoresistance.
Preferably, in the method for reducing crystal round fringes yield test problem, the patterning photoresistance is negative
Photoresistance, the opposite patterning photoresistance is positive photoresistance.It is further preferred that described for reducing the test of crystal round fringes yield
In the method for problem, in the second step so that the patterning photoresistance becomes positive photoresistance from negative photoresistance.That is, in the pattern
It is in the case of bearing photoresistance, in the second step to change photoresistance so that the patterning photoresistance becomes positive photoresistance from negative photoresistance.
Preferably, it is described for reducing wafer side in the method for reducing crystal round fringes yield test problem
The method of edge yield test problem is used for the wafer-level test of wafer.
In the method for reducing crystal round fringes yield test problem of the invention, the passivation layer of crystal round fringes is protected
Stay, and height will not be protruded, and not interfere with the follow-up processing procedure of wafer (for example testing, the processing procedure such as scribing)；Due to passivation
Layer is remained, would not occur to occur in the prior art certain is complete when during wafer-level test due to having an acupuncture treatment together
The tungsten for exposing at the edge of whole chip and cause the electric leakage between pin and pin, so as to cause other chips having an acupuncture treatment together to be judged to
It is the problem of failure.In the method for reducing crystal round fringes yield test problem of the invention, by the light of passivation layer
Cover and photoresistance all become anti-phase, have so both maintained in wafer, and the predetermined portions that removing marginal position starts are (for example, 2.8mm
Part), other parts figure is constant；And predetermined portions (part of 2.8mm) are played from edge, passivation layer is remained；This
Sample would not produce the problem of the false failure of test.It is of the invention can for reducing the method for crystal round fringes yield test problem
It is advantageously used in the wafer-level test of wafer.
Brief description of the drawings
With reference to accompanying drawing, and by reference to following detailed description, it will more easily have more complete understanding to the present invention
And its adjoint advantages and features is more easily understood, wherein：
Fig. 1 schematically show according to the metal level of prior art and the wafer edge exposure of passivation layer and side washing away from
From knot schematic diagram.
Fig. 2 schematically show metal level according to the preferred embodiment of the invention and passivation layer wafer edge exposure and
The knot schematic diagram of the distance of side washing.
Fig. 3 schematically shows according to the preferred embodiment of the invention for reducing crystal round fringes yield test problem
The flow chart of method.
It should be noted that accompanying drawing is used to illustrate the present invention, it is not intended to limit the present invention.Note, represent that the accompanying drawing of structure can
Can be not necessarily drawn to scale.Also, in accompanying drawing, same or similar element indicates same or similar label.
Specific embodiment
In order that present disclosure is more clear and understandable, with reference to specific embodiments and the drawings to of the invention interior
Appearance is described in detail.
The present inventor proposes, is asked for reducing the test of crystal round fringes yield according to the preferred embodiment of the invention
In the method for topic, the light shield and photoresistance of passivation layer are all become anti-phase, so both maintained in wafer, removed marginal position and open
The predetermined portions of beginning, other parts figure is constant；And predetermined portions are played from edge, passivation layer is remained, and thus will not
Produce the problem of the false failure of test.
Fig. 3 schematically shows according to the preferred embodiment of the invention for reducing crystal round fringes yield test problem
The flow chart of method.
Specifically, as shown in figure 3, according to the preferred embodiment of the invention for reducing crystal round fringes yield test problem
Method include the following step that performs successively：
First step S1：Obtain and the photoetching patterned photomask to be used and patterning light are performed to the passivation layer of wafer
Resistance；
Preferably, wherein the patterning photoresistance is positive photoresistance.
Wherein, photoetching is performed to the passivation layer of wafer using the patterned photomask and the patterning photoresistance, will be caused
The passivation layer of wafer from crystal round fringes to annulus at the radius apart from crystal round fringes preset distance between passivation
Layer region is removed.
Preferably, the preset distance is 2.8mm.Certainly, the preset distance is also likely to be other appropriate numerical value or number
Value scope.
Second step S2：The patterned photomask is become anti-phase to obtain anti-phase patterned photomask, and is being protected
Hold photoresistance pattern it is constant in the case of so that it is described patterning photoresistance positive and negative attribute change to obtain opposite patterning photoresistance；
Anti-phase for patterned photomask, specifically, the mask pattern that the patterned photomask is formed becomes described anti-phase
Patterned photomask openwork part；And specifically, the mask pattern that the anti-phase patterned photomask is formed is the figure
The openwork part of case light shield.
For example, in some specific embodiments, in the case where the patterning photoresistance is positive photoresistance, in second step S2
In so that the patterning photoresistance becomes negative photoresistance from positive photoresistance.For example, in other specific embodiments, in the patterning
In the case that photoresistance is negative photoresistance, in second step S2 so that the patterning photoresistance becomes positive photoresistance from negative photoresistance.One
As, it is preferable that the patterning photoresistance is positive photoresistance, and the opposite patterning photoresistance is negative photoresistance.
Third step S3：Using the anti-phase patterned photomask and the opposite patterning photoresistance, wafer is performed
Photoetching.
Fig. 2 schematically show metal level according to the preferred embodiment of the invention and passivation layer wafer edge exposure and
The knot schematic diagram of the distance of side washing.
As shown in Fig. 2 in the method for reducing crystal round fringes yield test problem according to the preferred embodiment of the invention
In, the passivation layer of crystal round fringes is remained, and height will not protrude, do not interfere with the follow-up processing procedure of wafer (for example test,
The processing procedures such as scribing)；Because passivation layer is remained, would not occur to occur in the prior art during wafer-level test by
In together have an acupuncture treatment when certain incomplete chip edge the tungsten for exposing and cause the electric leakage between pin and pin, so as to cause one
Other chips for playing acupuncture treatment are judged to the problem of failure.According to the preferred embodiment of the invention for reducing crystal round fringes yield
In the method for test problem, the light shield and photoresistance of passivation layer are all become anti-phase, so both maintained in wafer, remove edge
The predetermined portions (for example, part of 2.8mm) that position starts, other parts figure is constant；And play predetermined portions from edge
(part of 2.8mm), passivation layer is remained；The problem of the false failure of test will not thus be produced.
It is according to the preferred embodiment of the invention to be advantageously used for for reducing the method for crystal round fringes yield test problem
The wafer-level test of wafer.
Furthermore, it is necessary to explanation, unless stated otherwise or points out, term " first " otherwise in specification, " the
Two ", description such as " 3rd " is used only for distinguishing each component, element, step in specification etc., without being intended to indicate that each
Logical relation or ordinal relation between component, element, step etc..
Although it is understood that the present invention is disclosed as above with preferred embodiment, but above-described embodiment and being not used to
Limit the present invention.For any those of ordinary skill in the art, in the case where technical solution of the present invention ambit is not departed from,
Many possible variations and modification are all made to technical solution of the present invention using the technology contents of the disclosure above, or is revised as
With the Equivalent embodiments of change.Therefore, every content without departing from technical solution of the present invention, according to technical spirit pair of the invention
Any simple modification, equivalent variation and modification made for any of the above embodiments, still fall within the scope of technical solution of the present invention protection
It is interior.
And should also be understood that the present invention is not limited thereto place description specific method, compound, material, system
Technology, usage and application are made, they can change.It should also be understood that term described herein is used merely to describe specific
Embodiment, rather than for limiting the scope of the present invention.Must be noted that herein and being used in appended claims
Singulative " one ", " one kind " and " being somebody's turn to do " include complex reference, unless context explicitly indicates that contrary.Therefore, example
Such as, the citation to one or more elements is meaned to the citation of " element ", and including known to those skilled in the art
Its equivalent.Similarly, as another example, the citation of " step " or " device " is meaned to one or
The citation of multiple steps or device, and potentially include secondary step and second unit.Should be managed with broadest implication
All conjunctions that solution is used.Therefore, word "or" should be understood that the definition with logical "or", rather than logical exclusive-OR
Definition, unless context explicitly indicates that contrary.Structure described herein will be understood as also quoting from the function of the structure
Equivalent.Can be interpreted that approximate language should be understood like that, unless context explicitly indicates that contrary.
Claims (10)
1. a kind of method for reducing crystal round fringes yield test problem, it is characterised in that including：
First step：Obtain and the photoetching patterned photomask to be used and patterning photoresistance are performed to the passivation layer of wafer；
Second step：The patterned photomask is become anti-phase to obtain anti-phase patterned photomask, and is keeping photoresistance
Cause the positive and negative attribute change of the patterning photoresistance to obtain opposite patterning photoresistance in the case that pattern is constant；
Third step：Using the anti-phase patterned photomask and the opposite patterning photoresistance, photoetching is performed to wafer.
2. the method for reducing crystal round fringes yield test problem according to claim 1, it is characterised in that utilize institute
State patterned photomask and the patterning photoresistance and photoetching performed to the passivation layer of wafer, by cause the passivation layer of wafer from wafer
Passivation layer region between edge to annulus at the radius apart from crystal round fringes preset distance is removed.
3. the method for reducing crystal round fringes yield test problem according to claim 1 and 2, it is characterised in that institute
Preset distance is stated for 2.8mm.
4. the method for reducing crystal round fringes yield test problem according to claim 1 and 2, it is characterised in that institute
The mask pattern for stating patterned photomask formation becomes the openwork part of the anti-phase patterned photomask.
5. the method for reducing crystal round fringes yield test problem according to claim 1 and 2, it is characterised in that institute
The mask pattern for stating anti-phase patterned photomask formation is the openwork part of the patterned photomask.
6. the method for reducing crystal round fringes yield test problem according to claim 1 and 2, it is characterised in that institute
It is positive photoresistance to state patterning photoresistance, and the opposite patterning photoresistance is negative photoresistance.
7. the method for reducing crystal round fringes yield test problem according to claim 6, it is characterised in that second
In step so that the patterning photoresistance becomes negative photoresistance from positive photoresistance.
8. the method for reducing crystal round fringes yield test problem according to claim 1 and 2, it is characterised in that institute
It is negative photoresistance to state patterning photoresistance, and the opposite patterning photoresistance is positive photoresistance.
9. the method for reducing crystal round fringes yield test problem according to claim 8, it is characterised in that second
In step so that the patterning photoresistance becomes positive photoresistance from negative photoresistance.
10. the method for reducing crystal round fringes yield test problem according to claim 1 and 2, it is characterised in that institute
Stating the method for reducing crystal round fringes yield test problem is used for the wafer-level test of wafer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710079115.8A CN106803482B (en) | 2017-02-14 | 2017-02-14 | Method for reducing wafer edge yield test problem |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710079115.8A CN106803482B (en) | 2017-02-14 | 2017-02-14 | Method for reducing wafer edge yield test problem |
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| CN106803482A true CN106803482A (en) | 2017-06-06 |
| CN106803482B CN106803482B (en) | 2020-01-24 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108417476A (en) * | 2018-02-07 | 2018-08-17 | 上海华虹宏力半导体制造有限公司 | Wafer top layer oxide layer processing method |
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| EP0935280A1 (en) * | 1998-02-04 | 1999-08-11 | Canon Kabushiki Kaisha | SOI substrate and method of manufacturing the same |
| US20080084550A1 (en) * | 2006-10-06 | 2008-04-10 | Wafertech, Llc | High throughput wafer stage design for optical lithography exposure apparatus |
| US20090305169A1 (en) * | 2008-06-04 | 2009-12-10 | Katsutoshi Kobayashi | Method for manufacturing semiconductor device |
| CN101916722A (en) * | 2010-07-23 | 2010-12-15 | 上海宏力半导体制造有限公司 | Method for preventing metallic coatings at edges of wafers from peeling |
| US20120268721A1 (en) * | 2011-04-21 | 2012-10-25 | Macronix International Co., Ltd. | Apparatus for and method of wafer edge exposure |
| CN105161412A (en) * | 2015-08-31 | 2015-12-16 | 上海华力微电子有限公司 | Method for improving wafer edge product yield |
-
2017
- 2017-02-14 CN CN201710079115.8A patent/CN106803482B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0935280A1 (en) * | 1998-02-04 | 1999-08-11 | Canon Kabushiki Kaisha | SOI substrate and method of manufacturing the same |
| US20080084550A1 (en) * | 2006-10-06 | 2008-04-10 | Wafertech, Llc | High throughput wafer stage design for optical lithography exposure apparatus |
| US20090305169A1 (en) * | 2008-06-04 | 2009-12-10 | Katsutoshi Kobayashi | Method for manufacturing semiconductor device |
| CN101916722A (en) * | 2010-07-23 | 2010-12-15 | 上海宏力半导体制造有限公司 | Method for preventing metallic coatings at edges of wafers from peeling |
| US20120268721A1 (en) * | 2011-04-21 | 2012-10-25 | Macronix International Co., Ltd. | Apparatus for and method of wafer edge exposure |
| CN105161412A (en) * | 2015-08-31 | 2015-12-16 | 上海华力微电子有限公司 | Method for improving wafer edge product yield |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108417476A (en) * | 2018-02-07 | 2018-08-17 | 上海华虹宏力半导体制造有限公司 | Wafer top layer oxide layer processing method |
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| CN106803482B (en) | 2020-01-24 |
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