CN106803482B - Method for reducing wafer edge yield test problem - Google Patents
Method for reducing wafer edge yield test problem Download PDFInfo
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- CN106803482B CN106803482B CN201710079115.8A CN201710079115A CN106803482B CN 106803482 B CN106803482 B CN 106803482B CN 201710079115 A CN201710079115 A CN 201710079115A CN 106803482 B CN106803482 B CN 106803482B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
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Abstract
The invention provides a method for reducing wafer edge yield test problems, which comprises the following steps: the first step is as follows: obtaining a patterned photomask and a patterned photoresist which are to be adopted for carrying out photoetching on a passivation layer of a wafer; the second step is as follows: changing the patterned photomask into an inverse patterned photomask to obtain an inverse patterned photomask, and changing the positive and negative properties of the patterned photoresist under the condition of keeping the photoresist pattern unchanged to obtain an inverse patterned photoresist; the third step: and performing photoetching on the wafer by using the reverse patterned photomask and the reverse patterned photoresist. In the method for reducing the wafer edge yield test problem, the photomask and the photoresist of the passivation layer are changed into opposite phases, so that the preset part of the wafer from which the edge position begins is removed, and the patterns of other parts are unchanged; and the passivation layer remains from the edge to the predetermined portion, so that the problem of test false failure does not occur.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing and semiconductor testing, and more particularly to a method for reducing wafer edge yield test problems.
Background
Wafer level testing (CP Test, also referred to as wafer level testing) is an important step in semiconductor manufacturing processes. Early device characterization can be achieved using wafer level testing.
However, some products have a low yield at the edge of the wafer when performing wafer yield test, and even some products with large single chip area have a yield as low as 5%. This is undesirable.
In fact, such low wafer edge yield is associated with test pins. Specifically, an incomplete chip (partial die) on the edge of the wafer may cause other complete chips in one time of needle insertion (multi-chip simultaneous test) to be directly determined to be failed due to leakage of the incomplete chip pins.
Fig. 1 schematically shows a junction diagram of the distances of wafer edge exposure and edge cleaning of a metal layer and a passivation layer according to the prior art. As shown in fig. 1, in the prior art, the distance between the metal layer and the passivation layer (we (wafer edge exposure)/EBR (edge bead removal) is 2.8mm from the edge, and the photolithographic edge bead of the via layer is 1.0mm from the edge. When the through hole tungsten plug stretches the film, the mechanical setting does not grow within the range of 1.5mm from the edge of the wafer. Thus, in the range of 1.5mm to 2.8mm from the edge, the physical materials are a dielectric layer between metals and a tungsten plug, and after the tungsten plug of the through hole is exposed at the edge of the wafer, the passivation layer at the 0-2.8mm part of the edge of the wafer is removed. This results in such low wafer edge yield associated with test pins as described above.
Accordingly, in the field of semiconductor testing, it is desirable to provide a method that can effectively reduce wafer edge yield test problems.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a method capable of reducing the wafer edge yield test problem, aiming at the above defects in the prior art.
In order to achieve the above technical object, according to the present invention, there is provided a method for reducing wafer edge yield test problems, comprising:
the first step is as follows: obtaining a patterned photomask and a patterned photoresist which are to be adopted for carrying out photoetching on a passivation layer of a wafer;
the second step is as follows: changing the patterned photomask into an inverse patterned photomask to obtain an inverse patterned photomask, and changing the positive and negative properties of the patterned photoresist under the condition of keeping the photoresist pattern unchanged to obtain an inverse patterned photoresist;
the third step: and performing photoetching on the wafer by using the reverse patterned photomask and the reverse patterned photoresist.
Preferably, in the method for reducing the wafer edge yield test problem, performing photolithography on the passivation layer of the wafer by using the patterned photomask and the patterned photoresist removes a passivation layer region of the passivation layer of the wafer in a range from the wafer edge to a circle at a radius a predetermined distance from the wafer edge.
Preferably, in the method for reducing wafer edge yield test problems, the predetermined distance is 2.8 mm.
Preferably, in the method for reducing wafer edge yield test problems, the mask pattern formed by the patterned mask becomes the hollowed-out part of the inverse patterned mask.
Preferably, in the method for reducing wafer edge yield test problems, the mask pattern formed by the inverse patterned mask is a hollow part of the patterned mask.
Preferably, in the method for reducing wafer edge yield test problems, the patterned photoresist is a positive photoresist and the opposite patterned photoresist is a negative photoresist. Further preferably, in the method for reducing wafer edge yield test problems, in the second step, the patterned photoresist is changed from a positive photoresist to a negative photoresist. That is, in the case where the patterned photoresist is a positive photoresist, the patterned photoresist is changed from the positive photoresist to a negative photoresist in the second step.
Preferably, in the method for reducing wafer edge yield test problems, the patterned photoresist is a negative photoresist and the opposite patterned photoresist is a positive photoresist. Further preferably, in the method for reducing wafer edge yield test problems, in the second step, the patterned photoresist is changed from a negative photoresist to a positive photoresist. That is, in the case where the patterned photoresist is a negative photoresist, the patterned photoresist is changed from the negative photoresist to a positive photoresist in the second step.
Preferably, in the method for reducing wafer edge yield test problems, the method for reducing wafer edge yield test problems is used for wafer level testing of wafers.
In the method for reducing the wafer edge yield test problem according to the present invention, the passivation layer on the wafer edge is remained and has a height not protruding, which does not affect the subsequent processes (such as testing, scribing, etc.) of the wafer; due to the fact that the passivation layer is reserved, the problem that in the prior art, when the chips are pricked together, the exposed tungsten on the edge of a certain incomplete chip causes electric leakage between the pins, and other chips pricked together are judged to be invalid can not occur. In the method for reducing the wafer edge yield test problem, the photomask and the photoresist of the passivation layer are changed into opposite phases, so that the pattern of other parts is not changed even a predetermined part (for example, a part of 2.8 mm) of the wafer from which the edge position begins is removed; and the passivation layer remains from the edge to a predetermined portion (2.8mm portion); this does not create a problem of test false failures. The method for reducing wafer edge yield test problems according to the present invention can be advantageously used for wafer level testing of wafers.
Drawings
A more complete understanding of the present invention, and the attendant advantages and features thereof, will be more readily understood by reference to the following detailed description when considered in conjunction with the accompanying drawings wherein:
fig. 1 schematically shows a junction diagram of the distances of wafer edge exposure and edge cleaning of a metal layer and a passivation layer according to the prior art.
Fig. 2 schematically shows a junction diagram of the distances of wafer edge exposure and edge cleaning of the metal layer and the passivation layer according to a preferred embodiment of the present invention.
Fig. 3 schematically illustrates a flow chart of a method for reducing wafer edge yield test problems in accordance with a preferred embodiment of the present invention.
It is to be noted, however, that the appended drawings illustrate rather than limit the invention. It is noted that the drawings representing structures may not be drawn to scale. Also, in the drawings, the same or similar elements are denoted by the same or similar reference numerals.
Detailed Description
In order that the present disclosure may be more clearly and readily understood, reference will now be made in detail to the present disclosure as illustrated in the accompanying drawings.
The inventor of the present invention proposes that in the method for reducing wafer edge yield test problems according to the preferred embodiment of the present invention, the photo mask and the photo resist of the passivation layer are both changed into opposite phases, so that the predetermined portion of the wafer from which the edge position starts is removed, and the other portion of the pattern is kept unchanged; and the passivation layer remains from the edge to the predetermined portion, so that the problem of test false failure does not occur.
Fig. 3 schematically illustrates a flow chart of a method for reducing wafer edge yield test problems in accordance with a preferred embodiment of the present invention.
Specifically, as shown in fig. 3, the method for reducing wafer edge yield test problems according to the preferred embodiment of the present invention comprises the following steps performed in sequence:
first step S1: obtaining a patterned photomask and a patterned photoresist which are to be adopted for carrying out photoetching on a passivation layer of a wafer;
preferably, wherein the patterned photoresist is a positive photoresist.
And performing photoetching on the passivation layer of the wafer by using the patterned photomask and the patterned photoresist, so that the passivation layer area of the wafer in the range from the edge of the wafer to a circle at a radius which is a preset distance away from the edge of the wafer is removed.
Preferably, the predetermined distance is 2.8 mm. Of course, the predetermined distance may be other suitable values or ranges of values.
Second step S2: changing the patterned photomask into an inverse patterned photomask to obtain an inverse patterned photomask, and changing the positive and negative properties of the patterned photoresist under the condition of keeping the photoresist pattern unchanged to obtain an inverse patterned photoresist;
for the inverse phase of the patterned photomask, specifically, the photomask pattern formed by the patterned photomask becomes the hollow part of the inverse patterned photomask; and specifically, the mask pattern formed by the inverse patterned mask is a hollowed-out portion of the patterned mask.
For example, in some embodiments, in the case that the patterned photoresist is a positive photoresist, the patterned photoresist is changed from the positive photoresist to a negative photoresist in the second step S2. For example, in other embodiments, in the case that the patterned photoresist is a negative photoresist, the patterned photoresist is changed from the negative photoresist to a positive photoresist in the second step S2. In general, it is preferred that the patterned photoresist is a positive photoresist and the opposite patterned photoresist is a negative photoresist.
Third step S3: and performing photoetching on the wafer by using the reverse patterned photomask and the reverse patterned photoresist.
Fig. 2 schematically shows a junction diagram of the distances of wafer edge exposure and edge cleaning of the metal layer and the passivation layer according to a preferred embodiment of the present invention.
As shown in fig. 2, in the method for reducing the wafer edge yield test problem according to the preferred embodiment of the present invention, the passivation layer on the wafer edge remains and has a height that does not protrude, and does not affect the subsequent processes (e.g., testing, scribing, etc.) of the wafer; due to the fact that the passivation layer is reserved, the problem that in the prior art, when the chips are pricked together, the exposed tungsten on the edge of a certain incomplete chip causes electric leakage between the pins, and other chips pricked together are judged to be invalid can not occur. In the method for reducing the wafer edge yield test problem according to the preferred embodiment of the invention, the photomask and the photoresist of the passivation layer are changed into opposite phases, so that the pattern of other parts is not changed even a predetermined part (for example, a part of 2.8 mm) of the wafer from which the edge position begins is removed; and the passivation layer remains from the edge to a predetermined portion (2.8mm portion); this does not create a problem of test false failures.
The method for reducing wafer edge yield test problems according to the preferred embodiments of the present invention may be advantageously used for wafer level testing of wafers.
In addition, it should be noted that the terms "first", "second", "third", and the like in the specification are used for distinguishing various components, elements, steps, and the like in the specification, and are not used for indicating a logical relationship or a sequential relationship between the various components, elements, steps, and the like, unless otherwise specified or indicated.
It is to be understood that while the present invention has been described in conjunction with the preferred embodiments thereof, it is not intended to limit the invention to those embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
It is to be further understood that the present invention is not limited to the particular methodology, compounds, materials, manufacturing techniques, uses, and applications described herein, as such may, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "an element" means a reference to one or more elements and includes equivalents thereof known to those skilled in the art. Similarly, as another example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. Thus, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Structures described herein are to be understood as also referring to functional equivalents of such structures. Language that can be construed as approximate should be understood as such unless the context clearly dictates otherwise.
Claims (10)
1. A method for reducing wafer edge yield test problems, comprising:
the first step is as follows: obtaining a patterned photomask and a patterned photoresist which are to be adopted for carrying out photoetching on a passivation layer of a wafer;
the second step is as follows: changing the patterned photomask into an inverse patterned photomask to obtain an inverse patterned photomask, and changing the positive and negative properties of the patterned photoresist under the condition of keeping the photoresist pattern unchanged to obtain an inverse patterned photoresist;
the third step: performing lithography on a wafer by using the reverse patterned photomask and the reverse patterned photoresist; so that the passivation layer on the tungsten plug is remained from the edge of the wafer to the predetermined portion.
2. The method of claim 1, wherein performing photolithography on the passivation layer of the wafer using the patterned mask and the patterned photoresist causes a region of the passivation layer of the wafer in a range from the edge of the wafer to a ring at a radius a predetermined distance from the edge of the wafer to be removed.
3. The method of claim 2, wherein the predetermined distance is 2.8 mm.
4. The method as claimed in claim 1 or 2, wherein the patterned mask forms a mask pattern that becomes a hollow portion of the inverse patterned mask.
5. The method as claimed in claim 1 or 2, wherein the inverse patterned mask forms a mask pattern that is a hollow portion of the patterned mask.
6. The method as claimed in claim 1 or 2, wherein the patterned photoresist is a positive photoresist and the opposite patterned photoresist is a negative photoresist.
7. The method as claimed in claim 6, wherein the patterned photoresist is changed from a positive photoresist to a negative photoresist in the second step.
8. The method as claimed in claim 1 or 2, wherein the patterned photoresist is a negative photoresist and the opposite patterned photoresist is a positive photoresist.
9. The method as claimed in claim 8, wherein the patterned photoresist is changed from a negative photoresist to a positive photoresist in the second step.
10. The method of claim 1 or 2, wherein the method is used for wafer level testing of wafers.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710079115.8A CN106803482B (en) | 2017-02-14 | 2017-02-14 | Method for reducing wafer edge yield test problem |
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| CN201710079115.8A CN106803482B (en) | 2017-02-14 | 2017-02-14 | Method for reducing wafer edge yield test problem |
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| CN106803482B true CN106803482B (en) | 2020-01-24 |
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| CN108417476A (en) * | 2018-02-07 | 2018-08-17 | 上海华虹宏力半导体制造有限公司 | Wafer top layer oxide layer processing method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0935280A1 (en) * | 1998-02-04 | 1999-08-11 | Canon Kabushiki Kaisha | SOI substrate and method of manufacturing the same |
| CN101916722A (en) * | 2010-07-23 | 2010-12-15 | 上海宏力半导体制造有限公司 | Method for preventing metallic coatings at edges of wafers from peeling |
| CN105161412A (en) * | 2015-08-31 | 2015-12-16 | 上海华力微电子有限公司 | Method for improving wafer edge product yield |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7659965B2 (en) * | 2006-10-06 | 2010-02-09 | Wafertech, Llc | High throughput wafer stage design for optical lithography exposure apparatus |
| JP2009295716A (en) * | 2008-06-04 | 2009-12-17 | Toshiba Corp | Method for manufacturing semiconductor device and substrate processing apparatus |
| US8804096B2 (en) * | 2011-04-21 | 2014-08-12 | Macronix International Co., Ltd. | Apparatus for and method of wafer edge exposure |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0935280A1 (en) * | 1998-02-04 | 1999-08-11 | Canon Kabushiki Kaisha | SOI substrate and method of manufacturing the same |
| CN101916722A (en) * | 2010-07-23 | 2010-12-15 | 上海宏力半导体制造有限公司 | Method for preventing metallic coatings at edges of wafers from peeling |
| CN105161412A (en) * | 2015-08-31 | 2015-12-16 | 上海华力微电子有限公司 | Method for improving wafer edge product yield |
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