CN214098444U - Chip, optical biological identification module formed by chip and electronic equipment - Google Patents
Chip, optical biological identification module formed by chip and electronic equipment Download PDFInfo
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- CN214098444U CN214098444U CN202022591159.9U CN202022591159U CN214098444U CN 214098444 U CN214098444 U CN 214098444U CN 202022591159 U CN202022591159 U CN 202022591159U CN 214098444 U CN214098444 U CN 214098444U
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Abstract
The utility model discloses a chip and optics biological identification module and electronic equipment that this chip formed, include: a chip substrate; the light path structure is arranged on the chip substrate; the metal bonding pad is arranged on the chip substrate and is positioned outside the light path structure; and the first protective layer is positioned between the optical path structure and the chip substrate and between the optical path structure and the metal bonding pad. The utility model discloses the chip has reduced chip function failure or performance degradation scheduling problem.
Description
Technical Field
The utility model discloses the electron field, concretely relates to chip and optics biological identification module and electronic equipment that this chip formed.
Background
As shown in fig. 1-3, the optical circuit structure 2 is completed on a wafer substrate 1, wherein the wafer substrate 1 is a wafer substrate on which a photodiode 4 and a metal pad 3 are processed.
The wafer manufactured by the wafer manufacturing process method is subsequently packaged to form chips, and the problems of chip function failure or performance degradation and the like sometimes occur in the use process of the chips.
SUMMERY OF THE UTILITY MODEL
In order to solve the above-mentioned defect, on the one hand, the utility model provides a wafer manufacturing process manufacturing method, this wafer manufacturing process manufacturing method makes the chip and has reduced the functional failure of chip or performance degradation scheduling problem.
A method of manufacturing a wafer, the method comprising the steps of:
s01: taking a wafer substrate;
s02: forming a first protective layer;
s03: forming a light path structure;
s04: forming a resist mask;
s05: etching silicon nitride on the surface of the bonding pad;
s06: removing the resist mask;
s07: and processing the surface of the bonding pad.
Optionally, the first protection layer is a silicon nitride film layer.
Optionally, in S02, the forming the first protection layer is performed by chemical vapor deposition.
Optionally, the first protective layer has a thickness of 40 nm.
Optionally, between S03 and S04, S031: and forming a second protective layer.
Optionally, the second protective layer is a low temperature oxide layer.
Optionally, the low temperature oxide is silicon dioxide.
Optionally, in S031, the deposition is chemical vapor deposition at 180 ℃.
Optionally, the low-temperature oxide layer has a thickness of 100nm and a refractive index of 1.5.
Optionally, in S05, the etching is high-activity fluorine atom plasma etching generated by using a mixed gas of fluorocarbon and oxygen in a low-pressure glow discharge.
On the one hand, the utility model also provides a chip.
A chip, comprising:
a chip substrate;
the light path structure is arranged on the chip substrate;
the metal bonding pad is arranged on the chip substrate and is positioned outside the light path structure; and
and the first protective layer is positioned between the optical path structure and the chip substrate and between the optical path structure and the metal bonding pad.
Optionally, the chip further includes a second protection layer, and the second protection layer is coated on the optical path structure.
Optionally, the first protection layer is a silicon nitride film layer.
Optionally, the first protective layer has a thickness of 40 nm.
Optionally, the second protective layer is a low temperature oxide layer.
Optionally, the low temperature oxide layer is a silicon dioxide layer.
Optionally, the silica layer has a thickness of 100nm and a refractive index of 1.5.
On the one hand, the utility model also provides an optics biological identification module.
An optical biological identification module comprises the chip.
In one aspect, the utility model also provides an electronic equipment.
An electronic device comprises the optical biological identification module.
Compared with the prior art, the utility model discloses a utility model principle and beneficial effect lie in:
the utility model discloses the people discovers through long-term research that the chip function became invalid or performance degradation scheduling problem appears is because when the encapsulation routing, and welding point contact failure and arouse, and welding point contact failure is the welding point contact failure who causes because metal pad corrodes again, and metal pad corrodes because long-term contact chemicals and air in the manufacturing process of optics biological identification chip back end processing procedure light path structure to lead to the inside metal aluminium pad of chip to appear corroding.
The utility model discloses a solve chip metal pad corrosion problem in biological identification chip manufacturing process, reduce the defect on the pad surface to promote chip reliability and yield.
The utility model discloses before the light path structure is made, at chip surface deposit one deck silicon nitride film as the protective layer. And after the optical path structure process, removing the silicon nitride protective layer on the surface of the metal bonding pad by utilizing fluorine-based or chlorine-based plasma dry etching.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.
FIG. 1 is a schematic of a background art process flow;
FIG. 2 is a schematic diagram of a wafer optical circuit structure before fabrication;
FIG. 3 is a cross-sectional view of a prior art optical path structure after fabrication and before wafer packaging;
FIG. 4 is a schematic view of a process flow diagram of example 1 of the present invention;
FIG. 5 is a partial cross-sectional view of a wafer covered with a silicon nitride film;
FIG. 6 is a partial cross-sectional view of a wafer with completed optical path structure;
FIG. 7 is a partial cross-sectional view of a wafer covered with a resist mask according to example 1;
FIG. 8 is a partial cross-sectional view of a wafer with silicon nitride on the bonding pad etched away according to example 1;
FIG. 9 is a partial cross-sectional view of the wafer after the resist mask has been removed according to example 1;
FIG. 10 is a partial cross-sectional view of the wafer after the argon oxygen plasma treatment in example 1;
FIG. 11 is a schematic view of a process flow diagram of example 2 of the present invention;
FIG. 12 is a partial cross-sectional view of the wafer after depositing a low oxide layer according to example 2;
FIG. 13 is a partial cross-sectional view of a wafer covered with a resist mask according to example 2;
FIG. 14 is a partial cross-sectional view of a wafer with silicon nitride on the bonding pad etched away according to example 2;
FIG. 15 is a partial cross-sectional view of the wafer after the resist mask has been removed according to example 2;
FIG. 16 is a partial cross-sectional view of the wafer after the argon oxygen plasma treatment in example 2;
FIG. 17 is an enlarged view of a chip prepared by the background art process after use;
FIG. 18 is an enlarged view of a used chip prepared by the process of example 2;
FIG. 19 is a diagram illustrating an optical path structure and a bonding pad position;
fig. 20 is a schematic diagram of the chip structure of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The technical solution of the present invention will be described in detail with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
Example 1
Referring to fig. 2 and fig. 4-10, fig. 2 is a schematic partial cross-sectional view of a wafer before a wafer optical path structure is fabricated, fig. 4 is a schematic partial cross-sectional view of the present embodiment, fig. 5 is a schematic partial cross-sectional view of a wafer covered with a silicon nitride film layer, fig. 6 is a schematic partial cross-sectional view of a wafer with an optical path structure completed, fig. 7 is a schematic partial cross-sectional view of a wafer covered with a resist mask, fig. 8 is a schematic partial cross-sectional view of a wafer with a pad etched away, fig. 9 is a schematic partial cross-sectional view of a wafer with the resist mask removed, and fig. 10 is a schematic partial cross-sectional view of a wafer after an argon-oxygen plasma process in the present embodiment.
A method of manufacturing a wafer, the method comprising the steps of:
s01: taking a wafer substrate 1 (see fig. 2), wherein the wafer substrate 1 is a wafer substrate on which a photodiode 4 and a metal pad 3 are processed and the wafer substrate 1 is a wafer substrate.
S02: a silicon nitride film 5 is deposited (see fig. 5), and the silicon nitride film 5 is used to protect the metal pad.
Optionally, the deposition method is a chemical vapor deposition method or other covering method.
Optionally, the thickness of the silicon nitride film layer 5 is 40 nm.
S03: the fabrication of the optical path structure 2 is completed (see fig. 6).
S04: a resist mask 7 (see fig. 7) is formed by photolithography to expose the metal pad 3 position.
S05: and etching silicon nitride on the surface of the bonding pad by using fluorine-based plasma (as shown in figure 8).
S06: the resist mask 7 is removed (see fig. 9).
S07: the pad surface was treated with argon oxygen plasma (see fig. 10).
Example 2
Referring to fig. 2, fig. 5-6 and fig. 11-15, fig. 2 is a schematic partial cross-sectional view of a wafer before a wafer optical path structure is fabricated, fig. 5 is a schematic partial cross-sectional view of a wafer covered with a silicon nitride film layer, fig. 6 is a schematic partial cross-sectional view of a wafer after an optical path structure is completed, fig. 11 is a schematic view of a process flow of the present embodiment, fig. 12 is a schematic partial cross-sectional view of a wafer after a low oxide layer is deposited in the present embodiment, fig. 13 is a schematic partial cross-sectional view of a wafer covered with a resist mask in the present embodiment, fig. 14 is a schematic partial cross-sectional view of a wafer after a pad is etched away in the present embodiment, fig. 15 is a schematic partial cross-sectional view of a wafer after a resist mask is removed in the present embodiment, and fig. 16 is a schematic partial cross-sectional view of a wafer after an argon oxygen plasma is processed in the present embodiment.
A method of manufacturing a wafer, the method comprising the steps of:
s01: taking a wafer substrate 1 (see fig. 2), wherein the wafer substrate 1 is a wafer substrate on which a photodiode 4 and a metal pad 3 are processed and the wafer substrate 1 is a wafer substrate.
S02: a silicon nitride film 5 is deposited (see fig. 5), and the silicon nitride film 5 is used to protect the metal pad.
Optionally, the deposition method is a chemical vapor deposition method or other covering method.
Optionally, the thickness of the silicon nitride film layer 5 is 40 nm.
S03: the fabrication of the optical path structure 2 is completed (see fig. 6).
S031: a low temperature oxide layer 6 is deposited (see fig. 12), the low temperature oxide layer 6 serving to protect the optical path structure 2.
Optionally, the low temperature oxide is silicon dioxide.
Alternatively, the deposition is chemical vapor deposition at 180 ℃.
Alternatively, the low temperature oxide layer 6 is 100nm thick and has a refractive index of 1.5.
S04: a resist mask 7 is formed by photolithography (see fig. 13) to expose the metal pad 3 position.
S05: the pad surface silicon nitride and silicon dioxide are etched using a fluorine based plasma (see fig. 14).
Alternatively, the fluorine-based plasma is a highly reactive fluorine atom plasma generated by a mixed gas of a fluorocarbon and oxygen gas in a low-pressure glow discharge.
When the mixed gas of fluorocarbon and oxygen is used for treating the surface of the metal pad by high-activity fluorine atom plasma generated during low-pressure glow discharge, residual fluorine atoms are eliminated and an oxide film is formed, and the oxide film plays a role in corrosion prevention on the metal pad in a subsequent packaging process so as to reduce defects on the surface of the pad.
S06: the resist mask 7 is removed (see fig. 15).
S07: the pad surface was treated with argon oxygen plasma (see fig. 16).
On the one hand, after the low-temperature oxide layer 6 is formed, the optical path structure 2 is protected from being etched during plasma processing. On the other hand, the low-temperature oxide layer 6 covered on the optical path structure 2 can protect the chip and prevent glare when the chip is used.
The comparison results of the chip prepared by the process of example 2 and the chip prepared by the process of the background art after use are shown in fig. 17 and fig. 18, wherein fig. 17 is of the background art, and fig. 18 is of example 2.
As can be seen from fig. 17 and 18, the metal aluminum pads inside the chip are easily unprotected by the related art process, and corrosion occurs during the processing, which may easily cause chip failure and yield reduction in subsequent use. The process method in the embodiment 2 has an anti-corrosion effect on the metal bonding pad, and chip failure and yield reduction are not easily caused in subsequent use.
Based on the above wafer manufacturing method, the utility model also provides a chip.
Referring to fig. 19-20, fig. 19 is a schematic diagram of an optical path structure and a position of a bonding pad, and fig. 20 is a schematic diagram of a chip structure according to the present invention.
The utility model provides a chip, this chip includes chip base member 1, is provided with light path structure 2 and a plurality of metal pad 3 on this chip base member 1, and a plurality of metal pad 3 distribute outside light path structure 2, and this chip still includes first protective layer 9, and first protective layer 9 is located between light path structure 2 and chip base member 1 and light path structure 2 and a plurality of metal pad 3. The chip substrate 1 is a part of the wafer substrate 1.
Optionally, the first protection layer 9 is a silicon nitride film.
Optionally, the first protective layer has a thickness of 40 nm.
Optionally, the chip further includes a second protection layer 10, and the second protection layer 10 is coated on the optical path structure 2.
Optionally, the second protective layer 10 is a low temperature oxide layer.
Optionally, the low temperature oxide layer is a silicon dioxide layer.
Alternatively, the silica layer is 100nm thick and has a refractive index of 1.5.
Based on foretell chip, the utility model also provides an optics biological identification module.
An optical biological identification module comprises the chip.
The optics biological identification module can be called optics fingerprint identification module, fingerprint identification device, fingerprint identification module, fingerprint collection device, discernment module etc. and above-mentioned term can replace each other.
Based on foretell optics biological identification module, the utility model also provides an electronic equipment.
An electronic device comprises the optical biological identification module.
The electronic device can be a mobile phone, a tablet computer and the like.
In the description of the present invention, it is to be noted that, unless otherwise explicitly stated or limited, the terms "mounted," "connected," and "connected" are to be construed broadly and may include, for example, a fixed connection, an indirect connection via an intermediary, a connection between two elements, or an interaction between two elements. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.
In the description of the present invention, it is to be understood that the terms "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore, should not be construed as limiting the present invention. In the description of the present invention, "a plurality" means two or more unless specifically stated otherwise.
The terms "first," "second," "third," "fourth," and the like in the description and in the claims of the present application and in the drawings described above, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention.
Claims (9)
1. A chip, comprising:
a chip substrate;
the light path structure is arranged on the chip substrate;
the metal bonding pad is arranged on the chip substrate and is positioned outside the light path structure; and
and the first protective layer is positioned between the optical path structure and the chip substrate and between the optical path structure and the metal bonding pad.
2. The chip of claim 1, wherein: the first protective layer is a silicon nitride film layer.
3. The chip of claim 2, wherein: the first protective layer thickness is 40 nm.
4. The chip of claim 1, wherein: the chip further comprises a second protective layer, and the second protective layer is coated on the light path structure.
5. The chip of claim 4, wherein: the second protective layer is a low temperature oxide layer.
6. The chip of claim 5, wherein: the low-temperature oxide layer is a silicon dioxide layer.
7. The chip of claim 6, wherein: the thickness of the silicon dioxide layer is 100nm, and the refractive index is 1.5.
8. An optics biological identification module which characterized in that: the optical biological identification module comprises the chip of any one of claims 1-7.
9. An electronic device, characterized in that: the electronic device comprising the optical biometric module of claim 8.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202022591159.9U CN214098444U (en) | 2020-11-11 | 2020-11-11 | Chip, optical biological identification module formed by chip and electronic equipment |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202022591159.9U CN214098444U (en) | 2020-11-11 | 2020-11-11 | Chip, optical biological identification module formed by chip and electronic equipment |
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| CN214098444U true CN214098444U (en) | 2021-08-31 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112308007A (en) * | 2020-11-11 | 2021-02-02 | 上海菲戈恩微电子科技有限公司 | Wafer manufacturing method, chip manufactured by same and optical biological identification module |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112308007A (en) * | 2020-11-11 | 2021-02-02 | 上海菲戈恩微电子科技有限公司 | Wafer manufacturing method, chip manufactured by same and optical biological identification module |
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