CN108346640A - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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CN108346640A
CN108346640A CN201710060906.6A CN201710060906A CN108346640A CN 108346640 A CN108346640 A CN 108346640A CN 201710060906 A CN201710060906 A CN 201710060906A CN 108346640 A CN108346640 A CN 108346640A
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substrate
chip
flexible pcb
conductive bump
semiconductor structure
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CN108346640B (zh
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陈育民
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Winbond Electronics Corp
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Winbond Electronics Corp
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Abstract

本发明提供一种半导体结构及其制造方法，其包括基板、芯片、多个导电凸块、柔性电路板以及多条线路图案。芯片设置在基板上并包括多个焊垫。导电凸块分别设置在焊垫上。柔性电路板桥接在基板与芯片之间，且导电凸块穿过柔性电路板的一端。线路图案设置在柔性电路板上以电性连接导电凸块与基板。本发明提供的半导体结构及其制造方法，可简化制作工艺、提升良率，还可降低生产成本。

Description

半导体结构及其制作方法
技术领域
本发明涉及半导体结构及其制作方法，尤其涉及一种良率较高的半导体结构及其制作方法。
背景技术
在现今信息爆炸的社会，电子产品遍布于日常生活中，无论在食衣住行育乐方面，都会用到集成电路元件所组成的产品。随着电子科技不断地演进，功能性更复杂、更人性化的产品推陈出新，而一般电子产品是通过至少一芯片来控制其电子产品的作动，一般可以利用打线(wire-bonding)的方式、覆晶(flip-chip，F/C)的方式、软片自动贴合(tape-automated bonding，TAB)的方式，使芯片与一基板或导线架电性连接。
就打线工艺而言，打线装置例如用来将基板的接脚与半导体芯片的焊垫之间以细线的金属线连接。打线是以如下方式进行，即，使金属线与打线用工具一并朝向导线下降，继而，利用工具前端将金属线压抵于导线，一面施加超音波振动一面使两者接合，而成为第一接合。在第一接合后，提拉工具而一面使金属线延出而形成适当的线弧(loop)一面移动至焊垫的上方。当到达焊垫的上方时使工具下降。继而，利用工具前端将金属线压抵于焊垫，一面施加超音波振动一面使两者接合而进行第二接合。在第二接合后，一面利用线夹(wire clamper)停止金属线的移动一面提拉工具而将金属线在第二接合点处切断。重复该操作，而进行基板的多个接脚与半导体芯片的多个焊垫之间的连接。此外，在第一接合、第二接合时，也可进行适当的加热。此外，也可对焊垫进行第一接合，对接脚进行第二接合。
然而，现有的打线接合技术仍存在许多问题，举例而言，相邻的金属线间可能会发生短路，一或多个金属线的互连也会发生开路。例如：工艺中金属线的移动如摆动(sway)、弯曲(sweep)等可能导致相邻的金属线之间短路。更严重者，金属线的此类移动有可能造成一或多个金属线断裂，进而导致断路。并且，半导体工艺的制品种类繁多，在每个制品中用以连接的接线数、半导体形状并不相同。因此，现有的打线接合技术需对不同制品准备专用的打线工具和打线台，因而导致生产成本增高、设备上所安装的打线工具和打线台的更换需要时间以及打线工具和打线台的管理繁杂等问题。
发明内容
本发明实施例提供一种半导体结构及其制作方法，其可简化制作工艺、提升良率，更可降低生产成本。
本发明实施例提供一种半导体结构，其包括基板、第一芯片、多个第一导电凸块、第一柔性电路板以及多条第一线路图案。第一芯片设置于基板上并包括多个第一焊垫。第一导电凸块分别设置于第一焊垫上。第一柔性电路板桥接在基板与第一芯片之间，且第一导电凸块穿过第一柔性电路板的第一端。第一线路图案设置在第一柔性电路板上以电性连接第一导电凸块与基板。
本发明实施例提供一种半导体结构的制作方法，其包括下列步骤：
提供基板；设置第一芯片在基板上，其中第一芯片包括多个第一焊垫；以三维打印技术形成多个第一导电凸块在第一焊垫上；进行热压合工艺，以将第一柔性电路板桥接在基板与第一芯片之间，其中第一导电凸块穿过第一柔性电路板，以通过第一柔性电路板而电性连接至基板。
在本发明的一实施例中，上述的各第一导电凸块实质上为锥状导电凸块，其中锥状导电凸块的尖端穿过第一柔性电路板的第一线路图案。
在本发明的一实施例中，上述的各第一导电凸块的材料包括银合金或铝合金。
在本发明的一实施例中，上述的半导体结构还包括多个基板导电凸块，设置在基板上，其中第一线路图案由第一柔性电路板延伸至基板上并分别连接基板导电凸块，以电性连接第一导电凸块与基板。
在本发明的一实施例中，上述的半导体结构还包括多个基板导电凸块，基板导电凸块穿过第一柔性电路板相对在第一端的第二端，以电性连接第一线路图案。
在本发明的一实施例中，上述的半导体结构还包括压合胶，设置在第一柔性电路板与第一芯片之间以及第一柔性电路板与基板之间。
在本发明的一实施例中，上述的半导体结构还包括第二芯片、多个第二导电凸块以及第二柔性电路板，第二芯片叠设在第一芯片上并暴露第一焊垫，第二导电凸块分别设置在第二芯片的多个第二焊垫上，第二柔性电路板桥接在第一芯片与第二芯片之间并包括多条第二线路图案，第一导电凸块以及第二导电凸块分别穿过第二柔性电路板的相对两侧，以通过第二线路图案电性连接第一导电凸块与第二导电凸块。
在本发明的一实施例中，上述的半导体结构的制作方法还包括：以三维打印技术形成多条第一线路图案以及多个基板导电凸块，其中第一线路图案由第一柔性电路板延伸至基板，以电性连接第一导电凸块与基板上的基板导电凸块。
在本发明的一实施例中，上述的半导体结构的制作方法还包括：以三维打印技术形成多个基板导电凸块在基板上，其中第一柔性电路板桥接在基板与第一芯片之间时，基板导电凸块穿过第一柔性电路板，并电性连接第一柔性电路板上的多条第一线路图案。
在本发明的一实施例中，上述的半导体结构的制作方法还包括下列步骤。叠设第二芯片在第一芯片上，且第二芯片暴露第一焊垫。以三维打印技术形成多个第二导电凸块在第二芯片的多个第二焊垫上。将第二柔性电路板桥接在第一芯片与第二芯片之间，其中第二柔性电路板包括以三维打印技术而形成的多条第二线路图案，第一导电凸块以及第二导电凸块分别穿过第二柔性电路板的相对两侧，以通过第二柔性电路板的第二线路图案电性连接第一导电凸块与第二导电凸块。
基于上述，本发明实施例以三维打印技术分别在芯片及基板上打印形成多个导电凸块，接着再利用柔性电路板桥接在芯片与基板之间，并使芯片与基板上的导电凸块分别穿过柔性电路板的相对两端，以通过柔性电路板而电性连接芯片与基板。如此配置，本发明可省去现有的打线工艺即完成芯片与基板之间的电性连接，因而可避免现有的打线工艺中相邻的金属线间容易发生短路的问题，更可省去专用的打线工具和打线台的生产成本，因此，本发明的半导体结构及其制作方法可有效提升良率、简化工艺，还可降低生产成本。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
图1至图7是依照本发明的一实施例的一种半导体结构的制作流程示意图。
附图标记说明：
100：半导体结构； 110：基板；
112：基板导电凸块； 120：第一芯片；
122：第一焊垫； 130：第一导电凸块；
140：第一柔性电路板； 142：第一端；
144：第二端； 150：第一线路图案；
160：第二芯片； 162：第二焊垫；
170：第二导电凸块； 180：第二柔性电路板；
190：第二线路图案。
具体实施方式
有关本发明的前述及其他技术内容、特点与功效，在以下配合参考附图的各实施例的详细说明中，将可清楚的呈现。以下实施例中所提到的方向用语，例如：“上”、“下”、“前”、“后”、“左”、“右”等，仅是参考附图的方向。因此，使用的方向用语是用来说明，而并非用来限制本发明。并且，在下列各实施例中，相同或相似的元件将采用相同或相似的标号。
图1至图7是依照本发明的一实施例的一种半导体结构的制作流程示意图。本实施例的半导体结构100的制作方法包括下列步骤。首先，提供如图1所示的基板110。接着，设置第一芯片120在基板110上。在本实施例中，第一芯片120是经由对具有多个芯片的晶圆进行切割(dicing)而得。第一芯片120包括多个第一焊垫122、有源表面以及相对有源表面的背面。第一焊垫122设置在有源表面，而第一芯片120是以其背面设置在基板110上。
接着，请参照图2，以三维打印技术形成多个第一导电凸块130在第一焊垫122上。具体而言，本实施例可利用三维打印装置并依据第一导电凸块130的数字三维模型而打印出如图2所示的第一导电凸块130。本实施例的三维打印技术可包括熔丝制造(FusedFilament Fabrication,FFF)、光硬化(Stereolithography)、熔化压模(Melted andExtrusion Modeling)、电子束熔化成形(Electron Beam Modeling)或其他适合的三维打印技术，本发明并不以此为限。
在本实施例中，各个第一导电凸块130可如图2的局部放大图所示的为锥状导电凸块，其包括尖端，且第一导电凸块130的材料可包括银合金或铝合金。在本实施例中，第一导电凸块130的数字三维模型可为数字三维图像文件，其可通过例如电脑辅助设计(computer-aided design,CAD)或动画建模软件等建构而成，并将此数字三维模型横切为多个横截面以供三维打印装置读取，以依据此数字三维模型的横截面将建构材料逐层成形在三维打印装置的打印平台上，而形成多个叠构层。上述的叠构层彼此堆叠而形成第一导电凸块130。也就是说，以三维打印技术而形成的第一导电凸块130可由多个叠构层彼此堆叠而成，当然，本发明并不以此为限。此外，在打印形成第一导电凸块130之后，可选择性地进行固化工艺，以固化第一导电凸块130并强化第一导电凸块130的硬度。
接着，请参照图3，进行热压合工艺，以将第一柔性电路板140桥接在基板110与第一芯片120之间，其中，锥状的第一导电凸块130的尖端穿过第一柔性电路板140的第一端142，以通过第一柔性电路板140而电性连接至基板110。详细而言，本实施例可通过设置压合胶在第一柔性电路板140的相对两端，再进行热压合工艺，以将第一柔性电路板140的相对两端分别通过热压合工艺而压合在第一芯片120与基板110上。详细而言，压合胶可设置在第一柔性电路板140与第一芯片120之间以及第一柔性电路板140与基板110之间。
请接续参照图4，本实施例以三维打印技术而打印形成多条第一线路图案150以及多个基板导电凸块112，其中，基板导电凸块112打印形成在基板110上，而第一线路图案150则打印形成在第一柔性电路板140及基板110上并与第一导电凸块130及基板导电凸块112接触，以电性连接第一导电凸块130与基板110。
此外，在另一实施例中，通过第一柔性电路板140电性连接第一导电凸块130与基板110的方法也可如图5所示的预先以三维打印技术打印多条第一线路图案150在第一柔性电路板140上，并以三维打印技术打印形成多个基板导电凸块112在基板110上，以在热压合第一柔性电路板140时，使椎状的基板导电凸块112穿过第一柔性电路板140相对于第一端142的第二端144，以电性连接第一柔性电路板140上的第一线路图案150。在本实施例中，基板导电凸块112可如第一导电凸块130而呈锥状，如此，锥状的第一导电凸块130的尖端穿过第一线路图案150的一端，锥状的基板导电凸块112的尖端穿过第一线路图案150的另一端，因而可通过第一柔性电路板140的第一线路图案150而电性连接第一导电凸块130与基板导电凸块112。如此，本实施例的半导体结构的制作方法可大致完成。
在本实施例中，半导体结构的制作方法也可再接续执行下述步骤。请接续参照图6，叠设第二芯片160在第一芯片120上，且第二芯片160暴露第一芯片120的第一焊垫122。在本实施例中，第二芯片160可包括多个第二焊垫162、有源表面以及相对有源表面的背面。第二焊垫162设置在第二芯片160的有源表面上，而第二芯片160是以其背面叠设在第一芯片120上。接着，以三维打印技术形成多个第二导电凸块170在第二芯片160的第二焊垫162上。第二导电凸块170可如同第一导电凸块130而呈锥状。
接着，请参照图7，将第二柔性电路板180桥接在第一芯片120与第二芯片160之间，以通过第二柔性电路板180电性连接第一芯片120与第二芯片160。详细而言，本实施例可预先以三维打印技术而打印形成的多条第二线路图案190在第二柔性电路板180上，如此，在将第二柔性电路板180桥接在第一芯片120与第二芯片160之间时，第一导电凸块130以及第二导电凸块170可分别穿过第二柔性电路板180的相对两侧，并分别穿过第二柔性电路板180上的第二线路图案190，以通过第二柔性电路板180的第二线路图案190而电性连接第一导电凸块130与第二导电凸块180。如此，本实施例的半导体结构100的制作方法可大致完成。
综上所述，本发明以三维打印技术分别在芯片及基板上打印形成多个导电凸块，接着再利用柔性电路板桥接在芯片与基板之间，并使芯片与基板上的导电凸块分别穿过柔性电路板的相对两端，以通过柔性电路板而电性连接芯片与基板。此外，本发明还可应用在堆叠式芯片封装上，以利用柔性电路板桥接在各芯片之间，以电性连接各芯片及基板。
如此配置，本发明利用柔性电路板的可挠性来进行芯片与基板和/或芯片与芯片之间的电性连接，因而可省去现有的打线工艺，进而可避免现有的打线工艺中相邻的金属线间容易发生短路的问题，更可省去专用的打线工具和打线台的生产成本，因此，本发明的半导体结构及其制作方法可有效提升良率、简化制作工艺，更可降低生产成本。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (11)

1.一种半导体结构，其特征在于，包括：
基板；
第一芯片，设置在所述基板上并包括多个第一焊垫；
多个第一导电凸块，分别设置在所述多个第一焊垫上；
第一柔性电路板，桥接在所述基板与所述第一芯片之间，且所述多个第一导电凸块穿过所述第一柔性电路板的第一端；以及
多条第一线路图案，设置在所述第一柔性电路板上以电性连接所述多个第一导电凸块与所述基板。
2.根据权利要求1所述的半导体结构，其特征在于，各所述第一导电凸块实质上为锥状导电凸块，所述多个锥状导电凸块的尖端穿过所述第一柔性电路板的所述多个第一线路图案。
3.根据权利要求1所述的半导体结构，其特征在于，各所述第一导电凸块的材料包括银合金或铝合金。
4.根据权利要求1所述的半导体结构，其特征在于，还包括多个基板导电凸块，设置于所述基板上，其中所述多个第一线路图案由所述第一柔性电路板延伸至所述基板上并分别连接所述多个基板导电凸块，以电性连接所述多个第一导电凸块与所述基板。
5.根据权利要求1所述的半导体结构，其特征在于，还包括多个基板导电凸块，所述多个基板导电凸块穿过所述第一柔性电路板相对于所述第一端的第二端，以电性连接所述多个第一线路图案。
6.根据权利要求1所述的半导体结构，其特征在于，还包括压合胶，设置于所述第一柔性电路板与所述第一芯片之间以及所述第一柔性电路板与所述基板之间。
7.根据权利要求1所述的半导体结构，其特征在于，还包括第二芯片、多个第二导电凸块以及第二柔性电路板，所述第二芯片叠设于所述第一芯片上并暴露所述多个第一焊垫，所述多个第二导电凸块分别设置在所述第二芯片的多个第二焊垫上，所述第二柔性电路板桥接在所述第一芯片与所述第二芯片之间并包括多条第二线路图案，所述多个第一导电凸块以及所述多个第二导电凸块分别穿过所述第二柔性电路板的相对两侧，以通过所述多个第二线路图案电性连接所述多个第一导电凸块与所述多个第二导电凸块。
8.一种半导体结构的制作方法，其特征在于，包括：
提供基板；
设置第一芯片在所述基板上，其中所述第一芯片包括多个第一焊垫；
以三维打印技术形成多个第一导电凸块在所述多个第一焊垫上；以及
进行热压合工艺，以将第一柔性电路板桥接在所述基板与所述第一芯片之间，其中所述多个第一导电凸块穿过所述第一柔性电路板，以通过所述第一柔性电路板而电性连接至所述基板。
9.根据权利要求8所述的半导体结构的制作方法，其特征在于，还包括：
以三维打印技术形成多条第一线路图案以及多个基板导电凸块，其中所述多个第一线路图案由所述第一柔性电路板延伸至所述基板，以电性连接所述多个第一导电凸块与所述基板上的所述多个基板导电凸块。
10.根据权利要求8所述的半导体结构的制作方法，其特征在于，还包括：
以三维打印技术形成多个基板导电凸块于在所述基板上，其中所述第一柔性电路板桥接于在所述基板与所述第一芯片之间时，所述多个基板导电凸块穿过所述第一柔性电路板，并电性连接所述第一柔性电路板上的多条第一线路图案。
11.根据权利要求8所述的半导体结构的制作方法，其特征在于，还包括：
叠设第二芯片在所述第一芯片上，且所述第二芯片暴露所述多个第一焊垫；
以三维打印技术形成多个第二导电凸块在所述第二芯片的多个第二焊垫上；
将第二柔性电路板桥接于在所述第一芯片与所述第二芯片之间，其中所述第二柔性电路板包括以三维打印技术而形成的多条第二线路图案，所述多个第一导电凸块以及所述多个第二导电凸块分别穿过所述第二柔性电路板的相对两侧，以通过所述第二柔性电路板的所述多个第二线路图案电性连接所述多个第一导电凸块与所述多个第二导电凸块。
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