CN108346576A - 由p+衬底、p-层、n-层和第三层构成的层堆叠的制造方法 - Google Patents
由p+衬底、p-层、n-层和第三层构成的层堆叠的制造方法 Download PDFInfo
- Publication number
- CN108346576A CN108346576A CN201711365600.8A CN201711365600A CN108346576A CN 108346576 A CN108346576 A CN 108346576A CN 201711365600 A CN201711365600 A CN 201711365600A CN 108346576 A CN108346576 A CN 108346576A
- Authority
- CN
- China
- Prior art keywords
- layer
- substrate
- manufacturing
- stacks
- folded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 60
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 34
- 239000002019 doping agent Substances 0.000 claims abstract description 16
- 238000002347 injection Methods 0.000 claims abstract description 11
- 239000007924 injection Substances 0.000 claims abstract description 11
- 239000000463 material Substances 0.000 claims abstract description 10
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 230000007547 defect Effects 0.000 claims description 5
- 229910000765 intermetallic Inorganic materials 0.000 claims description 4
- 238000000926 separation method Methods 0.000 claims description 4
- 239000000243 solution Substances 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims 3
- 150000002736 metal compounds Chemical class 0.000 claims 1
- 238000004943 liquid phase epitaxy Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 238000000407 epitaxy Methods 0.000 description 3
- 150000002902 organometallic compounds Chemical class 0.000 description 3
- 239000012071 phase Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- -1 GaAs Compound Chemical class 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 210000004400 mucous membrane Anatomy 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/184—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/02546—Arsenides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/0257—Doping during depositing
- H01L21/02573—Conductivity type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/207—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds further characterised by the doping material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
- H01L31/0264—Inorganic materials
- H01L31/0304—Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/2654—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds
- H01L21/26546—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds of electrically active species
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Electromagnetism (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Recrystallisation Techniques (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
层堆叠的制造方法,层堆叠由p+衬底、p‑层、n‑层和第三层构成,p+衬底具有5*1018‑5*1020N/cm3的掺杂剂浓度和50‑900微米的层厚度且包括GaAs化合物,p‑层具有1014‑1016N/cm3的掺杂剂浓度和0.01‑30微米的层厚度且包括GaAs化合物,n‑层具有1014‑1016N/cm3的掺杂剂浓度,10‑200微米的层厚度且包括GaAs化合物,制造第一和第二部分堆叠且两个部分堆叠的上侧通过晶圆接合材料锁合地连接,第一部分堆叠包括至少p+衬底,第二部分堆叠包括至少n‑层,p‑层通过外延或注入制造,p‑层构成第一或第二部分堆叠的上侧,制造第三层,n‑层在n+衬底上制造。
Description
技术领域
本发明涉及一种由p+衬底、p-层、n-层和第三层构成的层堆叠的制造方法。
背景技术
由German Ashkinazi的《GaAs Power Devices》ISBN 965-7094-19-4(第8页和第9页)已知一种高压稳定的半导体二极管p+-n-n+,其中,所述n-层和n+层借助液相外延在两个p+衬底之间制造。在第三章,第22-26页描述一种肖特基二极管,所述肖特基二极管具有包括GaAs的具有n+衬底的外延的层结构以及用于构造肖特基接通部的包括镍的层。
由EP 2 645 431 A1已知一种用于由两个或多个太阳能电池构成的双太阳能电池(Tandemsolarzelle)的制造方法,其中,至少一个第一太阳能电池在基础衬底结构上制造,第二太阳能电池在辅助衬底上制造,并且所述两个太阳能电池紧接着借助晶圆接合材料锁合地彼此连接。
发明内容
在这些背景下,本发明的任务在于,说明一种扩展现有技术的设备。
所述任务通过具有权利要求1的特征的制造方法解决。本发明的有利构型是从属权利要求的主题。
根据本发明的主题提供一种用于层堆叠的制造方法,所述层堆叠包括p+衬底、p-层、n-层和第三层。
所述p+衬底具有1*1018-5*1020N/cm3的掺杂剂浓度和50-500微米的层厚度并且包括GaAs化合物或者由GaAs化合物构成。
所述p-层具有1014-1016N/cm3的掺杂剂浓度和0.01-30微米的层厚度并且包括GaAs化合物或者由GaAs化合物构成。
所述n-层具有1014-1016N/cm3的掺杂剂浓度,10-200微米的层厚度并且包括GaAs化合物或者由GaAs化合物构成。
制造第一部分堆叠和第二部分堆叠并且使第一部分堆叠的上侧与第二部分堆叠的上侧通过晶圆接合材料锁合地连接,以便制造层堆叠。
第一部分堆叠至少包括p+衬底,而第二部分堆叠至少包括n-层。
所述p-层通过外延、例如液相外延(LPE)或金属有机物气相外延(MOVPE)或通过在p+衬底的上侧上的注入或通过在n-层上的外延制造,并且形成第一部分堆叠的或第二部分堆叠的上侧。所述第三层在晶圆接合之前或之后制造。
优选地,p-层具有小于1013N/cm3的掺杂浓度或在1013N/cm3至1015N/cm3之间的掺杂浓度。在一种实施方式中,在接合之前或之后通过磨削过程将p+衬底削薄到200微米至500微米之间的厚度。
在第一替代方案中,在晶圆接合之后通过磨削至少部分地形成第二部分堆叠的n-衬底制造所述n-层,在所述第二部分堆叠中,从n-衬底出发,使n-衬底与第一堆叠通过晶圆接合过程连接。在以下过程步骤中,将n-衬底并且由此将n-层削薄到期望的厚度。
在第二替代方案中,在晶圆接合之前在n+衬底上外延地制造所述n-层。
优选地,n-层的厚度处于50微米至250微米之间的范围中。
借助另外的晶圆接合制造n-层的优点是,n-层的厚度可以容易地制造。由此省去在外延时的长的切削过程。借助另外的晶圆接合过程也可以降低堆叠错误的数量。
在一种替代的实施方式中,n-层具有大于1010N/cm3且小于1013N/cm3的浓度。其中,浓度极小,n-层也可以理解为固有层。
在另一扩展方案中,在削薄n-层之后借助外延或高掺杂注入在n+衬底上制造1018N/cm3至5*1019N/cm3的范围中的n+层。n-衬底的削薄优选借助CMP步骤、也就是说借助化学机械研磨进行。
应说明,表述“晶圆接合”与表述“半导体接合”同义地使用。第一部分堆叠优选单片地并且优选同样单片地构造。
可以理解,所述衬底以及第一层和第二层的情况涉及III-V族半导体层,其中,在一种扩展方案中,所述层和衬底具有分别相等的栅极常数并且优选地包括相同的半导体材料、尤其GaAs。
优点是:通过晶圆接合和通过p-中间层,所制造的层堆叠的晶体结构的质量与例如仅通过外延和/或不具有中间层而制造的堆叠相比恰好对于厚的半导体层获得高的层质量。层堆叠尤其可以以稍微偏移地制造。由此,尤其在n-层的情况下明显提高载流子寿命。也可以在p-中间层中在晶圆接合之前引入复合中心(Rekombinationszentren),以便影响p-中间层中电荷的寿命。
分离所述n-层的优点是,第二部分堆叠的载体或n-衬底被多次地反复使用。
相应地适用于所述n+衬底,也就是说通过薄的n+层的分离可以反复使用n+衬底。优选地,n-层也可以在分离薄的n+层之前外延地制造。换言之,在一种扩展方案中,使n+层——其作为n+衬底的直接邻接n-层的区域——与n-层一起在晶圆接合之前与n+衬底分离。
在一种扩展方案中,在晶圆接合之前制造的n-层在通过在n+衬底上的外延——例如液相外延(LPE)或金属有机物气相外延(MOVPE)——或通过在n+衬底内的注入而分离之前制造。
根据一种替代的扩展方案,所述第三层构造为n+层,所述n+层具有至少5*1018N/cm3的掺杂剂浓度、小于20微米的层厚度并且包括GaAs化合物或由GaAs化合物的构成。
所述n+层可以在晶圆接合之后通过在通过磨削制造的n-层上的外延或通过在通过磨削制造的n-层中的注入制造。
在一种扩展方案中,所述n-层借助晶格缺陷的注入与n-衬底分离。
n-层和/或n+层与n+衬底的分离根据另一实施方式通过晶格缺陷的注入实现。
根据一种替代的实施方式,所述第三层包括金属或金属化合物或由金属或金属化合物构成。
附图说明
接下来参照附图进一步阐述本发明。在此,同类的部分以同样的标志来标记。所显示的实施方式是强烈示意性的,也就是说,间距以及横向和纵向的延伸不是按比例的并且——只要未另外说明——彼此也不具有能推导的几何关系。在此示出:
图1:根据本发明的制造方法的第一实施方式的示意性视图;
图2:根据本发明的制造方法的第二实施方式的示意性视图;
图3A,B:根据本发明的制造方法的第三实施方式的示意性视图;
图4:根据本发明的制造方法的第四实施方式的示意性视图。
具体实施方式
图1的附图示出根据本发明的制造方法的第一实施方式的视图。
在具有5*1018-5*1020N/cm3的掺杂剂浓度和50-500微米的层厚度的p+衬底上制造具有1014-1016N/cm3的掺杂剂浓度和0.01-30微米的层厚度的p-层,其中,不仅p+衬底而且p-层包括GaAs化合物或由GaAs化合物构成。
由p+衬底和p-层构成的层序列形成第一部分堆叠,其中,p-层形成部分堆叠的上侧。
在具有至少5*1018N/cm3的掺杂剂浓度的n+衬底上通过外延——例如通过液相外延或者金属有机物气相外延——制造具有1012-1016N/cm3的掺杂剂浓度和10-300微米的层厚度的n-层,其中,所述n+衬底以及n-层包括GaAs化合物或者由GaAs化合物构成。
紧接着,使所述n-层与n+衬底的直接连接到n-层处的第一区域一起与n+衬底在位置AB处分离。所述分离例如通过在n+衬底中注入缺陷部位(Fehlstellen)实现。
所述n+衬底的经分离区域构成层堆叠的第三层并且具有小于30微米的层厚度。由n-层和n+层构成的层序列形成第二部分堆叠,其中,所述n-层形成所述部分堆叠的上侧。
第一部分堆叠的上侧与第二部分堆叠的上侧通过晶圆接合材料锁合地连接,也就是说,在所述分离之后上述由n-层和n+层构成的层序列以n-层的上侧施加到p-层的上侧上,并且两个上侧通过晶圆接合彼此材料锁合地连接。
在图2的附图中示出根据本发明的制造方法的第二种实施方式。以下仅阐述与图1的附图的区别。
根据第二实施方式,p-层通过在n-层的上侧上的外延制造并且形成第二部分堆叠的上侧,而第一部分堆叠仅包括p+衬底。
在图3A和3B的附图中示出根据本发明的制造方法的第三实施方式。以下仅阐述与图1的附图的区别。
根据第三实施方式,第一部分堆叠如在第一实施方式中那样由p+衬底和p-层形成。第二部分堆叠由n-衬底构成。n-层在第一部分堆叠与第二部分堆叠的材料锁合地连接之后通过n-衬底的磨削制造成期望的层厚度。
第三层在磨削之后——例如通过外延——施加在n-层的上侧上并且与所述上侧材料锁合地连接。替代地,第三层在n-层中通过将掺杂剂注入I到n-层的表面中形成。第三层是n+层。替代地,第三层由金属或金属化合物构成或者包括金属或金属化合物。
在图4的图示中示出根据本发明的制造方法的第四实施方式。以下仅阐述与以上图的图示的区别。
第四实施方式以以下区别相应于第三实施方式:p-层通过在n-衬底上的外延制造。
Claims (8)
1.一种层堆叠的制造方法,所述层堆叠由p+衬底、p-层、n-层和第三层构成,其中,
-所述p+衬底具有5*1018-5*1020N/cm3的掺杂剂浓度和50-900微米的层厚度并且包括GaAs化合物或者由GaAs化合物构成,
-所述p-层具有1014-1016N/cm3的掺杂剂浓度和0.01-1微米的层厚度并且包括GaAs化合物或者由GaAs化合物构成,
-所述n-层具有1014-1016N/cm3的掺杂剂浓度和10-200微米的层厚度并且包括GaAs化合物或者由GaAs化合物构成,
-制造第一部分堆叠和第二部分堆叠并且使所述第一部分堆叠的上侧与所述第二部分堆叠的上侧通过晶圆接合材料锁合地连接,以便制造所述层堆叠,
-所述第一部分堆叠至少包括所述p+衬底,
-所述第二部分堆叠至少包括所述n-层,
-通过在所述p+衬底的上侧上的外延或注入或通过在所述n-层上的外延制造所述p-层,并且所述p-层形成所述第一部分堆叠的或所述第二部分堆叠的上侧,
-所述第三层在所述晶圆接合之前或之后制造,
-在第一替代方案中,在所述晶圆接合之后通过磨削至少部分地形成所述第二部分堆叠的n-衬底制造所述n-层,或者,在第二替代方案中,在所述晶圆接合之前在n+衬底上制造所述n-层。
2.根据权利要求1所述的制造方法,其特征在于,通过在n+衬底上的外延制造在所述晶圆接合之前在所述n+衬底上制造的n-层。
3.根据权利要求1或2所述的制造方法,其特征在于,所述第三层构造为n+层,所述n+层具有至少1019N/cm3的掺杂剂浓度、小于30微米的层厚度并且包括GaAs化合物或者由GaAs化合物构成。
4.根据权利要求3所述的制造方法,其特征在于,在所述晶圆接合之后通过在通过磨削制造的n-层上的外延或通过在通过磨削制造的n-层中的注入或通过与所述n+衬底的分离制造所述n+层。
5.根据权利要求4所述的制造方法,其特征在于,使所述n+层——其作为所述n+衬底的直接邻接所述n-层的区域——与所述n-层一起在晶圆接合之前与所述n+衬底分离。
6.根据权利要求1至5中任一项所述的制造方法,其特征在于,借助晶格缺陷的注入使所述n-层与n-衬底分离。
7.根据权利要求1至5中任一项所述的制造方法,其特征在于,使所述n-层借助晶格缺陷的注入与所述n+衬底分离和/或使所述n+层通过晶格缺陷的注入与所述n+衬底分离。
8.根据权利要求1或2所述的制造方法,其特征在于,所述第三层包括金属或金属化合物或者由金属或金属化合物构成。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102016015056.4A DE102016015056A1 (de) | 2016-12-17 | 2016-12-17 | Herstellungsverfahren eines Schichtstapels aus einem p+-Substrat, einer p--Schicht, einer n--Schicht und einer dritten Schicht |
DE102016015056.4 | 2016-12-17 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN108346576A true CN108346576A (zh) | 2018-07-31 |
CN108346576B CN108346576B (zh) | 2021-03-16 |
Family
ID=60673431
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201711365600.8A Active CN108346576B (zh) | 2016-12-17 | 2017-12-18 | 由p+衬底、p-层、n-层和第三层构成的层堆叠的制造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US10192745B2 (zh) |
EP (1) | EP3336906B1 (zh) |
JP (1) | JP6649935B2 (zh) |
CN (1) | CN108346576B (zh) |
DE (1) | DE102016015056A1 (zh) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102019001459B3 (de) | 2019-03-04 | 2020-09-03 | 3-5 Power Electronics GmbH | Stapelförmige hochsperrende III-V-Leistungshalbleiterdiode |
DE102019003068A1 (de) | 2019-04-30 | 2020-11-05 | 3-5 Power Electronics GmbH | Stapelförmige hochsperrende lnGaAS-Halbleiterleistungsdiode |
DE102019003069B4 (de) | 2019-04-30 | 2023-06-01 | Azur Space Solar Power Gmbh | Stapelförmige hochsperrende lll-V-Halbleiterleistungsdioden |
DE102020001837B3 (de) | 2020-03-20 | 2021-08-26 | Azur Space Solar Power Gmbh | Stapelförmiges photonisches lll-V-Halbleiterbauelement |
DE102020001841A1 (de) | 2020-03-20 | 2021-09-23 | Azur Space Solar Power Gmbh | Stapelförmige hochsperrende III-V-Halbleiterleistungsdiode |
DE102020001838A1 (de) | 2020-03-20 | 2021-09-23 | Azur Space Solar Power Gmbh | Stapelförmige hochsperrende lll-V-Halbleiterleistungsdiode |
DE102020001842A1 (de) | 2020-03-20 | 2021-09-23 | Azur Space Solar Power Gmbh | Stapelförmiges photonisches III-V-Halbleiterbauelement |
DE102020001840B3 (de) | 2020-03-20 | 2021-09-23 | Azur Space Solar Power Gmbh | Stapelförmiges photonisches III-V-Halbleiterbauelement |
DE102020001843A1 (de) | 2020-03-20 | 2021-09-23 | Azur Space Solar Power Gmbh | Stapelförmige hochsperrende InGaAs-Halbleiterleistungsdiode |
DE102020001835A1 (de) | 2020-03-20 | 2021-09-23 | Azur Space Solar Power Gmbh | Stapelförmige hochsperrende lll-V-Halbleiterleistungsdiode |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01259570A (ja) * | 1988-04-11 | 1989-10-17 | Toshiba Corp | 半導体装置及びその製造方法 |
US20020048900A1 (en) * | 1999-11-23 | 2002-04-25 | Nova Crystals, Inc. | Method for joining wafers at a low temperature and low stress |
US20100233839A1 (en) * | 2009-01-29 | 2010-09-16 | Emcore Solar Power, Inc. | String Interconnection and Fabrication of Inverted Metamorphic Multijunction Solar Cells |
CN102810466A (zh) * | 2011-05-10 | 2012-12-05 | Soitec公司 | 用于制造半导体衬底的方法 |
CN103700712A (zh) * | 2012-09-27 | 2014-04-02 | 比亚迪股份有限公司 | 一种快恢复二极管的结构及其制造方法 |
CN104781907A (zh) * | 2013-11-13 | 2015-07-15 | 住友电气工业株式会社 | Iii族氮化物复合衬底及其制造方法、层叠的iii族氮化物复合衬底、iii族氮化物半导体器件及其制造方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001015769A (ja) * | 1999-07-02 | 2001-01-19 | Fuji Electric Co Ltd | 高耐圧半導体装置 |
US8097919B2 (en) * | 2008-08-11 | 2012-01-17 | Cree, Inc. | Mesa termination structures for power semiconductor devices including mesa step buffers |
JP2012038932A (ja) * | 2010-08-06 | 2012-02-23 | Sumco Corp | 半導体ウェーハの薄厚化方法および貼り合せウェーハの製造方法 |
CN101950774A (zh) * | 2010-08-17 | 2011-01-19 | 中国科学院苏州纳米技术与纳米仿生研究所 | 四结GaInP/GaAs/InGaAsP/InGaAs太阳电池的制作方法 |
EP2645429A1 (en) * | 2012-03-28 | 2013-10-02 | Soitec | Manufacture of multijunction solar cell devices |
EP2645431A1 (en) | 2012-03-28 | 2013-10-02 | Soltec | Manufacture of multijuntion solar cell devices |
CN103219414B (zh) * | 2013-04-27 | 2016-12-28 | 中国科学院苏州纳米技术与纳米仿生研究所 | GaInP/GaAs/InGaAsP/InGaAs四结级联太阳电池的制作方法 |
CN104701162A (zh) * | 2013-12-06 | 2015-06-10 | 江苏物联网研究发展中心 | 半导体器件、pin二极管和igbt的制作方法 |
US9425351B2 (en) * | 2014-10-06 | 2016-08-23 | Wisconsin Alumni Research Foundation | Hybrid heterostructure light emitting devices |
US9899556B2 (en) * | 2015-09-14 | 2018-02-20 | Wisconsin Alumni Research Foundation | Hybrid tandem solar cells with improved tunnel junction structures |
-
2016
- 2016-12-17 DE DE102016015056.4A patent/DE102016015056A1/de not_active Withdrawn
-
2017
- 2017-12-12 EP EP17002021.8A patent/EP3336906B1/de active Active
- 2017-12-15 JP JP2017240696A patent/JP6649935B2/ja active Active
- 2017-12-18 CN CN201711365600.8A patent/CN108346576B/zh active Active
- 2017-12-18 US US15/845,530 patent/US10192745B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01259570A (ja) * | 1988-04-11 | 1989-10-17 | Toshiba Corp | 半導体装置及びその製造方法 |
US20020048900A1 (en) * | 1999-11-23 | 2002-04-25 | Nova Crystals, Inc. | Method for joining wafers at a low temperature and low stress |
US20100233839A1 (en) * | 2009-01-29 | 2010-09-16 | Emcore Solar Power, Inc. | String Interconnection and Fabrication of Inverted Metamorphic Multijunction Solar Cells |
CN102810466A (zh) * | 2011-05-10 | 2012-12-05 | Soitec公司 | 用于制造半导体衬底的方法 |
CN103700712A (zh) * | 2012-09-27 | 2014-04-02 | 比亚迪股份有限公司 | 一种快恢复二极管的结构及其制造方法 |
CN104781907A (zh) * | 2013-11-13 | 2015-07-15 | 住友电气工业株式会社 | Iii族氮化物复合衬底及其制造方法、层叠的iii族氮化物复合衬底、iii族氮化物半导体器件及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
EP3336906B1 (de) | 2019-04-10 |
CN108346576B (zh) | 2021-03-16 |
EP3336906A1 (de) | 2018-06-20 |
JP6649935B2 (ja) | 2020-02-19 |
US20180174841A1 (en) | 2018-06-21 |
DE102016015056A1 (de) | 2018-06-21 |
US10192745B2 (en) | 2019-01-29 |
JP2018107441A (ja) | 2018-07-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN108346576A (zh) | 由p+衬底、p-层、n-层和第三层构成的层堆叠的制造方法 | |
CN109478591B (zh) | 用于RF滤波器应用的外延AlN/稀土氧化物结构 | |
TWI441337B (zh) | 在通道區域下具有delta摻雜層之第三-五族裝置 | |
CN101896998B (zh) | 半导体基板、半导体基板的制造方法及电子器件 | |
US7626217B2 (en) | Composite substrates of conductive and insulating or semi-insulating group III-nitrides for group III-nitride devices | |
JP2014527302A (ja) | 酸化物半導体基板上の縦型電界効果トランジスタおよびその製造方法 | |
CN103367115A (zh) | 半导体基板、半导体基板的制造方法及电子器件 | |
JP2008227356A (ja) | 半導体装置とその製造方法 | |
EP2920817B1 (en) | Gan-based schottky diode having partially recessed anode and method of manufacturing the same | |
CN106158946A (zh) | 具有周期性碳掺杂的氮化镓的高电子迁移率晶体管 | |
US20150123124A1 (en) | Rotated channel field effect transistor | |
FR3030114A1 (fr) | Transistor hemt | |
WO2023022768A2 (en) | Epitaxial nitride ferroelectronics | |
WO2015052456A1 (fr) | Transistor hemt à base d'heterojonction | |
US9960249B2 (en) | Semiconductor heterobarrier electron device and method of making | |
TWI753915B (zh) | 用於GaN基底應用的磷屬化物緩衝結構和裝置 | |
US20060057790A1 (en) | HEMT device and method of making | |
US11430875B2 (en) | Method for manufacturing transistor | |
JP2012190990A (ja) | タンデム太陽電池セル | |
CN102683352B (zh) | 硅层转印基板以及半导体基板的制造方法 | |
JP2010177416A (ja) | 窒化物半導体装置 | |
US20230395707A1 (en) | Electronic component, method for the control thereof, and method for producing an electronic component | |
US20150214326A1 (en) | Nitride semiconductor schottky diode and method for manufacturing same | |
CN113643978A (zh) | 复合衬底的制备方法及复合衬底 | |
JP6441767B2 (ja) | 半導体装置およびその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |