CN108307661B - 全模制的微型化半导体模块 - Google Patents

全模制的微型化半导体模块 Download PDF

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Publication number
CN108307661B
CN108307661B CN201680067827.1A CN201680067827A CN108307661B CN 108307661 B CN108307661 B CN 108307661B CN 201680067827 A CN201680067827 A CN 201680067827A CN 108307661 B CN108307661 B CN 108307661B
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semiconductor die
smd
semiconductor
encapsulant
layer
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CN108307661A (zh
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克里斯多佛·M·斯坎伦
提莫泽·L·奥森
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Decca Technology Inc
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Decca Technology Inc
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Priority claimed from US15/354,447 external-priority patent/US9831170B2/en
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    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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    • H01L2224/24135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
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  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
CN201680067827.1A 2015-11-20 2016-11-18 全模制的微型化半导体模块 Active CN108307661B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201562258040P 2015-11-20 2015-11-20
US62/258,040 2015-11-20
US15/354,447 US9831170B2 (en) 2011-12-30 2016-11-17 Fully molded miniaturized semiconductor module
US15/354,447 2016-11-17
PCT/US2016/062940 WO2017087899A1 (en) 2015-11-20 2016-11-18 Fully molded miniaturized semiconductor module

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CN108307661A CN108307661A (zh) 2018-07-20
CN108307661B true CN108307661B (zh) 2022-07-08

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HK (1) HK1256963A1 (ko)
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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9831170B2 (en) * 2011-12-30 2017-11-28 Deca Technologies, Inc. Fully molded miniaturized semiconductor module
KR102563424B1 (ko) * 2017-11-02 2023-08-07 주식회사 아모센스 반도체 패키지 및 모바일용 전자기기
US10608638B2 (en) * 2018-05-24 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
US11114311B2 (en) * 2018-08-30 2021-09-07 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure and method for forming the same
KR102179167B1 (ko) * 2018-11-13 2020-11-16 삼성전자주식회사 반도체 패키지
US11183482B2 (en) 2019-09-17 2021-11-23 Taiwan Semiconductor Manufacturing Company, Ltd. Shift control method in manufacture of semiconductor device
US11515174B2 (en) * 2019-11-12 2022-11-29 Micron Technology, Inc. Semiconductor devices with package-level compartmental shielding and associated systems and methods
TWI829379B (zh) * 2021-10-12 2024-01-11 南韓商Wit有限公司 大面積監視設備
CN117525039A (zh) * 2022-07-30 2024-02-06 华为技术有限公司 芯片封装结构及其制作方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103187322A (zh) * 2011-12-30 2013-07-03 赛普拉斯半导体公司 充分成型的扇出

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5759737A (en) 1996-09-06 1998-06-02 International Business Machines Corporation Method of making a component carrier
US6972481B2 (en) * 2002-09-17 2005-12-06 Chippac, Inc. Semiconductor multi-package module including stacked-die package and having wire bond interconnect between stacked packages
TWI229433B (en) * 2004-07-02 2005-03-11 Phoenix Prec Technology Corp Direct connection multi-chip semiconductor element structure
US20090170241A1 (en) * 2007-12-26 2009-07-02 Stats Chippac, Ltd. Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier
US9196509B2 (en) * 2010-02-16 2015-11-24 Deca Technologies Inc Semiconductor device and method of adaptive patterning for panelized packaging
US8268677B1 (en) * 2011-03-08 2012-09-18 Stats Chippac, Ltd. Semiconductor device and method of forming shielding layer over semiconductor die mounted to TSV interposer
TWI543307B (zh) * 2012-09-27 2016-07-21 欣興電子股份有限公司 封裝載板與晶片封裝結構
US9269622B2 (en) * 2013-05-09 2016-02-23 Deca Technologies Inc. Semiconductor device and method of land grid array packaging with bussing lines
KR101601388B1 (ko) * 2014-01-13 2016-03-08 하나 마이크론(주) 반도체 패키지 및 그 제조 방법

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103187322A (zh) * 2011-12-30 2013-07-03 赛普拉斯半导体公司 充分成型的扇出

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TW201729373A (zh) 2017-08-16
KR20180084877A (ko) 2018-07-25
KR102127774B1 (ko) 2020-06-29
WO2017087899A1 (en) 2017-05-26
TWI674658B (zh) 2019-10-11
HK1256963A1 (zh) 2019-10-04
CN108307661A (zh) 2018-07-20

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