CN107078133B - 制备用于全模制封装的3d互连部件的方法 - Google Patents

制备用于全模制封装的3d互连部件的方法 Download PDF

Info

Publication number
CN107078133B
CN107078133B CN201680003401.XA CN201680003401A CN107078133B CN 107078133 B CN107078133 B CN 107078133B CN 201680003401 A CN201680003401 A CN 201680003401A CN 107078133 B CN107078133 B CN 107078133B
Authority
CN
China
Prior art keywords
substrate
semiconductor die
conductive
component
temporary carrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201680003401.XA
Other languages
English (en)
Other versions
CN107078133A (zh
Inventor
C.M.斯坎伦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Decca Technology Inc
Original Assignee
Decca Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Decca Technology Inc filed Critical Decca Technology Inc
Publication of CN107078133A publication Critical patent/CN107078133A/zh
Application granted granted Critical
Publication of CN107078133B publication Critical patent/CN107078133B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13113—Bismuth [Bi] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
    • H01L2224/2731—Manufacturing methods by local deposition of the material of the layer connector in liquid form
    • H01L2224/2732—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
    • H01L2224/2733—Manufacturing methods by local deposition of the material of the layer connector in solid form
    • H01L2224/27334—Manufacturing methods by local deposition of the material of the layer connector in solid form using preformed layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/27444—Manufacturing methods by blanket deposition of the material of the layer connector in gaseous form
    • H01L2224/2745—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2746—Plating
    • H01L2224/27462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2746—Plating
    • H01L2224/27464—Electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29113—Bismuth [Bi] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/29124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/29294—Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/292 - H01L2224/29291
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32227—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/83815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83909—Post-treatment of the layer connector or bonding area
    • H01L2224/8391—Cleaning, e.g. oxide removal step, desmearing
    • H01L2224/83911—Chemical cleaning, e.g. etching, flux
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83909—Post-treatment of the layer connector or bonding area
    • H01L2224/8391—Cleaning, e.g. oxide removal step, desmearing
    • H01L2224/83913—Plasma cleaning
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H01L23/295—Organic, e.g. plastic containing a filler
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Ceramic Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

本发明公开了一种制备半导体部件封装的方法，该方法可包括：提供包括导电迹线的基板；利用焊料将表面安装装置(SMD)焊接至该基板；利用第一模制化合物在该SMD上方并围绕该SMD包封该基板上的该SMD以形成部件组件；以及将该部件组件安装至临时载体，其中该部件组件的第一侧面朝向该临时载体取向。该方法还可包括：将包括导电互连件的半导体模片邻近该部件组件安装至该临时载体；利用第二模制化合物包封该部件组件和该半导体模片以形成重构板材；以及使该导电互连件和导电迹线相对于该第二模制化合物暴露在该部件组件的第一侧面和第二侧面处。

Description

制备用于全模制封装的3D互连部件的方法
相关申请的交叉引用
本公开要求2015年4月29日申请的名称为“3D Interconnect Component forFully Molded Packages”的美国临时专利62/154,218的权益(包括申请日期)，该专利的公开内容以引用方式并入本文。
技术领域
本公开涉及用于全模制封装的三维(3D)互连部件或部件组件，包括旋转可焊接部件组件。全模制封装可包括多个整合式半导体装置，包括部件组件，该多个整合式半导体装置用于可穿戴科技、物联网(IoT)装置、或两者。
背景技术
半导体装置常见于现代电子产品中。半导体装置具有不同的电部件数量和电部件密度。离散半导体装置一般包含一种类型电部件，例如，发光二极管(LED)、小信号晶体管、电阻器、电容器、电感器、以及功率金属氧化物半导体场效应晶体管(MOSFET)。整合式半导体装置一般包含数百至数百万个电部件。整合式半导体装置的示例包括微控制器、微处理器、电荷耦合装置(CCD)、太阳能电池、以及数字微镜装置(DMD)。
半导体装置执行各式各样的功能，诸如信号处理、高速计算、传输以及接收电磁信号、控制电子装置、将日光转变成电力、以及建立用于电视显示器的视觉投影。在娱乐、通信、功率转换、网络、计算机、以及消费性产品领域中可见到半导体装置。军事应用、航空、汽车、工业控制器、以及办公室设备中也可见到半导体装置。
半导体装置利用半导体材料的电性质。半导体材料的原子结构允许通过施加电场或基极电流或通过掺杂程序来操纵其导电性。掺杂将杂质引入至半导体材料中，以操纵和控制半导体装置的导电性。
半导体装置包含有源和无源电结构。有源结构(包括双极性和场效应晶体管)控制电流的流动。通过改变掺杂的电平以及电场或基极电流施加的电平，晶体管促进或限制电流的流动。无源结构(包括电阻器、电容器和电感器)建立执行各式各样电功能所需的电压与电流之间的关系。无源结构和有源结构电连接以形成电路，其使得半导体装置能够执行高速计算以及其他实用的功能。
一般使用两个复杂的制造程序来制造半导体装置，即，前端制造和后端制造，各自可能涉及数百个步骤。前端制造涉及在半导体晶圆的表面上形成多个半导体模片。每个半导体模片一般是相同的并且包含通过电连接有源部件和无源部件而形成的电路。后端制造涉及从晶圆成品单切单个半导体模片并且封装该模片，以提供结构支撑和环境隔离。如本文所用，术语“半导体模片”是指该字词的单数形式和复数形式两者，并且因此可指单个半导体装置和多个半导体装置两者。
半导体制造的一个目标是生产较小的半导体装置。较小装置一般消耗较少电力、具有较高性能，并且可被更有效地生产。此外，较小半导体装置具有较小占有面积，这对较小最终产品是所期望的。可通过前端程序的改进来实现较小半导体模片大小，从而得到具有较小的较高密度有源部件和无源部件的半导体模片。后端程序可通过电互连和封装材料的改进而得到具有较小占有面积的半导体装置封装。
半导体模片的后端处理也可包括多个表面安装装置(SMD)、无源部件、或两者的整合，其用于将半导体模片或集成电路连接至基板表面和PCB，而不使用PCB中的通孔。四面扁平封装(QFP)使用SMD，该SMD包括从封装的四个侧面中的每个侧面延伸的引线，该引线有时被称为“鸥翼引线”。QFP引线提供封装内的半导体模片与安装有QFP的PCB或基板之间的电输入/输出(I/O)互连。其他SMD封装在无引线的情况下制备并且常常是指扁平无引线封装。扁平无引线封装的示例是四面扁平无引线封装(QFN)和双面扁平无引线(DFN)封装。QFN封装常规地包括通过线接合而连接至用于封装I/O互连的引线架的半导体模片。
无源部件在扇出型晶圆级封装(FO-WLP)中的整合一般通过在模制或包封无源部件之前将无源部件直接放置到临时载带上来进行。在嵌入式晶圆级球栅阵列(eWLB)情况中，半导体模片的有源表面以及无源部件可附接至胶带，然后包覆模制或包封以形成并重构晶圆或板材。在释离该胶带之后，可暴露半导体模片和无源部件的端子或接触焊盘，并且重分布层可被施加至板材，使得导电迹线可制备至无源部件的连接。通常，焊接至基板的SMD无源件附接在基板内的核心层上，以形成基板中嵌入式模片的施加。
发明内容
存在改良半导体制造的机会。因此，在一项方面中，一种制备半导体部件封装的方法可包括：提供基板，该基板包括导电迹线；利用焊料将多个表面安装装置(SMD)焊接至该基板；利用第一模制化合物在该多个SMD上方并围绕该多个SMD包封该基板上的多个SMD；以及通过分开该基板来单切该多个SMD，以暴露导电迹线并形成多个部件组件，该多个部件组件包括在部件组件的第一侧面以及在此类部件组件的第二侧面的暴露的导电迹线，此类部件组件的第二侧面与此类部件组件的第一侧面相对。该方法还可包括：提供临时载体；将部件组件中的至少一者安装至该临时载体，其中该至少部件组件的该第一侧面以及经暴露的导电迹线朝向该临时载体取向；将包括导电互连件的半导体模片安装至该临时载体，该半导体模片邻近此类部件组件中的至少一者；在该至少一经单切的部件组件以及该半导体模片安装至该临时载体时，利用第二模制化合物包封此类部件组件中的至少一者以及该半导体模片，以形成重构板材；以及使该导电互连件以及经暴露的导电迹线相对于该第二模制化合物暴露在该至少部件组件的第一侧面或第二侧面处。该方法还可包括：在该第二模制化合物上方形成第一重分布层，以将该导电互连件和经暴露的导电迹线电连接；以及单切该重构板材。
制备半导体部件封装的方法还可包括基板，该基板包括两层层压层、印刷电路板(PCB)、或坯料模制化合物板材。部件组件可包括无源装置。半导体模片可为嵌入式半导体模片，该嵌入式半导体模片包括耦接至该半导体模片并相对于该第二模制化合物暴露的导电互连件。导电互连件可包括铜凸块、支柱、立柱、或厚RDL迹线。将经单切的部件组件中的至少一者耦接至基板的焊料可包含在半导体部件封装内，并且相对于半导体部件封装不暴露。
在另一项方面中，一种制备半导体部件封装的方法可包括：提供基板，该基板包括导电迹线；利用焊料将SMD附接至该基板以形成部件组件；将该部件组件安装至临时载体，其中该部件组件的第一侧面朝向该临时载体取向；将包括导电互连件的半导体模片邻近该部件组件安装至该临时载体；在该部件组件以及该半导体模片安装至该临时载体时，利用模制化合物包封该部件组件以及该半导体模片，以形成重构板材；以及使该导电互连件以及导电迹线相对于该模制化合物暴露在该部件组件的第一侧面或第二侧面处。
制备半导体部件封装的方法还可包括基板，该基板包括两层层压层、PCB、或坯料模制化合物板材。在将该部件组件安装至该临时载体之前，可利用附加模制化合物在该SMD上方并围绕该SMD包封基板上的SMD。半导体模片可为嵌入式半导体模片，该嵌入式半导体模片包括耦接至该半导体模片并相对于模制化合物暴露的导电互连件，其中该导电互连件包括铜凸块、支柱、立柱、或厚RDL迹线。将部件组件耦接至基板的焊料可包含在部件组件内，并且相对于部件组件不暴露。可通过从重构板材移除临时载体并研磨重构板材来使导电互连件以及导电迹线暴露。第一重分布层可形成于重构板材上方，以电连接导电互连件以及导电迹线，并且第二重分布层可形成为与第一重分布层相对以电连接经暴露的导电迹线，以形成穿过半导体部件封装的厚度的电连接。
在另一项方面中，一种制备半导体部件封装的方法可包括：提供基板，该基板包括导电迹线；利用焊料将SMD附接至该基板；将该SMD以及该基板安装至临时载体；邻近该SMD安装包括导电互连件的半导体模片；将模制化合物分配于该临时载体上方；以及使该导电互连件以及此类导电迹线相对于该模制化合物暴露。
制备半导体部件封装的方法还可包括邻近临时载体安装包括导电互连件的半导体模片。包括半导体互连件的半导体模片可邻近SMD安装。模制化合物可经分配以包封SMD以及半导体模片，从而形成重构板材。该方法还可包括：单切基板以使导电迹线暴露在基板的第一侧面处；以及将SMD和基板安装至临时载体，其中基板的第一侧面以及经暴露的导电迹线朝向临时载体取向。基板可包括两层层压层、印刷电路板(PCB)、或坯料模制化合物板材。导电互连件可包括铜凸块、支柱、立柱、或厚RDL迹线。
本领域技术人员将可自具体实施方式与附图以及权利要求书清楚了解前述以及其他方面、特征以及优点。
附图说明
图1示出从重构板材30单切的嵌入式半导体模片。
图2A至图2F示出部件组件、SMD部件组件、或3D互连部件的形成。
图3A至图3F示出包括可焊接部件组件、SMD部件组件、或3D互连部件的半导体部件封装的形成。
具体实施方式
本公开参照附图在以下描述中包括一个或多个方面或实施方案，其中相似数字代表相同或类似的元件。本领域技术人员应理解，描述意图覆盖如通过随附权利要求书所限定的可包括于本公开的实质和范围内的替代方案、修改、以及等效物，以及如通过以下公开以及说明书附图所支持的其效物。在描述中，阐述许多特定细节，诸如特定构型、组成和程序等，以提供对本公开的透彻理解。在其他情况中，为了不混淆本公开，未描述熟知的程序以及制造技术的具体细节。此外，图中所示的各种实施方案是说明性代表且不必按比例绘制。
本公开、其方面以及实施方式不受限于本文中所公开的特定设备、材料类型、或其他系统部件示例或方法。设想与制造和封装一致的本技术领域中已熟知的许多附加部件、制造以及装配过程，以与本公开的具体实施方式一起使用。因此，例如，虽然公开了具体实施方式，但是此类实施方式以及实施的部件可包括如本技术领域中已熟知的用于此类系统以及实施的部件的任何部件、型号、类型、材料、版本、量、和/或类似者，此类系统和实施的部件与意图的操作一致。
本文使用字词“示例性”、“示例”或其各种形式意指用作示例、实例、或图解阐释。本文描述“示例性”或为“示例”的任何方面或设计非必然视为优选或优点优于其他方面或设计。另外，示例仅为了清楚以及理解的目的而提供并且非意欲以任何方式限制或限定所公开的主体或本公开的相关部分。应当理解，可呈现不同范围的众多附加或替代示例，但出于简洁的目的加以省略。
在以下示例、实施方案和实施方式参考示例的情况下，本领域技术人员应了解，其他制造装置和示例可与所提供的装置和示例互混或取代所提供的装置和示例。在上文描述参考特定实施方案的地方，应显而易见，可进行多种修改而不会脱离其实质，并且显而易见，这些实施方案和实施方式也可应用于其他技术。因此，所公开的主题意图涵盖所有此类变更、修改和变化，其均落入本公开的实质和范围以及本领域技术人员的知识内。
通常使用两个复杂的制造程序来制造半导体装置：前端制造和后端制造。前端制造涉及在半导体晶圆的表面上形成多个模片。该晶圆上的每个模片包含电连接以形成功能电路的有源电部件和无源电部件。有源电部件(诸如晶体管和二极管)具有控制电流的流动的能力。无源电部件(诸如电容器、电感器、电阻器和变压器)建立执行电路功能所需的电压与电流之间的关系。
无源部件和有源部件通过一系列程序步骤形成于半导体晶圆的表面上方，包括掺杂、沉积、光刻法、蚀刻、以及平坦化。掺杂通过诸如离子植入或热扩散的技术而将杂质引入到半导体材料中。掺杂程序修改有源装置中的半导体材料的导电性，将半导体材料转变成绝缘体、导体，或响应于电场或基极电流而动态地改变半导体材料导电性。晶体管包含被配置成所需的不同类型和掺杂程度的区域，以在施加电场或基极电流时使得晶体管能够促进或限制电流的流动。
有源部件和无源部件由具有不同电性质的材料的层形成。可通过各式各样沉积技术来形成层，部分地根据所沉积的材料的类型来决定沉积技术。例如，薄膜沉积可涉及化学气相沉积(CVD)、物理气相沉积(PVD)、电解电镀、以及无电解电镀程序。每个层通常被图案化以形成有源部件的部分、无源部件的部分、或位于部件之间的电连接的部分。
可使用光刻法来将层图案化，该光刻法涉及沉积光敏材料(例如，光致抗蚀剂)于待图案化的层上方。使用光将图案从光掩膜转移至光致抗蚀剂。在一个实施方案中，使用溶剂移除光致抗蚀剂图案的经受光的部分，从而暴露待图案化的下面层的部分。在另一实施方案中，使用溶剂移除光致抗蚀剂图案的未经受光的部分(负光致抗蚀剂)，从而暴露待图案化的下面层的部分。移除光致抗蚀剂的其余部分，从而留下图案化的层。另选地，一些类型的材料通过使用诸如无电解和电解电镀的技术将该材料直接沉积于通过先前沉积/蚀刻程序所形成的区或空隙中而图案化。
图案化是移除半导体晶圆表面上的顶部层的部分的基本操作。可使用光刻法、光掩膜、掩膜、氧化物或金属移除、摄影以及模板印刷、以及显微蚀刻来移除半导体晶圆的部分。光刻法包括：在光罩或光掩膜中形成图案；以及转移该图案至半导体晶圆的表面层中。光刻法以两步骤式程序将有源和无源部件的水平尺寸形成在半导体晶圆的表面上。第一，将光罩或光掩膜的图案转移至光致抗蚀剂层上。光致抗蚀剂是在暴露于光时经历结构和性质改变的光敏材料。改变光致抗蚀剂的结构和性质的程序作为负型作用光致抗蚀剂或正型作用光致抗蚀剂发生。第二，将光致抗蚀剂层转移至晶圆表面中。转移发生在蚀刻移除半导体晶圆的顶部层的未被光致抗蚀剂覆盖的部分时。光致抗蚀剂的化学性质使得该光致抗蚀剂实质上保持完整，并且在移除半导体晶圆的顶部层的未被光致抗蚀剂覆盖的部分时，抵抗被化学蚀刻溶液移除。可根据使用的特定光致抗蚀剂以及所期望的结果来修改形成、暴露以及移除光致抗蚀剂的程序，以及修改移除半导体晶圆的一部分的程序。
在负型作用光致抗蚀剂中，光致抗蚀剂暴露于光，并且在已知为聚合的程序从可溶状况变为不可溶状况。在聚合中，使未聚合材料暴露于光或能量源，并且聚合物形成交联材料，该交联材料是抗蚀剂。在大多数负光致抗蚀剂中，聚合物是聚异戊二烯。用化学溶剂或显影剂移除可溶部分(即，未暴露于光的部分)在光致抗蚀剂层中留下对应于光罩上的不透明图案的孔洞。图案存在于不透明区域中的光掩膜被称为清场光掩膜。
在正型作用光致抗蚀剂中，光致抗蚀剂暴露于光并且在已知为光溶解化的程序中从相对非可溶状况变为更可溶状况。在光溶解化中，相对不可溶光致抗蚀剂曝光于适当的光能量并且被转换成较可溶状态。在显影程序中，可通过溶剂移除光致抗蚀剂的光溶解化部分。基本正光致抗蚀剂聚合物为酚-甲醛聚合物，还被称为酚-甲醛酚醛树脂。用化学溶剂或显影剂移除可溶部分(即，暴露于光的部分)在光致抗蚀剂层中留下对应于光罩上的透明图案的孔洞。图案存在于透明区域中的光掩膜被称为暗场光掩膜。
在移除半导体晶圆的未被光致抗蚀剂覆盖的顶部部分之后，移除光致抗蚀剂的其余部分，而留下图案化的层。另选地，一些类型材料是通过使用诸如无电解和电解电镀的技术将该材料直接沉积于通过先前沉积/蚀刻程序所形成的区或空隙中而图案化。
将材料的薄膜沉积于现有图案上方可增大下面的图案并且建立非均匀的平坦表面。均匀的平坦表面可对于生产较小且更致密聚集的有源部件和无源部件来说是有益的或需要的。平坦化可用于从晶圆的表面移除材料并且产生均匀的平坦表面。平坦化涉及用抛光垫抛光晶圆的表面。在抛光期间，将研磨材料和腐蚀性化学品添加至晶圆的表面。另选地，在不使用腐蚀性化学品的情况下，将机械研磨用于平坦化。在一些实施方案中，纯机械研磨通过使用带式研磨机、标准晶圆背面研磨器、或其他类似的机器而实现。组合的研磨机械作用以及化学腐蚀作用移除任何不规则形貌，从而导致均匀的平坦表面。
后端制造是指将晶圆成品切割或单切成单个半导体模片，然后封装半导体模片以用于结构支撑和环境隔离。为了单切半导体模片，沿称为锯道或划线的晶圆的非功能区域切割晶圆。使用雷射切割工具或锯刃单切晶圆。在单切之后，单个半导体模片被安装至封装基板，该封装基板包括用于与其他系统部件互连的接针或接触焊盘。接着，形成于半导体模片上方的接触焊盘连接至封装内的接触焊盘。可用焊料凸块、柱形凸块、导电膏、重分布层、或线接合来制备电连接。包封物或其他模制材料沉积于封装上方，以提供物理支撑和电隔离。接着，将成品封装插入电系统中，并且使半导体装置的功能可供其他系统部件使用。
电系统可为独立系统，该独立系统使用半导体装置执行一个或多个电功能。另选地，电系统可为较大系统的子部件。例如，电系统可为蜂窝无线电话的部分、个人数字助理(PDA)的部分、数字视频摄影机(DVC)的部分、或其他电子通信装置的部分。另选地，电系统可为图形适配器、网络适配器、或可插入计算机中的其他信号处理卡。半导体封装可包括微处理器、内存、特殊应用集成电路(ASIC)、逻辑电路、模拟电路、RF电路、离散装置、或其他半导体模片或电部件。小型化以及重量减轻可对于待被市场所接受的产品而言是有益的或必需的。为实现较高密度，必须减小半导体装置之间的距离。
通过将一个或多个半导体封装组合于单个基板上方，制造商可将预制备部件并入电子装置和系统中。因为半导体封装包括复杂的功能性，所以电子装置可使用较便宜的部件和效率化制造程序来制造。所得装置不太可能发生故障并且制造成本更低，使得消费者的花费更低。
但是，当将一个或多个半导体封装于单基板上方时，在具有焊料或镀锡(Sn)终端的标准可焊接无源部件上方形成RDL层可为不实用的，因为焊料或Sn可在后续处理期间熔化，造成电故障。因此，使用其他替代方案以减少故障，诸如使用较昂贵的具有裸Cu终端的部件而非使用Sn或可焊接部件，从而通过减少故障来减少成本。在焊料或Sn焊接的情况下使用标准可焊接无源部件的另一个替代方案包括放置SMD无源件至基板核心层，以在基板中形成嵌入式模片、装置、或部件，这允许使用可焊接无源部件，同时减少在后续处理期间熔化焊料和Sn的风险，以及导致的故障。然而，将SMD无源件放置在基板中会增加封装的厚度，并且会需要大得多的预制基板面积，从而增加大小和成本，此两者均为不期望的。
图1示出多个半导体模片14的截面图，该多个半导体模片是根据如上文所述的前端制造方法以及过程所形成且包括在重构板材、板材、重构晶圆、或晶圆30内。更具体地，半导体模片14可由半导体晶圆或原生晶圆形成，或形成为半导体晶圆或原生晶圆的一部分，该半导体晶圆或原生晶圆具有用于结构支撑的基础基板材料，诸如但不限于硅、锗、砷化镓、磷化铟、或碳化硅。多个半导体模片或部件14可形成于原生晶圆上并且可通过如上文所述的非作用的模片间晶圆区或锯道分开。锯道提供将半导体晶圆单切成单个半导体模片14的切割区，该单个半导体模片用于包括在重构板材或晶圆30中，该重构板材或晶圆也可包括嵌入式模片板材。
每个半导体模片14具有背侧或背表面18以及与背侧18相对的有源表面20。有源表面20包含模拟电路或数字电路，模拟电路或数字电路实施为形成在模片内的有源装置、无源装置、导电层以及介电层，并且根据模片的电设计以及功能而电互连。例如，电路可包括形成在有源表面20内的一个或多个晶体管、二极管以及其他电路元件，以实施模拟电路或数字电路，诸如DSP、ASIC、内存或其他信号处理电路。半导体模片14也可包含用于RF信号处理的IPD，诸如电感器、电容器和电阻器。
使用PVD、CVD、电解电镀、无电解电镀制程、或其他合适的金属沉积程序在有源表面20上方形成导电层22。导电层22可为铝(A1)、铜(Cu)、Sn、镍(Ni)、金(Au)、银(Ag)、或其他合适的导电材料的一个或多个层。导电层22用作电耦合或电连接至有源表面20上的电路的接触焊盘或接合焊盘。导电层22可被形成为并排设置距半导体模片14的边缘第一距离的接触焊盘，如图1中所示。另选地，导电层22可被形成为在多列中偏移的接触焊盘，使得第一列接触焊盘被设置成距模片的边缘第一距离，而与该第一列交替的第二列接触焊盘被设置成距模片的边缘第二距离。
图1还示出保形施加于有源表面20上方以及导电层22上方的可选的绝缘层或钝化层26。绝缘层26可包括一个或多个层，其使用PVD、CVD、网板印刷、旋涂、喷涂、烧结、热氧化、或其他合适的程序施加。绝缘层26可包含但不限于二氧化硅(SiO2)、氮化硅(Si3N4)、氮氧化硅(SiON)、五氧化钽(Ta2O5)、氧化铝(Al2O3)、聚合物、聚酰亚胺、苯环丁烯(BCB)、聚苯并
Figure GDA0003124612940000101
唑(PBO)、或具有类似的绝缘以及结构性质的其他材料的一个或多个层。另选地，在不使用任何PBO层的情况下封装半导体模片14，并且绝缘层26可由不同材料形成或被彻底省略。在另一实施方案中，绝缘层26包括钝化层，该钝化层形成于有源表面20上方而不设置于导电层22上方。当绝缘层26存在且形成于导电层22上方时，形成完全穿过绝缘层26的开口以暴露导电层22的至少一部分，从而实现后续机械且电互连。另选地，当绝缘层26被省略时，导电层22暴露，从而在不形成开口的情况下实现后续电互连。
图1还示出导电互连件或电互连结构28，导电互连件或电互连结构28可形成为由铜或其他合适的导电材料所形成的管柱、支柱、立柱、厚RDLS、凸块、或柱形物，其设置于导电层22上方并耦接或连接至导电层22。可使用图案化以及金属沉积程序(诸如印刷、PVD、CVD、溅镀、电解电镀、无电解电镀、金属蒸镀、金属溅镀、或其他合适的金属沉积程序)将导电互连件28直接形成于导电层22上。导电互连件28可为Al、Cu、Sn、Ni、Au、Ag、钯(Pd)、或其他合适的导电材料的一个或多个层并且可包括一个或多个UBM层。在一些实施方案中，可通过将光致抗蚀剂层沉积于半导体模片14以及导电层22上方来形成导电互连件28。可通过蚀刻显影程序来暴露并移除光致抗蚀剂层的一部分，并且导电互连件28可使用选择电镀程序以铜支柱的形式形成于光致抗蚀剂的移除部分中以及导电层22上方。可移除光致抗蚀剂层，留下导电互连件28，这提供后续机械且电互连以及相对于有源表面20的支脚。导电互连件28可包括在10至100微米(μm)的范围内的高度H1或在20至50μm的范围内的高度、或约35μm的高度。
可使用膏印刷、压缩模制、转移模制、液体包封物模制、层压、真空层压、旋涂、或其他合适的施用器来将包封物42沉积成围绕多个半导体模片14。包封物42可为聚合物复合材料，诸如含填料的环氧树脂、含填料的环氧丙烯酸酯、或含适当填料的聚合物。半导体模片14可一起嵌入包封物42中，包封物42可为非导电性并在环境上保护半导体模片14免于外部元素以及污染物的侵害。
半导体模片14的取向可为面向上，其中有源表面20远离安装有半导体模片14的载体取向，或另选地可安装成面向下，其中有源表面20朝向安装有半导体模片14的载体取向。因此，黏着剂41可包括在半导体模片14的背表面18上方或从半导体模片14的背表面18上方省略，其取决于包封半导体模片14以及形成板材30所使用的程序，板材30包括全模制于包封物42的核心中或在环氧树脂核心内的半导体模片14。
板材30可以可选地经历固化程序以固化包封物42。包封物42的表面可实质上与黏着剂41共面。另选地，包封物42可实质上与背侧18共面，通过移除载体以及界面层而使该包封物暴露。板材30可包括任何形状以及大小的占有面积或形状因数，包括圆形、矩形、或方形，诸如类似于包括具有300毫米(mm)直径的圆形占有面积的300mm半导体晶圆的形状因数的形状因数。也可形成任何其他所期望的大小。
板材30可利用研磨机经历可选的研磨操作以平坦化表面并减小板材30的厚度。也可使用化学蚀刻以移除并平坦化板材30中的包封物42的一部分。因此，导电互连件28的表面可相对于包封物42在板材30的边缘或周边暴露，以在半导体模片14与后续形成的重分布层或互连结构之间提供电连接。可使用锯刃或雷射切割工具32穿过间隙或锯道40将板材30单切成单个嵌入式半导体模片44。嵌入式半导体模片44可随后用作后续形成的半导体部件封装的一部分，如下文更详细地讨论。然而，嵌入式半导体模片44也可在施加导电互连件28之后以及在嵌入式半导体模片44从板材30单切或装配至图3C中所示的重构板材112中之前为全部可测试的。
在一些情况下，嵌入式半导体模片44可如2015年4月29日提交的名称为“Die UpFully Molded Fan-out Wafer Level Packaging”的美国专利申请13/632,062(现为USP8,535,978)中所述形成，该申请的公开内容全文以引用方式并入本文。
图2A示出基板、层压层、印刷电路板(PCB)、或坯料模制化合物板材50的截面轮廓图。基板50可包括：导电迹线54，导电迹线54形成于基板核心或核心材料52的第一表面56上方；以及焊接焊盘58，焊接焊盘58形成于基板核心或核心材料52的第二表面60上方，第二表面60与第一表面56相对。当基板50形成为坯料模制化合物板材时，核心材料52可包括与包封物42、包封物或第一模制化合物78、或第二包封物或模制化合物110相同、类似、或功能上等效的材料或材料性质。
导电迹线54和焊接焊盘58可被图案化并沉积于基板50的基板核心52上方。在一些情况下，导电迹线54可在两者上形成为一个或多个重分布层(RDL)或RDL图案，其可形成于仅第一表面56、仅第二表面60、或第一表面56以及第二表面60两者上或上方。类似地，焊接焊盘58可形成于仅第一表面56、仅第二表面60、或第一表面56以及第二表面60两者上或上方。
导电迹线54、焊接焊盘58、或两者可为Al、Cu、Sn、Ni、Au、Ag、Ti/Cu、TiW/Cu、或偶合剂/Cu或其他合适的导电材料的一个或多个层。可使用PVD、CVD、电解电镀、无电解电镀、或其他合适的程序形成导电迹线54、焊接焊盘58、或两者。在一个实施方案中，导电迹线54、焊接焊盘58、或两者可包括Ti障壁层、Cu种层、以及形成于Ti障壁层以及Cu种层上方的Cu层，并且可提供与后续安装至基板或层压层50的部件的电互连。在一些情况下，基板或层压层50可为购买的或呈预成形或预制备项获得，并且两层层压基板50可包括130微米(μm)或约130μm(诸如在30至200μm范围内)的核心52。
绝缘层或钝化层62可设置于导电迹线54以及第一表面56上方。类似地，绝缘层或钝化层64可设置于焊接焊盘58以及第二表面60上方。绝缘层62以及64可为通过PVD、CVD、网板印刷、旋涂、喷涂、层压、烧结、或热氧化形成的SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚酰亚胺、BCB、PBO、环氧树脂、阻焊材料、或具有类似的绝缘以及结构性质的其他材料的一个或多个层。在一些情况下，绝缘层或钝化层62和64可包括在预成形或预制备基板或层压层50中。绝缘层64中的开口68可形成于焊接焊盘58的部分上方，以促进与表面安装装置(SMD)(如图2B中所示的SMD 70)上的一个或多个端子或接触焊盘72的后续电互连。
图2B示出使用焊料或焊料膏74将SMD 70的端子72表面安装至基板或层压层50。SMD 70可具有所期望的大小并且包括无源部件、有源部件、可焊接无源件(诸如电阻器或电容器)、其他半导体模片、IC、晶圆级芯片尺度封装(WLCSP)以及其他部件。SMD 70的大小可根据JDEC标准，利用公制代码或英制代码设定大小，其中公制代码以数十毫米给出SMD部件的长度以及宽度，并且英制代码以数百寸给出SMD部件的长度以及宽度，除了一些例外。在一些情况下，可使用0201 SMD封装大小，其包括约0.25mm×0.125mm(或.0098in×0.0049in)的尺寸。在其他情况下，0201封装的尺寸可包括0.6mm×0.3mm(或0.024in×0.012in)的尺寸。无论如何，在某些情况下，SMD的大小可选择成与最终封装的总体构型以及设计一致，如下文更详细地描述。
可将焊料74放置于焊接焊盘58上以促进SMD 70与基板50之间的电连通。焊料74可包括Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、以及它们的组合连同可选的助焊剂溶液。例如，焊料74可为共熔Sn/Pb、高铅焊料、或无铅焊料。可使用蒸镀、电解电镀、无电解电镀、球滴、或网板印刷程序来将焊料74沉积于基板50上方以及焊接焊盘58上。在一些实施方案中，焊料74为Sn焊料膏，其使用网板印刷沉积于基板50上方以及焊接焊盘58上。在SMD 70耦接至具有焊料74的基板50之后，焊料74可经历回焊程序或经回焊以改良SMD 70与焊接焊盘58之间的电接触。在回焊之后，基板50以及SMD 70可以可选地经历水性清洁、自动化光学检查(AOI)、以及电浆清洁中的一者或多者。
图2C示出可使用膏印刷、压缩模制、转移模制、液体包封物模制、层压、真空层压、旋涂、或其他合适的施用器将第一包封物或模制化合物78可选地沉积成围绕该多个SMD70。包封物78可为聚合物复合材料，诸如含填料的环氧树脂、含填料的环氧丙烯酸酯、或含适当填料的聚合物。在一些情况下，包封物78可相同于或类似于形成嵌入式半导体模片44中所用的包封物42。SMD 70可一起嵌入基板50上在包封物78中，包封物78可为非导电性并在环境上保护SMD 70免于外部元素以及污染物的侵害。在模制或包封之后，模制基板50以及SMD 70可经历后模制清洁(PMC)以及测试，以鉴别并标记模制基板内的任何坏的、缺陷的或不工作的SMD 70。尽管包封物或第一模制化合物78经示出形成或设置成围绕SMD 70以促进或使得将最终部件组件82更容易安装至临时载体100，如图3A中所示，但是包封物或第一模制化合物78可为可选的并可被彻底省略。在一些实施方案中，在包封物或第一模制化合物78为完全可选的情况下，可在不存在包封物或第一模制化合物78的情况下进行将最终部件组件82安装至临时载体100。
如图2D中所示，可随后使用锯刃或雷射切割工具80在SMD 70之间将模制基板50单切成单个部件组件、SMD部件组件、或包括包封物78的模盖的3D互连部件82。模制基板50的单切可分开基板50以暴露导电迹线54并形成多个部件组件或SMD部件组件82。部件组件82可包括经暴露的导电迹线84，包括导电迹线54、焊接焊盘58、或两者。经暴露的导电迹线84可在仅部件组件82的第一侧面86、仅部件组件82的第二侧面88、或第一侧面86以及第二侧面88两者暴露，其中第一侧面86可与第二侧面88相对。对于安装部件组件82而言，第一侧面86以及第二侧面88可为平的、平坦的、或实质上如此。部件组件82可包括在0.4至0.8mm、0.5至0.7mm的范围内、或约0.6mm(诸如0.62mm)的高度H。高度H可为模制化合物高度Hm以及基板高度Hs的总和。模制化合物高度Hm可在0.1至0.3mm的范围内、或为约0.2mm，诸如0.22mm。模制化合物高度Hs可在0.2至0.6mm的范围内、或为约0.4mm。部件组件82也可具有在0.9至1.3mm、1.0至1.2mm的范围内、或约1.1mm的长度L。
图2E示出部件组件82的截面轮廓图，该图示出部件组件82的宽度W，并且示出部件组件82的方向，该方向垂直于或正交于图2D中所示视图的方向。部件组件82的宽度W可在0.2至0.6mm、0.3至0.5mm的范围内、或为约0.4mm，诸如0.43mm。尽管部件组件82的长度L、宽度W、以及高度H的示例性测量涉及0201SMD 70给出，但是也可使用不同大小的SMD，从而将导致部件组件82的长度L、宽度W、以及高度H的大小的对应差异。图2E的视图还示出在部件组件82的第一侧面86以及部件组件82的第二侧面88的经暴露的导电迹线84，其可用于后续电连接以及封装整合，如关于图3A至图3F所讨论。
图2F示出部件组件82的透视图，其中在部件组件的第一侧面86的经暴露的导电迹线84为可见的。图2F还示出部件组件82的长度L、宽度W、以及高度H的相对定位以及取向。
图3A示出临时载体或基板100，载体或基板100包含临时基础材料或牺牲性基础材料，诸如硅、聚合物、不锈钢、或用于结构支撑的其他合适的低成本刚性材料。可选的界面层或双面胶带102可形成于临时载体100上方，作为临时黏接膜或蚀刻停止层。在一个实施方案中，载体100可为包括开放中心部分的环形膜架，其在胶带102的周边支撑胶带。
一个或多个(诸如多个)部件组件82可安装至临时载体100以及界面层102，其中部件组件82的第一侧面86以及经暴露的导电迹线84朝向临时载体100取向，并且导电迹线54呈垂直取向。相应地，部件组件82的第二侧面88以及经暴露的导电迹线84的相对端可取向成远离临时载体100、或面向上，实现在最终半导体部件封装内的后续垂直互连。因此，部件组件82可自保持于未单切基板50上的水平位置垂直，或相对于该水平位置旋转90度。因此，导电迹线54可采取当安装于临时载体100上时的垂直取向，而非当安装于未单切基板50的部分上时所保持的水平取向，其中部件组件82的两个侧面包括经暴露的导电迹线84、经暴露的焊接焊盘58、或两者。
图3B示出图1的嵌入式半导体模片44面向上安装至临时载体100以及界面层102，其中背侧18朝向临时载体100取向，并且有源表面20远离临时载体100取向。半导体模片14可使用取放操作或其他合适的操作放置于临时载体100上方。如图1中所示，黏着剂41可以可选地设置于半导体模片14的背侧18与临时载体100之间。黏着剂41(当存在时)可为热环氧树脂、环氧树脂、B阶段环氧树脂膜、含可选的丙烯酸聚合物的紫外线(UV)B阶段膜、或其他合适的材料。在一个实施方案中，可在半导体模片14安装于临时载体100上方之前将黏着剂41设置于背侧18上方。另选地，黏着剂41可在将嵌入式半导体模片44安装至临时载体100之前设置于临时载体100上方。在其他实施方案中，嵌入式半导体模片41可在不使用黏着剂41的情况下直接安装至界面层或支撑胶带102或临时载体100。
每个嵌入式半导体模片44可安装至临时载体100，每个嵌入式半导体模片44邻近或横向接触对应部件组件82。当安装于临时载体100上方时可通过空间或间隙104使成对的嵌入式半导体模片44以及部件组件82分开，以提供后续形成的半导体部件封装的锯道或离距104。在一些情况下，空间104的一部分可用于后续形成的扇出型互连结构。尽管图3A以及图3B示出部件组件82在嵌入式半导体模片44之前安装至临时载体100，但是在其他情况下，嵌入式半导体模片44可在部件组件82之前首先安装至临时载体100。在安装嵌入式半导体模片44以及部件组件82至临时载体100过程中，部件组件82也可安装、耦接、或附接至嵌入式半导体模片44。为了安装，部件组件82也可被翻转，诸如其中其的第一侧面86朝向临时载体100取向，使得导电迹线54垂直取向，而非水平取向，从而使得导电迹线54可提供穿过最终半导体部件封装142、在重构板材112或半导体部件封装142的前表面116与背表面118之间完全延伸的垂直互连。在另一情况下，可水平安装部件组件以及SMD 70，或在相对于图3B中所示者旋转90度的情况下安装部件组件以及SMD 70，使得导电迹线54与临时载体100平行或实质上平行，诸如在0至10度、0至5度、或0至1度内。
图3C示出利用第二包封物或模制化合物110包封多个部件组件82以及嵌入式半导体模片44或半导体模片14，第二包封物或模制化合物110形成为围绕部件组件82、嵌入式半导体模片44或半导体模片14，并且形成于空间104内，同时经单切的部件组件82、嵌入式半导体模片44、以及半导体模片14安装至临时载体100以形成重构板材或晶圆112。第二包封物110可与第一包封物78、包封物42、或两者类似或相同，并且可使用膏印刷、压缩模制、转移模制、液体包封物模制、层压、真空层压、旋涂、或其他合适的施用器沉积。第二包封物110可为聚合物复合材料，诸如含填料的环氧树脂、含填料的环氧丙烯酸酯、或合适当的填料的聚合物，其可为非导电性并在环境上保护嵌入式半导体模片44以及部件组件82免于外部元素以及污染物的侵害。在一些情况下，重构板材或晶圆112也可于基板内包括至少一个导孔或垂直互连，该至少一个导孔或垂直互连在重构板材112的底部表面116与顶部表面118之间延伸，并且可暴露在重构板材112的底部表面116以及顶部表面118。
重构板材112可经历使用研磨机114的研磨操作，以平坦化重构板材112的前表面116并减小重构板材112的厚度。也可使用化学蚀刻以移除并平坦化重构板材112的一部分。研磨操作可使嵌入式半导体模片44的导电互连件28暴露以及使经暴露的导电迹线84相对于第二包封物110暴露在部件组件82的第一侧面86。重构板材112也可经历使用研磨机114的研磨操作，以平坦化重构板材112的背表面118并减小重构板材112的厚度。研磨操作也可使经暴露的导电迹线84相对于第二包封物110暴露在部件组件82的第二侧面88。
图3D示出第一堆积互连结构120形成于重构板材112的前表面116上方。堆积互连结构120可包括任何所期望数目的导电层以及绝缘层，其取决于最终装置或半导体部件封装142的构型、设计、以及路由需要。关于图3D示出并描述堆积互连结构120的非限制性示例。堆积互连结构120可包括导电层或重分布层(RDL)124，导电层或重分布层124经图案化并沉积于嵌入式半导体模片44(包括导电互连件28)以及部件组件82(包括焊接焊盘58以及经暴露的导电迹线84)上方。在一些情况下，导电层124可直接形成于重构板材112的前表面116上，或接触重构板材112的前表面116。在其他情况下，中间绝缘层或钝化层122可形成于导电层124以及前表面116上或设置于导电层124与前表面116之间。当中间绝缘层或钝化层122存在时，绝缘层122可为通过PVD、CVD、网板印刷、旋涂、喷涂、烧结、或热氧化形成的SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚酰亚胺、BCB、PBO、或具有类似的绝缘以及结构性质的其他材料的一个或多个层。
导电层124可为Al、Cu、Sn、Ni、Au、Ag、Ti/Cu、TiW/Cu、或偶合剂/Cu或其他合适的导电材料的一个或多个层。可使用PVD、CVD、电解电镀、无电解电镀、或其他合适的程序形成导电层124。在一个实施方案中，导电层124为RDL，其包括TiW种层、Cu种层、以及形成于TiW种层以及Cu种层上方的Cu层。为了在完成的半导体部件封装内的点的中传送电信号，导电层124可在导电互连件28、焊接焊盘58、经暴露的导电迹线84、以及完成的半导体部件封装142内的其他特征之间提供电互连。
当诸如为了形成重构板材112在放置以及包封于临时载体100上期间而使嵌入式半导体模片44以及部件组件82的位置从正常位置变动时，嵌入式半导体模片44以及部件组件82的真实或实际位置会未充分对准堆积互连结构120或导电层124的标称设计，以提供给定所期望路由密度以及节距公差的封装互连所期望的可靠性。当嵌入式半导体模片44以及部件组件82的位置变动小时，可不需调整导电层124的位置以适当地对准导电层124与嵌入式半导体模片44以及部件组件82。然而，当嵌入式半导体模片44以及部件组件82在重构板材112内的位置的变化为使得标称位置无法提供适当的与导电层122的对准以及对于导电层122的暴露时，可通过Adaptive PatterningTM或单元特定图案化(下文中，“单元特定图案化”)如2013年5月9日提交的美国专利申请13/891,006中更详细所述进行堆积互连结构120位置的调整，该申请的公开内容以引用方式并入本文。因此，互连结构120以及导电层124的位置、对准、或位置以及对准可通过x-y移动、通过角θ的旋转、通过两者、或通过相对于其的标称位置或相对于重构板材112上的参考点或基准点来调整，从而保持嵌入式半导体模片44与模块封装轮廓之间以及部件组件82与模块封装轮廓之间的恒定对准。
图3D进一步示出绝缘层或钝化层126保形施加于导电层124以及绝缘层122(如果存在)上方并接触导电层124以及绝缘层122。绝缘层126可为使用PVD、CVD、网板印刷、旋涂、喷涂、烧结、热氧化、或其他合适的程序施加的SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚酰亚胺、BCB、PBO、干膜抗蚀层、或具有类似的绝缘以及结构性质的其他材料的一个或多个层。绝缘层126可经图案化，并且可通过蚀刻、雷射钻孔、机械钻孔、或其他合适的程序移除绝缘层126的一部分，以形成完全穿过绝缘层126的开口以暴露导电层124。绝缘层126中的开口可用于接收凸块、球、或互连结构128。
可通过使用蒸镀、电解电镀、无电解电镀、球滴、或网板印刷程序沉积导电凸块材料于导电层124的部分(其可形成为凸块下金属化(UBM)垫)上方来形成凸块128。凸块材料可为Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、以及它们的组合连同可选的助焊剂溶液。例如、凸块材料可为共熔Sn/Pb、高铅焊料、或无铅焊料。可使用合适的附接或接合程序，将凸块材料接合至导电层124。在一个实施方案中，可通过将凸块材料加热至高于其熔点来使凸块材料回焊，以形成凸块128。在一些应用中，凸块128被第二次回焊以改良至导电层124的电接触。凸块128也可被压缩接合或热压接合至导电层124。凸块128表示可形成于导电层124上方的一种类型互连结构。凸块128也可包括柱形凸块、微凸块、或其他电互连。
图3E示出重构板材112，其中第一堆积互连结构120形成于重构板材112上，并且从临时载体100移除重构板材112，在此之后临时载体可以可选地经历研磨操作(该研磨操作与图3C的研磨操作类似，但是在背表面118而不是在前表面116)以平坦化背表面118，以减少重构板材112的厚度，并且使经暴露的导电迹线84相对于第二包封物110或背表面118暴露在部件组件82的第二侧面88。因此，在各种实施方案中，经暴露的导电迹线84(如导电迹线54以及焊接焊盘58)可暴露在仅第一侧面86、仅暴露在第二侧面88，或可暴露在第一侧面86以及第二侧面88两者。在一些情况下，经暴露的导电迹线84相对于第二包封物110暴露，然而在其他情况下，经暴露的导电迹线84相对于第一侧面86、第二侧面88、或两者暴露。
在经暴露的导电迹线84暴露在部件组件82的第二侧面88的情况下，第二堆积互连结构130可形成于重构板材112的背表面118上方。堆积互连结构130可包括任何所期望数目的导电层以及绝缘层，其取决于最终装置或半导体部件封装142的构型、设计、以及路由需要。关于图3E示出并描述堆积互连结构130的非限制性示例。堆积互连结构130可包括导电层或重分布层(RDL)134，导电层或重分布层134经图案化并沉积于嵌入式半导体模片44上方以及部件组件82(包括焊接焊盘58以及经暴露的导电迹线84)上方。在一些情况下，导电层134可直接形成于重构板材112的背表面118上或接触重构板材112的背表面118。在其他情况下，中间绝缘层或钝化层132可形成于导电层134以及背表面118上或设置于导电层134与背表面118之间。当中间绝缘层或钝化层132存在时，绝缘层132可为通过PVD、CVD、网板印刷、旋涂、喷涂、烧结、或热氧化形成的SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚酰亚胺、BCB、PBO、或具有类似的绝缘以及结构性质的其他材料的一个或多个层。
导电层134可为Al、Cu、Sn、Ni、Au、Ag、Ti/Cu、TiW/Cu、或偶合剂/Cu或其他合适的导电材料的一个或多个层。可使用PVD、CVD、电解电镀、无电解电镀、或其他合适的程序形成导电层134。在一个实施方案中，导电层134为RDL或扇出型RDL，其包括TiW种层、Cu种层、以及形成于TiW种层以及Cu种层上方的Cu层。为了在完成的半导体部件封装内的点的中传送电信号，导电层134可提供焊接焊盘58、经暴露的导电迹线84、以及完成的半导体部件封装142内的其他特征之间的电互连。
当诸如为了形成重构板材112在放置以及包封于临时载体100上期间而使嵌入式半导体模片44以及部件组件82的位置自正常位置变动时，嵌入式半导体模片44以及部件组件82的真实或实际位置会未充分对准堆积互连结构130或导电层134的标称设计，以提供给定所期望路由密度以及节距公差的封装互连所期望的可靠性。当嵌入式半导体模片44以及部件组件82的位置变动小时，可不需调整导电层134的位置以适当地对准导电层134与嵌入式半导体模片44以及部件组件82。然而，当嵌入式半导体模片44以及部件组件82在重构板材112内的位置的变化为使得标称位置无法提供适当的与导电层132的对准以及对于导电层132的暴露时，可通过单元特定图案化进行堆积互连结构130位置的调整。因此，互连结构130以及导电层134的位置、对准、或位置以及对准可通过x-y移动、通过角θ的旋转、通过两者、或通过相对于其的标称位置或相对于重构板材112上的参考点或基准点来调整，从而保持嵌入式半导体模片44与模块封装轮廓之间以及部件组件82与模块封装轮廓之间的恒定对准。
图3E进一步示出绝缘层或钝化层136保形施加于导电层134以及绝缘层132(如果存在)上方并接触导电层134以及绝缘层132。绝缘层136可为使用PVD、CVD、网板印刷、旋涂、喷涂、烧结、热氧化、或其他合适的程序施加的SiO2、Si3N4、SiON、Ta2O5、Al2O3、聚酰亚胺、BCB、PBO、干膜抗蚀层、或具有类似的绝缘以及结构性质的其他材料的一个或多个层。绝缘层136可经图案化，并且可通过蚀刻、雷射钻孔、机械钻孔、或其他合适的程序移除绝缘层136的一部分，以形成完全穿过绝缘层136的开口138以暴露导电层134。绝缘层136中的开口138可暴露导电层134的部分(其呈堆栈式封装(POP)焊接焊盘或SMD焊接焊盘139形成于第二堆积互连结构130的顶部路由层上)，用于接收凸块、球、或互连结构128以及其他装置、封装、SMD、表面安装装置(SMD)、表面安装组件(例如经封装的IC、无源部件、连接器、机械零件、EMI屏蔽)、或至基板或其他装置的安装。
在形成第一堆积互连结构120以及第二堆积互连结构130之后，重构板材以及第一堆积互连120以及第二堆积互连130可使用锯刃或雷射切割工具140单切成单个半导体部件封装142。
图3F示出图3E的半导体封装142的放大图。如所示，重构板材或晶圆112可包括约0.43mm的高度H1，并且包括第一堆积互连结构120以及第二堆积互连结构130的高度的总体封装高度H2可为0.5mm、或约0.5mm，诸如0.3mm至0.7mm。第一堆积互连结构120以及第二堆积互连结构130可耦接至贯穿模型的导电迹线54以及SMD 70的焊接焊盘58，并且直接电连通贯穿模具的导电迹线54以及SMD 70的焊接焊盘58，从而提供封装142的底部表面144与封装142的顶部表面146之间的垂直电互连。在一些情况下，部件组件82可被锯成略微大于成品高度或厚度H1，使得在顶部以及底部研磨步骤中可使垂直贯穿模具的导电迹线54暴露，诸如利用如图3C中所示的研磨机114在研磨前表面116以及在形成第二堆积互连结构130的前研磨背表面118期间，如图3E中所示。
半导体封装142的改良的整合以及减小的大小，包括具有焊料或Sn连接74的部件组件82的内含，特别适合小型电子系统(诸如智能型表)以及需要减小的形状因数或可能最小形状因数的其他IoT装置。将可焊接组件82嵌入3D扇出型晶圆级封装或半导体部件封装142的核心内的方法可包括：使用焊料回焊附接无源部件或有源部件70至基板或PCB条50；包覆模制该条以包封组件70；切分该条以形成离散模制组件82；以及将至少一个模制部件组件82放置于临时载体100上，使得部件组件82内的导电迹线54经垂直取向，并且第一侧表面86朝向载体100取向并附接至载体100。
该方法还可包括：将具有导电互连件28或镀Cu凸块的至少半导体模片14放置于临时载带102上，半导体模片14邻近部件组件或模制无源件82；包封临时载体100以形成重构板材或晶圆112；研磨重构板材112以暴露半导体模片14上的导电互连件或Cu凸块28以及模制组件82内的导电迹线54(导电迹线54中的至少2条电连接至SMD、无源部件、或有源部件70)而不暴露嵌入部件组件或模制组件82内的焊料74；以及在重构板材112上形成第一堆积互连结构或重分布层120，以电连接半导体模片14上的至少一个接触焊盘22至SMD或嵌入式无源部件70上的至少一个端子72。可选地，第二堆积互连结构或重分布层130可形成于重构板材112的相对的第二表面或侧面118，接触部件组件或离散模制组件82内的导电迹线54中的至少一者，使得产生穿过半导体部件封装142的高度H1或厚度至半导体模片14上的接触焊盘或接合焊盘22的电连接。
如图3F中所示，半导体部件封装142可包括一个或多个半导体模片14以及SMD技术70，SMD技术70可包括其他半导体模片、IC、无源装置、晶圆级芯片尺度封装(WLCSP)以及其他组件，SMD技术70安装至嵌入式半导体模片44并包括于半导体部件封装142内，而不是使SMD 70安装至熟知基板或PCB并从还安装至熟知基板或PCB的半导体模片14或嵌入式半导体模片44偏离。
因此，半导体部件封装142可提供许多优点，包括：整合并使用标准的低成本的具有Sn终端的0201无源件；为了易于安装至界面层或载带材料102，SMD 70包括平的第一侧表面86；导电迹线54穿过半导体部件封装142的高度H1用作或操作成3D或垂直互连结构，实现PoP构型；0201无源件整合成在0.5mm主体厚度内；兼容于全模制晶圆级扇出型半导体封装设计(包括Deca M-SeriesTM封装)；以及外部部件组件不需要附加内部程序或设备且还不需要附加循环时间。
在半导体部件封装142的一些变化中，部件组件82的长度L可延伸并包括更多SMD或无源件70以及更多贯穿模具的导电迹线54。在一些情况下，基板50可形成为多层基板以添加附加贯穿模具的导电迹线54。在其他情况下，SMD或无源件70可安装于基板50的相对的第一表面56以及第二相对表面60或基板核心52上方。当SMD 70安装于基板50的相对表面上方时，可模制或包封具有SMD 70的基板50的一个或两个侧面。在其他情况下，小的有源Si半导体模片可并入具有SMD 70的基板50上。此外，在当SMD 70包括于包括单侧(2D)封装结构的半导体部件封装142内时的情况下，可在无第二堆积互连结构或RDL 130的情况下形成2D封装结构，使得部件组件82可在水平取向的情况下安装至界面层或板材载带102，并且基板或引线架50可面向上，使得在板材研磨程序或前研磨程序期间暴露POP或SMD焊接焊盘139，如图3C中所示。
虽然本公开包括不同形式的多个实施方案，但是在说明书附图以及以下撰写的说明书中呈现具体实施方案的细节，且了解本公开视为所公开的方法以及系统的范例以及原理，并且非意图使所公开的概念的广泛方面限于所阐释的实施方案。此外，本领域技术人员应了解，其他结构、制造装置以及示例可与所提供的装置以及示例互混或取代所提供的装置以及示例。在上文描述参考特定实施方案的处，应显而易见，可进行多种修改而不会脱离其实质，并且显而易见，这些实施方案以及实施方案也可应用于其他技术。因此，所公开的目标物意图含括所有此类变更、修改以及变化，彼等皆落入本公开的实质以及范围以及本领域技术人员的知识内。因此，显而易见的是，可在不脱离如随附权利要求书中所阐述的本发明的较宽实质以及范围的情况下对其做出各种修改以及改变。因此，应以说明性意义而非限制性意义来看待说明书以及说明书附图。

Claims (20)

1.一种制备半导体部件封装的方法，包括：
提供包括导电迹线的基板；
利用焊料将多个表面安装装置(SMD)焊接至所述基板；
利用第一模制化合物在所述多个SMD上方并围绕所述多个SMD包封所述基板上的所述多个SMD；
通过分开所述基板来单切所述多个SMD，以暴露所述导电迹线并且形成多个部件组件，所述多个部件组件在所述部件组件的第一侧面和所述部件组件的第二侧面处包括暴露的导电迹线，所述部件组件的所述第二侧面与所述部件组件的所述第一侧面相对；
提供临时载体；
将所述部件组件中的至少一者安装至所述临时载体，其中所述至少一个部件组件的所述第一侧面和所述暴露的导电迹线朝向所述临时载体取向；
将包括导电互连件的半导体模片邻近所述部件组件中的所述至少一者安装至所述临时载体；
在所述至少一个经单切的部件组件和所述半导体模片安装至所述临时载体时，利用第二模制化合物包封所述部件组件中的所述至少一者和所述半导体模片以形成重构板材；
使所述导电互连件和所述暴露的导电迹线相对于所述第二模制化合物暴露在所述至少一个部件组件的所述第一侧面或所述第二侧面处；
在所述第二模制化合物上方形成第一重分布层，以将所述导电互连件和所述暴露的导电迹线电连接；以及
单切所述重构板材。
2.根据权利要求1所述的方法，其中所述基板包括两层层压层、印刷电路板(PCB)、或坯料模制化合物板材。
3.根据权利要求1所述的方法，其中所述部件组件包括无源装置。
4.根据权利要求1所述的方法，其中所述半导体模片为嵌入式半导体模片，所述嵌入式半导体模片包括耦接至所述半导体模片并相对于所述第二模制化合物暴露的所述导电互连件。
5.根据权利要求1所述的方法，其中所述导电互连件包括铜凸块或支柱。
6.根据权利要求1所述的方法，其中将所述单切的部件组件中的所述至少一者耦接至所述基板的所述焊料包含在所述半导体部件封装内并且相对于所述半导体部件封装不暴露。
7.一种制备半导体部件封装的方法，包括：
提供包括导电迹线的基板；
利用焊料将表面安装装置(SMD)附接至所述基板以形成部件组件；
将所述部件组件安装至临时载体，其中所述部件组件的第一侧面朝向所述临时载体取向；
将包括导电互连件的半导体模片邻近所述部件组件安装至所述临时载体；
在所述部件组件和所述半导体模片安装至所述临时载体时，利用模制化合物包封所述部件组件和所述半导体模片以形成重构板材；以及
使所述导电互连件和所述导电迹线相对于所述模制化合物暴露在所述部件组件的所述第一侧面或第二侧面处。
8.根据权利要求7所述的方法，其中所述基板包括两层层压层、印刷电路板(PCB)、或坯料模制化合物板材。
9.根据权利要求7所述的方法，还包括在将所述部件组件安装至所述临时载体之前，利用附加模制化合物在所述SMD上方并围绕所述SMD包封所述基板上的所述SMD。
10.根据权利要求7所述的方法，其中所述半导体模片为嵌入式半导体模片，所述嵌入式半导体模片包括耦接至所述半导体模片并相对于所述模制化合物暴露的所述导电互连件，其中所述导电互连件包括铜凸块或支柱。
11.根据权利要求7所述的方法，其中将所述部件组件耦接至所述基板的所述焊料包含在所述部件组件内并且相对于所述部件组件不暴露。
12.根据权利要求7所述的方法，其中暴露所述导电互连件和所述导电迹线进一步包括从所述重构板材移除所述临时载体并研磨所述重构板材。
13.根据权利要求7所述的方法，还包括：
在所述重构板材上方形成第一重分布层，以将所述导电互连件和所述导电迹线电连接；以及
形成与所述第一重分布层相对的第二重分布层，以与所述暴露的导电迹线电连接以穿过所述半导体部件封装的厚度形成电连接。
14.一种制备半导体部件封装的方法，包括：
提供包括导电迹线的基板；
利用焊料将表面安装装置(SMD)附接至所述基板；
将所述SMD和所述基板安装至临时载体；
邻近所述SMD安装包括导电互连件的半导体模片；
在所述临时载体上方分配模制化合物；以及
使所述导电互连件和所述导电迹线相对于所述模制化合物且在所述模制化合物的同一表面处暴露。
15.根据权利要求14所述的方法，还包括邻近所述临时载体安装包括所述导电互连件的所述半导体模片。
16.根据权利要求14所述的方法，还包括邻近所述SMD安装包括所述导电互连件的所述半导体模片。
17.根据权利要求14所述的方法，还包括分配模制化合物以包封所述SMD和所述半导体模片，从而形成重构板材。
18.根据权利要求14所述的方法，还包括：
单切所述基板以使所述导电迹线暴露在所述基板的第一侧面处；以及
将所述SMD和所述基板安装至所述临时载体，其中所述基板的所述第一侧面和所述暴露的导电迹线朝向所述临时载体取向。
19.根据权利要求14所述的方法，其中所述基板包括两层层压层、印刷电路板(PCB)、或坯料模制化合物板材。
20.根据权利要求14所述的方法，其中所述导电互连件包括铜凸块或支柱。
CN201680003401.XA 2015-04-29 2016-04-29 制备用于全模制封装的3d互连部件的方法 Active CN107078133B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201562154218P 2015-04-29 2015-04-29
US62/154,218 2015-04-29
US15/141,028 US9502397B1 (en) 2015-04-29 2016-04-28 3D interconnect component for fully molded packages
US15/141,028 2016-04-28
PCT/US2016/030117 WO2016176576A1 (en) 2015-04-29 2016-04-29 3d interconnect component for fully molded packages

Publications (2)

Publication Number Publication Date
CN107078133A CN107078133A (zh) 2017-08-18
CN107078133B true CN107078133B (zh) 2021-10-15

Family

ID=57199394

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201680003401.XA Active CN107078133B (zh) 2015-04-29 2016-04-29 制备用于全模制封装的3d互连部件的方法

Country Status (4)

Country Link
US (1) US9502397B1 (zh)
KR (1) KR102447319B1 (zh)
CN (1) CN107078133B (zh)
WO (1) WO2016176576A1 (zh)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9196509B2 (en) * 2010-02-16 2015-11-24 Deca Technologies Inc Semiconductor device and method of adaptive patterning for panelized packaging
KR101411813B1 (ko) * 2012-11-09 2014-06-27 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
CN110767864A (zh) * 2013-03-15 2020-02-07 赛尔格有限责任公司 用于锂离子二次电池的多层混杂型电池隔板及其制造方法
US9541330B2 (en) 2013-07-17 2017-01-10 Whirlpool Corporation Method for drying articles
US9410282B2 (en) 2013-10-02 2016-08-09 Whirlpool Corporation Method and apparatus for drying articles
US9645182B2 (en) * 2013-10-16 2017-05-09 Whirlpool Corporation Method and apparatus for detecting an energized E-field
US9605899B2 (en) 2015-03-23 2017-03-28 Whirlpool Corporation Apparatus for drying articles
US11272618B2 (en) 2016-04-26 2022-03-08 Analog Devices International Unlimited Company Mechanically-compliant and electrically and thermally conductive leadframes for component-on-package circuits
JP2017212356A (ja) * 2016-05-26 2017-11-30 京セラ株式会社 積層型基板およびその製造方法
US10573601B2 (en) 2016-09-19 2020-02-25 Deca Technologies Inc. Semiconductor device and method of unit specific progressive alignment
US10157803B2 (en) 2016-09-19 2018-12-18 Deca Technologies Inc. Semiconductor device and method of unit specific progressive alignment
US10529671B2 (en) * 2016-12-13 2020-01-07 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
TWI656612B (zh) * 2017-03-16 2019-04-11 佳邦科技股份有限公司 半導體封裝件
US10290532B2 (en) * 2017-05-19 2019-05-14 Analog Devices Global Forming an isolation barrier in an isolator
EP3639634A4 (en) * 2017-06-15 2021-07-14 Jabil Inc. SYSTEM, DEVICE AND METHOD FOR USING SURFACE MOUNTING TECHNOLOGY ON METAL SUBSTRATES
US11075132B2 (en) * 2017-08-29 2021-07-27 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package, package-on-package structure, and manufacturing method thereof
US10497635B2 (en) 2018-03-27 2019-12-03 Linear Technology Holding Llc Stacked circuit package with molded base having laser drilled openings for upper package
US10622073B2 (en) * 2018-05-11 2020-04-14 Texas Instruments Incorporated Integrated circuit including vertical capacitors
US11626343B2 (en) * 2018-10-30 2023-04-11 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with enhanced thermal dissipation and method for making the same
US11410977B2 (en) 2018-11-13 2022-08-09 Analog Devices International Unlimited Company Electronic module for high power applications
CN111200702B (zh) * 2018-11-20 2022-03-15 中芯集成电路（宁波）有限公司 摄像组件及其封装方法、镜头模组、电子设备
US11139249B2 (en) * 2019-04-01 2021-10-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of forming the same
DE102019119371A1 (de) * 2019-07-17 2021-01-21 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Bauteil und verfahren zur herstellung eines bauteils
US11676922B2 (en) * 2019-10-28 2023-06-13 Qualcomm Incorporated Integrated device comprising interconnect structures having an inner interconnect, a dielectric layer and a conductive layer
CN112786435A (zh) * 2019-11-07 2021-05-11 长鑫存储技术有限公司 半导体结构及其制备方法
US11844178B2 (en) 2020-06-02 2023-12-12 Analog Devices International Unlimited Company Electronic component
KR102680894B1 (ko) * 2021-08-18 2024-07-04 한국성전(주) 입체가공형 터치패드 및 그 형성방법
TWI822387B (zh) * 2022-10-11 2023-11-11 廖富江 半導體元件、半導體封裝件及其製造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6546620B1 (en) * 2000-06-29 2003-04-15 Amkor Technology, Inc. Flip chip integrated circuit and passive chip component package fabrication method
CN102099911A (zh) * 2008-07-17 2011-06-15 飞兆半导体公司 使用预模制载体的嵌入式裸片封装及工艺流程
CN103715104A (zh) * 2012-09-28 2014-04-09 新科金朋有限公司 在半导体管芯上形成支撑层的半导体器件和方法
CN104011851A (zh) * 2011-12-22 2014-08-27 英特尔公司 具有窗口插入器的3d集成电路封装

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6770971B2 (en) * 2002-06-14 2004-08-03 Casio Computer Co., Ltd. Semiconductor device and method of fabricating the same
JPWO2007069606A1 (ja) * 2005-12-14 2009-05-21 新光電気工業株式会社 チップ内蔵基板の製造方法
TW200802634A (en) * 2006-06-02 2008-01-01 Siliconware Precision Industries Co Ltd Semiconductor package and method for fabricating the same
US8143719B2 (en) * 2007-06-07 2012-03-27 United Test And Assembly Center Ltd. Vented die and package
KR101501739B1 (ko) * 2008-03-21 2015-03-11 삼성전자주식회사 반도체 패키지 제조 방법
US8487435B2 (en) * 2008-09-09 2013-07-16 Triquint Semiconductor, Inc. Sheet-molded chip-scale package
US9082806B2 (en) * 2008-12-12 2015-07-14 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US20110156239A1 (en) * 2009-12-29 2011-06-30 Stmicroelectronics Asia Pacific Pte Ltd. Method for manufacturing a fan-out embedded panel level package
US9177926B2 (en) * 2011-12-30 2015-11-03 Deca Technologies Inc Semiconductor device and method comprising thickened redistribution layers
US9196509B2 (en) * 2010-02-16 2015-11-24 Deca Technologies Inc Semiconductor device and method of adaptive patterning for panelized packaging
US9576919B2 (en) * 2011-12-30 2017-02-21 Deca Technologies Inc. Semiconductor device and method comprising redistribution layers
US9735113B2 (en) * 2010-05-24 2017-08-15 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming ultra thin multi-die face-to-face WLCSP
US9385009B2 (en) * 2011-09-23 2016-07-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming stacked vias within interconnect structure for Fo-WLCSP
WO2013102146A1 (en) * 2011-12-30 2013-07-04 Deca Technologies, Inc. Die up fully molded fan-out wafer level packaging
US10049964B2 (en) * 2012-03-23 2018-08-14 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units
US9385006B2 (en) * 2012-06-21 2016-07-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming an embedded SOP fan-out package
US9721920B2 (en) * 2012-10-19 2017-08-01 Infineon Technologies Ag Embedded chip packages and methods for manufacturing an embedded chip package
US9704780B2 (en) * 2012-12-11 2017-07-11 STATS ChipPAC, Pte. Ltd. Semiconductor device and method of forming low profile fan-out package with vertical interconnection units
US9287204B2 (en) * 2012-12-20 2016-03-15 Stats Chippac, Ltd. Semiconductor device and method of bonding semiconductor die to substrate in reconstituted wafer form
US9269622B2 (en) * 2013-05-09 2016-02-23 Deca Technologies Inc. Semiconductor device and method of land grid array packaging with bussing lines
US9111870B2 (en) * 2013-10-17 2015-08-18 Freescale Semiconductor Inc. Microelectronic packages containing stacked microelectronic devices and methods for the fabrication thereof
US20150279824A1 (en) * 2014-03-28 2015-10-01 Vijay K. Nair Electronic package and method of forming an electronic package
US9040316B1 (en) * 2014-06-12 2015-05-26 Deca Technologies Inc. Semiconductor device and method of adaptive patterning for panelized packaging with dynamic via clipping
US9281284B2 (en) * 2014-06-20 2016-03-08 Freescale Semiconductor Inc. System-in-packages having vertically-interconnected leaded components and methods for the fabrication thereof
US9595485B2 (en) * 2014-06-26 2017-03-14 Nxp Usa, Inc. Microelectronic packages having embedded sidewall substrates and methods for the producing thereof
US9396999B2 (en) * 2014-07-01 2016-07-19 Freescale Semiconductor, Inc. Wafer level packaging method
KR102081684B1 (ko) * 2014-08-26 2020-04-28 데카 테크놀로지 잉크 고유 식별자를 포함하는 패키지에 대한 프론트사이드 패키지 레벨 직렬화
US9826630B2 (en) * 2014-09-04 2017-11-21 Nxp Usa, Inc. Fan-out wafer level packages having preformed embedded ground plane connections and methods for the fabrication thereof
US20160086930A1 (en) * 2014-09-24 2016-03-24 Freescale Semiconductor, Inc. Fan-out wafer level package containing back-to-back embedded microelectronic components and assembly method therefor
US10354958B2 (en) * 2014-10-01 2019-07-16 Nxp Usa, Inc. Through package circuit in fan-out wafer level package
US9941207B2 (en) * 2014-10-24 2018-04-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of fabricating 3D package with short cycle time and high yield

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6546620B1 (en) * 2000-06-29 2003-04-15 Amkor Technology, Inc. Flip chip integrated circuit and passive chip component package fabrication method
CN102099911A (zh) * 2008-07-17 2011-06-15 飞兆半导体公司 使用预模制载体的嵌入式裸片封装及工艺流程
CN104011851A (zh) * 2011-12-22 2014-08-27 英特尔公司 具有窗口插入器的3d集成电路封装
CN103715104A (zh) * 2012-09-28 2014-04-09 新科金朋有限公司 在半导体管芯上形成支撑层的半导体器件和方法

Also Published As

Publication number Publication date
KR20170141645A (ko) 2017-12-26
CN107078133A (zh) 2017-08-18
WO2016176576A1 (en) 2016-11-03
US20160322343A1 (en) 2016-11-03
US9502397B1 (en) 2016-11-22
KR102447319B1 (ko) 2022-09-23

Similar Documents

Publication Publication Date Title
CN107078133B (zh) 制备用于全模制封装的3d互连部件的方法
US10373902B2 (en) Fully molded miniaturized semiconductor module
KR101803612B1 (ko) 3ｄ 패키지 구조 및 그 형성 방법
KR101957851B1 (ko) 동적 비아 클리핑에 의한 패널식 패키징을 위한 적응적 패터닝 방법 및 반도체 디바이스
CN108666214B (zh) 半导体器件以及用于形成低廓形嵌入式晶圆级球栅阵列模塑激光封装的方法
US9269622B2 (en) Semiconductor device and method of land grid array packaging with bussing lines
US8592992B2 (en) Semiconductor device and method of forming vertical interconnect structure with conductive micro via array for 3-D Fo-WLCSP
TWI602262B (zh) 形成穿過互連結構和ｗｌｃｓｐ的封膠的導電通孔之半導體裝置及方法
US9082780B2 (en) Semiconductor device and method of forming a robust fan-out package including vertical interconnects and mechanical support layer
CN108257877B (zh) 形成扇出封装体叠层器件的半导体方法和器件
KR102164012B1 (ko) 전체 성형 주변 패키지 온 패키지 디바이스
CN108307661B (zh) 全模制的微型化半导体模块
US10672624B2 (en) Method of making fully molded peripheral package on package device
KR20180051611A (ko) 열적으로 강화된 전체 성형 팬-아웃 모듈
US9230896B2 (en) Semiconductor device and method of reflow soldering for conductive column structure in flip chip package
TW201327744A (zh) 半導體裝置和形成具有扇出互連結構以減少基板複雜性之擴大的半導體裝置之方法
TWI690044B (zh) 全模製封裝之３ｄ互連組件
KR102164011B1 (ko) 전체 성형 주변 패키지 온 패키지 디바이스
CN115565937A (zh) 具有穿硅通孔（tsv）垂直互连的可堆叠全模制半导体结构

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
REG Reference to a national code

Ref country code: HK

Ref legal event code: DE

Ref document number: 1243223

Country of ref document: HK

CB02 Change of applicant information

Address after: Arizona, USA

Applicant after: Decca Technology Inc.

Address before: Arizona, USA

Applicant before: DECA TECHNOLOGIES Inc.

CB02 Change of applicant information
GR01 Patent grant
GR01 Patent grant