CN108281358A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN108281358A
CN108281358A CN201810170561.4A CN201810170561A CN108281358A CN 108281358 A CN108281358 A CN 108281358A CN 201810170561 A CN201810170561 A CN 201810170561A CN 108281358 A CN108281358 A CN 108281358A
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李凡
张海洋
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Semiconductor Manufacturing International Shanghai Corp
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Abstract

公开了一种半导体器件及其制造方法。该方法包括：在衬底上形成栅极绝缘层和栅极；在所述栅极两侧分别形成间隔件；以所述栅极和所述间隔件为掩模来刻蚀所述衬底以形成凹槽；在所述间隔件两侧分别形成伪侧墙；以所述栅极、所述间隔件和所述伪侧墙为掩模来刻蚀所述衬底以形成凹部，所述凹部具有比所述凹槽更深的深度；去除所述伪侧墙；以及在所述凹槽和所述凹部中填充SiGe，从而形成所述半导体器件的源漏扩展区和源极/漏极区；其中，在所述填充SiGe的步骤之前，还包括对所述衬底进行加热以使得所述衬底的材料回流从而至少改变所述凹槽的接近栅极一侧的侧壁的形状的步骤。

Description

半导体器件及其制造方法
本申请是于2011年5月12日提交的、申请号为201110121643.8、发明名称为“半导体器件及其制造方法”的申请之分案申请。
技术领域
本发明涉及半导体器件及其制造方法，具体来说，涉及具有嵌入式硅锗(SiGe)的源极/漏极结构的半导体器件及其制造方法。
背景技术
提高沟道区的载流子迁移率能够增大场效应晶体管的驱动电流，提高器件的性能。而提高载流子迁移率的一种有效机制是在沟道中产生应力。尽管已经提出了各种沟道应力技术，但是对于pMOSFET而言，嵌入式SiGe技术能最有效地提升应力。嵌入式SiGe技术已经被广泛地用在现代CMOS技术中，以用于提高pMOSFET的性能。
N.Yasutake等人的论文“A High Performance pMOSFET with Two-stepRecessed SiGe-S/D Structure for 32nm node and Beyond”(Solid-State DeviceResearch Conference,2006,Proceeding of the 36th European,IEEE,pp.77～80)中公开了一种两级凹进式SiGe的源极/漏极结构，其极大地改善了pMOSFET中的短沟道效应和源极/漏极电阻问题，并且实现了多于80％的电流增大。从该论文中可知，SiGe与沟道的接近程度对于增大沟道应变和实现高性能pMOSFET而言是主导参数，并且对于减小源漏扩展区(SDE)电阻而言也是关键参数。然而，对于现有的两级凹进式SiGe的源极/漏极结构，如图1所示，从栅极101的边缘到SiGe顶端的距离由偏移间隔件102的宽度限定，这限制了SiGe与沟道的接近程度。
鉴于上述问题，期望提出一种半导体器件制造方法以使得作为源极/漏极结构的SiGe与栅极边缘尽可能地接近，从而实现更高性能的半导体器件。
发明内容
本发明的一个目的是提高作为源极/漏极结构的SiGe与栅极边缘的接近程度，从而提高半导体器件的性能。
根据本发明的第一方面，提供了一种制造半导体器件的方法，包括：在衬底上形成栅极绝缘层和栅极；在该栅极两侧分别形成间隔件；以该栅极和该间隔件为掩模来刻蚀该衬底以形成凹槽；在该间隔件两侧分别形成伪侧墙；以该栅极、该间隔件和该伪侧墙为掩模来刻蚀该衬底以形成凹部，该凹部具有比该凹槽更深的深度；去除该伪侧墙；以及在该凹槽和该凹部中填充SiGe，从而形成该半导体器件的源漏扩展区和源极/漏极区；其中，在该填充SiGe的步骤之前，还包括对该衬底进行加热以使得该衬底的材料回流从而至少改变该凹槽的接近栅极一侧的侧壁的形状的步骤。
优选地，对该衬底进行加热的步骤是在形成凹槽的步骤之后并且在形成伪侧墙的步骤之前进行的。
优选地，对该衬底进行加热的步骤是在去除伪侧墙的步骤之后进行的。
优选地，对该衬底进行加热的步骤是在氢气氛中进行的。
优选地，对该衬底进行加热的温度在750℃到850℃的范围内，加热的时间为30秒到5分钟。
优选地，该填充SiGe的步骤包括外延生长SiGe的步骤。
优选地，在外延生长SiGe的同时对SiGe进行原位掺杂。
优选地，在该形成栅极的步骤之后且在该形成间隔件的步骤之前，对该衬底进行晕圈注入。
优选地，在该填充SiGe的步骤之后，进行低温尖峰式快速热退火。
优选地，刻蚀该衬底的步骤均使用干法刻蚀工艺。
优选地，该衬底为硅衬底。
优选地，该形成栅极绝缘层和栅极的步骤包括通过热氧化工艺形成二氧化硅层以作为栅极绝缘层。
优选地，通过上述方法制造的半导体器件是pMOSFET。
优选地，在对该衬底进行加热的步骤之后，该凹槽的接近栅极一侧的开口边缘与该栅极的侧壁对齐。
根据本发明的第二方面，提供了一种半导体器件，包括：在衬底上的栅极绝缘层和栅极；在该栅极两侧的间隔件；在该衬底中的由SiGe形成的一体化的源极扩展区和源极区以及由SiGe形成的一体化的漏极扩展区和漏极区；该源极扩展区和该漏极扩展区的接近栅极一侧的边缘上端位于该间隔件下方。
优选地，该半导体器件是pMOSFET。
优选地，该衬底为硅衬底。
优选地，该栅极绝缘层是二氧化硅层。
优选地，该源极扩展区和该漏极扩展区的接近栅极一侧的边缘上端分别与该栅极的对应一侧的侧壁对齐。
本发明的一个优点在于，两级凹进式SiGe能够使半导体器件的尺寸进一步按比例缩小。通过优化结构还能够极大地改善短沟道效应。
本发明的另一个优点在于，与现有技术相比，使得作为源极/漏极结构的SiGe能够更接近沟道，从而提升沟道中的应力，提高半导体器件的性能。
本发明的另一个优点在于，通过加热使衬底材料回流的工艺具有很好的工艺兼容性并且成本较低。而且，无需使用复杂的刻蚀工艺就能实现SiGe与栅极边缘的极端接近。因此，半导体器件的性能得到了显著的提高。
通过以下参照附图对本发明的示例性实施例的详细描述，本发明的其它特征及其优点将会变得更为清楚。
附图说明
参照附图，根据下面的详细描述，可以更加清楚地理解本发明。为了清楚起见，图中各个层的相对厚度以及特定区域的相对尺寸并没有按比例绘制。在附图中：
图1是现有技术中的具有两级凹进式SiGe的源极/漏极结构的半导体器件的示意图；以及
图2A－2G是根据本发明实施例的半导体器件在其制造过程中的各个阶段处的示意性截面图。
具体实施方式
现在将参照附图来详细描述本发明的各种示例性实施例。
发明人注意到，在特定气氛(例如，氢气氛)下，在远低于熔点的温度下会发生硅原子的表面迁移。为了使总表面能最小化，硅原子的迁移不仅改善了表面粗糙度，而且改变了硅结构的形状，例如产生圆角。这种效果类似于玻璃或聚合物的回流工艺，即，也可以称为硅的回流。但是与玻璃或聚合物的回流工艺不同，这种机制仅仅依赖于表面原子的移动，而保持晶体结构。具体分析可参见Ming-Chang M.Lee等人的论文“Thermal Annealing inHydrogen for 3-D Profile Transformation on Silicon-on-Insulator and SidewallRoughness Reduction”(J.Microelectromech.Syst.,vol.15,no.2,pp.338-343,2006年4月)，其全部内容通过引用而被并入于此。
基于上述原理，提出了本发明。
以下对示例性实施例的描述仅仅是说明性的，决不作为对本发明及其应用或使用的任何限制。本领域中公知的技术可以被应用于没有特别示出或描述的部分。
(第一实施例)
在本实施例中，提出了一种具有两级凹进式SiGe的源极/漏极结构的半导体器件及其制造方法，其中在第一次刻蚀衬底之后，对硅衬底进行加热，使得发生硅的回流，至少改变凹槽的接近栅极一侧的侧壁的形状，从而使凹槽的前端更接近栅极边缘、甚至与栅极边缘对齐。下面将更详细地描述该制造方法。
首先，如图2A所示，在衬底201上形成栅极绝缘层202和栅极203，并且在栅极203两侧分别形成有间隔件204。间隔件204的厚度可以为5nm到10nm。间隔件204可以是例如硅氮化物、硅氧化物等材料。可以利用例如化学气相沉积(CVD)的方法来沉积间隔件204的材料。可选地，在形成栅极203之后并且在形成间隔件204之前，对衬底进行晕圈(halo)离子注入，这有助于控制短沟道效应。
接下来，如图2B所示，以栅极203和间隔件204为掩模来刻蚀衬底201以形成凹槽206。刻蚀衬底的方法可以包括例如反应离子刻蚀(RIE)等的干法刻蚀方法。
接下来，如图2C所示，对衬底201进行加热以使得硅回流，从而至少改变该凹槽206的接近栅极一侧的侧壁的形状。该加热步骤可以在例如氢气氛中进行，对衬底201进行加热的温度可以在750℃到850℃的范围内，加热的时间可以为30秒到5分钟。在加热过程中，硅特别会在有较大曲率的区域(例如，各向异性刻蚀(如RIE刻蚀)得到的凹槽的角)处发生回流。因此，凹槽的角变圆，凹槽的接近栅极一侧的边缘朝向栅极一侧移动，从而使凹槽的接近栅极一侧的开口边缘位于间隔件204下方。在另一实施例中，可以控制加热步骤的温度和时间等条件，从而使凹槽的接近栅极一侧的开口边缘与栅极的侧壁对齐，如图2C'所示。在又一实施例中，在栅极绝缘层202是例如通过热氧化工艺形成的二氧化硅层的情况下，由于硅与二氧化硅层之间的接合较强，而硅与通过CVD形成的间隔件204之间的接合相对较弱，因此，在适当的温度(例如，800℃到850℃)下，硅回流会停止在硅与二氧化硅之间的界面处(即，凹槽的接近栅极一侧的开口边缘与栅极的侧壁对齐)，而不会再发生进一步的回流。因此，能够有效且简单地实现两级凹进式SiGe与栅极边缘的最优的接近，即，能够使SiGe结构的接近栅极一侧的前端与栅极边缘对齐。请注意，在上述实施例中，栅极绝缘层202并不限于通过热氧化工艺形成的二氧化硅层，而间隔件204也不限于通过CVD形成的间隔件。
接下来，如图2D所示，在间隔件204两侧分别形成稍后要被去除的伪侧墙205。伪侧墙205的材料要与间隔件204的材料不同。伪侧墙205可以由例如硅氮化物、硅氧化物等的材料构成，并且可以利用例如CVD的方法来沉积伪侧墙205的材料。
接下来，如图2E所示，以栅极203、间隔件204和伪侧墙205为掩模来刻蚀衬底201以形成凹部207，该凹部207具有比上述凹槽206更深的深度。刻蚀衬底的方法可以包括例如反应离子刻蚀(RIE)等的干法刻蚀方法。
接下来，如图2F所示，去除伪侧墙205。去除伪侧墙205的方法可以包括例如湿法去除方法。例如，在伪侧墙205由硅氮化物构成时，可以用热磷酸来湿法去除伪侧墙205，而在伪侧墙205由硅氧化物构成时，可以用氢氟酸来去除伪侧墙205。
接下来，如图2G所示，在凹槽和凹部中填充SiGe，从而形成半导体器件的源极/漏极结构，即，源极/漏极扩展区和源极/漏极区。填充SiGe的方法可以包括例如，外延生长SiGe。可选地，在外延生长SiGe的同时对SiGe进行原位(in situ)掺杂。在不用离子注入工艺而是通过原位掺杂SiGe形成源漏扩展区的情况下，能够实现超浅结。可选地，在填充SiGe之后，进行低温尖峰式快速热退火，从而改善Si/SiGe界面。填充的SiGe不一定要如图2G所示那样与衬底上表面齐平，而是可以高出衬底上表面以形成抬高的源极/漏极结构。该半导体器件优选地是pMOSFET。
(第二实施例)
第二实施例的半导体器件及其制造方法与第一实施例基本相同，但是不是在第一次刻蚀衬底之后而是在第二次刻蚀衬底之后，对硅衬底进行加热，使得发生硅的回流，至少改变凹槽的接近栅极一侧的侧壁的形状，从而使凹槽的前端更接近栅极边缘、甚至与栅极边缘对齐。也就是说，对衬底进行加热以使硅回流的步骤是在去除伪侧墙205的步骤之后并且在凹槽和凹部中填充SiGe的步骤之前进行的。
与第一实施例一样，本实施例能够使源极扩展区和漏极扩展区的接近栅极一侧的边缘上端延伸到间隔件204下方，甚至与栅极的侧壁对齐。通过使SiGe更接近栅极边缘，能够提高沟道中的应力，从而提高半导体器件的性能。在本实施例中，硅回流还可以改善整个凹槽和凹部的表面粗糙度，并且改善后续形成的Si/SiGe界面。
虽然已经通过示例性实施例对本发明进行了详细说明，但是本领域的技术人员应该理解，以上示例性实施例仅是为了进行说明，而不是为了限制本发明的范围。本领域的技术人员应该理解，可在不脱离本发明的范围和精神的情况下，对以上实施例进行修改。本发明的范围由所附权利要求来限定。

Claims (10)

1.一种制造半导体器件的方法，包括：
在衬底上形成栅极绝缘层和栅极；
在所述栅极两侧分别形成间隔件；
以所述栅极和所述间隔件为掩模来各向异性地刻蚀所述衬底以形成凹槽，所述凹槽的接近栅极一侧的侧壁与所述间隔件的侧壁基本齐平，并且所述凹槽的所述侧壁的上端具有角部；
在所述间隔件两侧分别形成伪侧墙；
对所述衬底进行加热以使得所述衬底的材料回流从而至少改变所述角部的形状，并使得所述角部相对于所述侧壁的其余部分更接近所述栅极的边缘；
在所述回流之后，以所述栅极、所述间隔件和所述伪侧墙为掩模来刻蚀所述衬底以形成凹部，所述凹部具有比所述凹槽更深的深度；
去除所述伪侧墙；以及
在所述凹槽和所述凹部中填充SiGe，从而形成所述半导体器件的源漏扩展区和源极/漏极区；
其中对所述衬底进行加热的步骤是在氢气氛中进行的，并且对所述衬底进行加热的温度在750℃到850℃的范围内，加热的时间为30秒到5分钟。
2.根据权利要求1所述的方法，其中所述填充SiGe的步骤包括外延生长SiGe的步骤。
3.根据权利要求2所述的方法，其中在外延生长SiGe的同时对SiGe进行原位掺杂。
4.根据权利要求1所述的方法，其中在所述形成栅极的步骤之后且在所述形成间隔件的步骤之前，对所述衬底进行晕圈注入。
5.根据权利要求1所述的方法，其中在所述填充SiGe的步骤之后，进行低温尖峰式快速热退火。
6.根据权利要求1所述的方法，其中刻蚀所述衬底的步骤均使用干法刻蚀工艺。
7.根据权利要求1所述的方法，其中所述衬底为硅衬底。
8.根据权利要求7所述的方法，其中所述形成栅极绝缘层和栅极的步骤包括通过热氧化工艺形成二氧化硅层以作为栅极绝缘层。
9.根据权利要求1所述的方法，其中所述半导体器件是pMOSFET。
10.根据权利要求1－9中的任一项所述的方法，其中在对所述衬底进行加热的步骤之后，所述凹槽的接近栅极一侧的开口边缘与所述栅极的侧壁对齐。
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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5640379B2 (ja) 2009-12-28 2014-12-17 ソニー株式会社 半導体装置の製造方法
US8564066B2 (en) * 2010-06-18 2013-10-22 International Business Machines Corporation Interface-free metal gate stack
US9287252B2 (en) * 2011-03-15 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor mismatch reduction
US9576868B2 (en) * 2012-07-30 2017-02-21 General Electric Company Semiconductor device and method for reduced bias temperature instability (BTI) in silicon carbide devices
CN104409505A (zh) * 2014-11-26 2015-03-11 上海华力微电子有限公司 嵌入式锗硅器件及其制作方法
CN104392930A (zh) * 2014-11-26 2015-03-04 上海华力微电子有限公司 嵌入式锗硅器件的制作方法
CN106960789B (zh) * 2016-01-08 2020-03-10 中芯国际集成电路制造(上海)有限公司 半导体器件以及改善半导体器件性能的方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070228417A1 (en) * 2006-04-03 2007-10-04 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating the same
JP2008078347A (ja) * 2006-09-21 2008-04-03 Sony Corp 半導体装置の製造方法および半導体装置
US20090261349A1 (en) * 2008-04-18 2009-10-22 Hynix Semiconductor Inc. Semiconductor device with strained channel and method of fabricating the same
US20100038727A1 (en) * 2007-03-29 2010-02-18 Texas Instruments Incorporated Carbon-Doped Epitaxial SiGe

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8207523B2 (en) * 2006-04-26 2012-06-26 United Microelectronics Corp. Metal oxide semiconductor field effect transistor with strained source/drain extension layer

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070228417A1 (en) * 2006-04-03 2007-10-04 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating the same
JP2008078347A (ja) * 2006-09-21 2008-04-03 Sony Corp 半導体装置の製造方法および半導体装置
US20100038727A1 (en) * 2007-03-29 2010-02-18 Texas Instruments Incorporated Carbon-Doped Epitaxial SiGe
US20090261349A1 (en) * 2008-04-18 2009-10-22 Hynix Semiconductor Inc. Semiconductor device with strained channel and method of fabricating the same

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
DA-WEN LIN ET AL.: "An Extreme Surface Proximity Push for Embedded SiGe in pMOSFETs Featuring Self-Aligned Silicon Reflow", 《IEEE ELECTRON DEVICE LETTERS》 *
N. YASUTAKE ET AL.: "A high performance pMOSFET with two-step recessed SiGe-S/D structure for 32nm node and beyond", 《SOLID-STATE ELECTRONICS》 *

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