CN108172516A - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
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- CN108172516A CN108172516A CN201711215205.1A CN201711215205A CN108172516A CN 108172516 A CN108172516 A CN 108172516A CN 201711215205 A CN201711215205 A CN 201711215205A CN 108172516 A CN108172516 A CN 108172516A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000003989 dielectric material Substances 0.000 claims abstract description 61
- 150000002500 ions Chemical class 0.000 claims abstract description 15
- 230000008859 change Effects 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims description 121
- 239000000463 material Substances 0.000 claims description 117
- 125000006850 spacer group Chemical group 0.000 claims description 50
- 239000011229 interlayer Substances 0.000 claims description 38
- 239000007924 injection Substances 0.000 claims description 35
- 238000002347 injection Methods 0.000 claims description 32
- 238000011049 filling Methods 0.000 claims description 28
- 239000004020 conductor Substances 0.000 claims description 20
- 230000008021 deposition Effects 0.000 claims description 14
- 238000005452 bending Methods 0.000 claims description 3
- 239000003446 ligand Substances 0.000 claims description 3
- 230000008901 benefit Effects 0.000 abstract description 2
- 230000001419 dependent effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 81
- 230000008569 process Effects 0.000 description 39
- 239000002019 doping agent Substances 0.000 description 29
- 238000000151 deposition Methods 0.000 description 27
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 24
- 239000000758 substrate Substances 0.000 description 20
- 238000005229 chemical vapour deposition Methods 0.000 description 18
- 239000007769 metal material Substances 0.000 description 14
- 238000005516 engineering process Methods 0.000 description 13
- 238000005530 etching Methods 0.000 description 13
- MWUXSHHQAYIFBG-UHFFFAOYSA-N nitrogen oxide Inorganic materials O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 12
- 239000000377 silicon dioxide Substances 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 238000000231 atomic layer deposition Methods 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 230000000873 masking effect Effects 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 8
- 238000001312 dry etching Methods 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 238000001039 wet etching Methods 0.000 description 8
- 239000011248 coating agent Substances 0.000 description 7
- 238000000576 coating method Methods 0.000 description 7
- 238000004544 sputter deposition Methods 0.000 description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 6
- 229910052718 tin Inorganic materials 0.000 description 6
- 229910052721 tungsten Inorganic materials 0.000 description 6
- 229910052726 zirconium Inorganic materials 0.000 description 6
- 238000000059 patterning Methods 0.000 description 5
- ITWBWJFEJCHKSN-UHFFFAOYSA-N 1,4,7-triazonane Chemical compound C1CNCCNCCN1 ITWBWJFEJCHKSN-UHFFFAOYSA-N 0.000 description 4
- -1 AlInAs Inorganic materials 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 229910004200 TaSiN Inorganic materials 0.000 description 4
- 229910010037 TiAlN Inorganic materials 0.000 description 4
- 229910052748 manganese Inorganic materials 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 3
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 239000011435 rock Substances 0.000 description 3
- 229910016570 AlCu Inorganic materials 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910004166 TaN Inorganic materials 0.000 description 2
- 150000004645 aluminates Chemical class 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229910052914 metal silicate Inorganic materials 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910000326 transition metal silicate Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 description 2
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910004541 SiN Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910010041 TiAlC Inorganic materials 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000011469 building brick Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- 239000002305 electric material Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910000078 germane Inorganic materials 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- FAHBNUUHRFUEAI-UHFFFAOYSA-M hydroxidooxidoaluminium Chemical compound O[Al]=O FAHBNUUHRFUEAI-UHFFFAOYSA-M 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000002045 lasting effect Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 238000004062 sedimentation Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 229910003468 tantalcarbide Inorganic materials 0.000 description 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 229910052723 transition metal Inorganic materials 0.000 description 1
- 229910000314 transition metal oxide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/3115—Doping the insulating layers
- H01L21/31155—Doping the insulating layers by ion implantation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76859—After-treatment introducing at least one additional element into the layer by ion implantation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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Abstract
提供了半导体器件及其制造方法,其中,改变介电材料的物理特性以在进一步处理期间为周围的结构提供额外的益处。通过将离子注入介电材料以形成改进区来实施改变。一旦已经注入离子,进一步处理依赖于改进区的改变的结构,而不是初始结构。
Description
技术领域
本发明的实施例涉及半导体器件及其制造方法。
背景技术
半导体器件用于诸如例如个人电脑、手机、数码相机和其它电子设备的各种电子应用中。通常通过在半导体衬底上方依次沉积绝缘或介电层、导电层和半导体材料层以及使用光刻图案化各个材料层以在各个材料层上形成电路组件和元件来制造半导体器件。
半导体工业通过最小部件尺寸的持续减小持续地改进各个电子组件(例如,晶体管、二极管、电阻器、电容器等)的集成密度,这允许更多的组件集成到给定的区域。然而,随着最小部件尺寸的减小,出现了应该解决的其他问题。
发明内容
本发明的实施例提供了一种制造半导体器件的方法,所述方法包括:沉积第一伪栅极堆叠件和第二伪栅极堆叠件,其中,所述第一伪栅极堆叠件具有第一沟道长度,并且所述第二伪栅极堆叠件具有与所述第一沟道长度不同的第二沟道长度;在所述第一伪栅极堆叠件和所述第二伪栅极堆叠件周围沉积层间电介质;平坦化所述第一伪栅极堆叠件、所述第二伪栅极堆叠件和所述层间电介质;将离子注入所述层间电介质以形成注入区;去除所述第一伪栅极堆叠件和所述第二伪栅极堆叠件以形成第一开口和第二开口,其中,去除所述第一伪栅极堆叠件和所述第二伪栅极堆叠件减小所述层间电介质的高度;以及用导电材料填充所述第一开口和所述第二开口。
本发明的另一实施例提供了一种制造半导体器件的方法,所述方法包括:形成邻近短沟道伪栅极的第一间隔件,形成邻近长沟道伪栅极的第二间隔件,并且形成邻近第一伪栅极的第三间隔件;邻近所述第一间隔件和所述第二间隔件沉积第一介电材料;在不去除所述短沟道伪栅极和所述长沟道伪栅极的情况下,去除所述第一伪栅极以形成第一开口;用第二介电材料填充所述第一开口;平坦化所述第二介电材料,其中,平坦化所述第二介电材料暴露所述短沟道伪栅极和所述长沟道伪栅极;将离子注入所述第一介电材料、所述短沟道伪栅极、所述长沟道伪栅极、所述第一间隔件和所述第二间隔件;去除所述短沟道伪栅极和所述长沟道伪栅极以形成第二开口;用导电材料填充所述第二开口;以及回蚀刻所述导电材料。
本发明的又一实施例提供了一种制造半导体器件的方法,所述方法包括:形成多个伪栅极堆叠件,其中,所述多个伪栅极堆叠件的第一个比所述多个伪栅极堆叠件的剩余部分具有更大的长度;在所述多个伪栅极堆叠件周围沉积层间电介质;在不替换所述多个伪栅极堆叠件的第一个的情况下,用介电材料替换所述多个伪栅极堆叠件的一个;平坦化所述介电材料与所述层间电介质和所述多个伪栅极堆叠件的第一个;沿着所述层间电介质和所述多个伪栅极堆叠件的顶面改变注入区中的组分的浓度;去除所述多个伪栅极堆叠件的第一个以形成第一开口,其中,去除所述多个伪栅极堆叠件的第一个还减小所述层间电介质的高度;用栅电极材料填充所述第一开口;使所述栅电极材料凹进至所述第一开口内以形成栅电极;以及用覆盖材料填充所述第一开口的剩余部分。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳理解本发明的各个方面。应该指出,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。
图1示出了根据一些实施例的鳍上方的栅极堆叠件的形成。
图2示出了根据一些实施例的栅极堆叠件的去除。
图3A至图3B示出了根据一些实施例的介电材料的沉积。
图4A至图4B示出了根据一些实施例的注入工艺。
图5示出了根据一些实施例的栅极堆叠件的去除。
图6示出了根据一些实施例的导电材料的沉积。
图7示出了根据一些实施例的导电材料的凹进。
图8示出了根据一些实施例的覆盖材料的沉积。
图9示出了根据一些实施例的覆盖材料的平坦化。
图10示出了根据一些实施例的位于低器件密度区中的层间电介质。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为便于描述,在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语,以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上),而本文使用的空间相对描述符可以同样地作出相应的解释。
现在参照图1,示出了诸如FinFET器件的半导体器件100的立体图。在实施例中,半导体器件100包括具有形成在其中的第一沟槽103的衬底101。衬底101可以是硅衬底,但是可以使用诸如绝缘体上半导体(SOI)、应变的SOI和绝缘体上硅锗的其他衬底。衬底101可以是p型半导体,但是在其他实施例中,它可以是n型半导体。
作为第一隔离区105的最终形成中的初始步骤,可以形成第一沟槽103。可以使用掩蔽层(未在图1中单独示出)以及合适的蚀刻工艺形成第一沟槽103。例如,掩蔽层可以是通过诸如化学气相沉积(CVD)的工艺形成的包括氮化硅的硬掩模,但是可以利用诸如氧化物、氮氧化物、碳化硅、这些的组合等的其他材料以及诸如等离子体增强化学气相沉积(PECVD)、低压化学气相沉积(LPCVD)或甚至氧化硅形成和随后的氮化的其他工艺。一旦形成,可以通过合适的光刻工艺图案化掩蔽层以暴露将被去除的衬底101的那些部分以形成第一沟槽103。
然而,如本领域技术人员将认识到的,以上描述的形成掩蔽层的工艺和材料不是可以用于保护衬底101的部分而同时暴露用于形成第一沟槽103的衬底101的那些部分的唯一方法。诸如图案化和显影光刻胶的任何合适的工艺可以用于暴露将被去除的衬底101的部分以形成第一沟槽103。所有这样的方法完全旨在包括在本实施例的范围内。
一旦已经形成和图案化掩蔽层,在衬底101中形成第一沟槽103。可以通过诸如反应离子蚀刻(RIE)的合适的工艺去除暴露的衬底101以在衬底101中形成第一沟槽103,但是可以使用任何合适的工艺。在实施例中,第一沟槽103可以形成为从衬底101的表面具有小于约的深度,诸如约
然而,如本领域技术人员将认识到的,以上描述的形成第一沟槽103的工艺仅是一个潜在工艺,并且不意味着是唯一实施例。相反,可以利用可以形成第一沟槽103的任何合适的工艺,并且可以使用包括任何数量的掩蔽和去除步骤的任何合适的工艺。
除了形成第一沟槽103,掩蔽和蚀刻工艺额外地由未被去除的衬底101的那些部分形成鳍107。为了方便,鳍107在图中示出为由虚线与衬底101分隔开,但是分隔的物理标识可以存在或可以不存在。如下面所讨论的,这些鳍107可以用于形成多栅极FinFET晶体管的沟道区。虽然图1仅示出由衬底101形成的三个鳍107,但是可以使用任何数量的鳍107。
鳍107可以形成为使得它们在衬底101的表面处具有介于约5nm和约80nm之间的宽度,诸如约30nm。此外,鳍107之间可以彼此间隔开介于约10nm和约100nm之间的距离,诸如约50nm。通过以这种方式间隔开鳍107,每个鳍107可以形成单独的沟道区,但是仍足够接近以共享共同的栅极(下面进一步讨论)。
一旦已经形成第一沟槽103和鳍107,可以用介电材料填充第一沟槽103,并且可以使介电材料凹进在第一沟槽103内以形成第一隔离区105。介电材料可以是氧化物材料、高密度等离子体(HDP)氧化物等。在第一沟槽103的可选择的清洗和衬垫之后,可以使用化学气相沉积(CVD)方法(例如,HARP工艺)、高密度等离子体CVD方法或本领域已知的其他任何形成方法来形成介电材料。
通过用介电材料过填充第一沟槽103和衬底101来填充第一沟槽103,并且然后通过诸如化学机械抛光(CMP)、蚀刻、这些的组合等的合适的工艺去除位于第一沟槽103和鳍107外部的过量的材料。在实施例中,去除工艺也去除位于鳍107上方的任何介电材料,使得介电材料的去除将暴露鳍107的表面以用于进一步的处理步骤。
一旦已经用介电材料填充第一沟槽103,然后可以使介电材料凹进远离鳍107的表面。可以实施凹进以暴露邻近鳍107的顶面的鳍107的侧壁的至少部分。可以通过将鳍107的顶面浸入诸如HF的蚀刻剂,使用湿蚀刻来使介电材料凹进,但是可以使用诸如H2的其他蚀刻剂以及诸如反应离子蚀刻、采用诸如NH3/NF3的蚀刻剂的干蚀刻、化学氧化物去除或干化学清洗的其他方法。介电材料可以从鳍107的表面凹进介于约和约之间的距离,诸如约此外,该凹进也可以去除位于鳍107上方的任何残留的介电材料以确保暴露鳍107用于进一步处理。
然而,如本领域技术人员将认识到的,以上描述的步骤可能仅仅是用于填充和凹进介电材料的所有工艺流程的一部分。例如,衬垫步骤、清洗步骤、退火步骤、间隙填充步骤、这些的组合等也可以用于形成第一沟槽103和以介电材料填充第一沟槽103。所有潜在工艺步骤完全旨在包括在本实施例的范围内。
在已经形成第一隔离区105之后,可以在每个鳍107上方形成伪栅极电介质109、位于伪栅极电介质109上方的伪栅电极111以及第一间隔件113。在实施例中,可以通过热氧化、化学气相沉积、溅射或本领域已知并用于形成栅极电介质的任何其他方法来形成伪栅极电介质109。取决于栅极电介质形成的技术,鳍107的顶部上的伪栅极电介质109的厚度可以与鳍107的侧壁上的伪栅极电介质的厚度不同。
伪栅极电介质109可以包括厚度在从约3埃至约100埃(诸如约10埃)的范围内的诸如二氧化硅或氮氧化硅的材料。伪栅极电介质109可以由高介电常数(高k)材料(例如,具有大于约5的相对介电常数)形成,诸如等效氧化物厚度为约0.5埃至约100埃(诸如约10埃以下)的氧化镧(La2O3)、氧化铝(Al2O3)、氧化铪(HfO2)、氮氧化铪(HfON)或氧化锆(ZrO2)或这些的组合。此外,二氧化硅、氮氧化硅和/或高k材料的任何组合也可以用于伪栅极电介质109。
伪栅电极111可以包括导电材料并且可以选自由多晶硅、W、Al、Cu、AlCu、W、Ti、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、Ta、TaN、Co、Ni、这些的组合等组成的组。可以通过化学气相沉积(CVD)、溅射沉积或本领域已知并用于沉积导电材料的其他技术来沉积伪栅电极111。伪栅电极111的厚度可以在约至约的范围内。伪栅电极111的顶面可以具有非平坦顶面,并且可以在图案化伪栅电极111之前被平坦化。
一旦形成,可以图案化伪栅极电介质109和伪栅电极111以形成一个或多个伪堆叠件116、短沟道伪栅极堆叠件115和长沟道伪栅极堆叠件117。在实施例中,一个或多个伪堆叠件116可以用于帮助防止有源器件之间的区域中的不期望的变化,诸如通过防止制造期间引起的凹陷或其他问题。在实施例中,一个或多个伪堆叠件116可以形成为具有介于约10nm和约50nm之间的第一宽度W1,诸如约35nm。然而,可以利用任何合适的宽度。
此外,短沟道伪栅极堆叠件115将用于帮助形成短沟道晶体管607(图1中未示出,但是下面参照图6示出和进一步描述)的栅极堆叠件。例如,在一些实施例中,短沟道晶体管可以期望具有介于约10nm和约50nm之间的沟道长度,诸如小于或等于约40nm。由此,在这个实施例中,短沟道伪栅极堆叠件115可以具有介于约10nm和约50nm之间的第二宽度W2,诸如小于或等于约10nm,但是可以利用任何合适的宽度。
最后,长沟道伪栅极堆叠件117将用于帮助形成长沟道晶体管609(图1中未示出,但是下面参照图6示出和进一步描述)的栅极堆叠件。例如,在一些实施例中,长沟道晶体管可以期望具有介于约10nm和约50nm之间的沟道长度,诸如大于约10nm。由此,在这个实施例中,长沟道伪栅极堆叠件117可以具有介于约50nm和约150nm之间的第三宽度W3,诸如大于约100nm,但是可以利用任何合适的宽度。
短沟道伪栅极堆叠件115和长沟道伪栅极堆叠件117限定位于它们的单独的伪栅极电介质109下面的鳍107的每侧上的多个沟道区。例如,可以使用本领域已知的沉积和光刻技术通过在伪栅电极111上沉积和图案化栅极掩模(未在图1中单独示出)来形成短沟道伪栅极堆叠件115和长沟道伪栅极堆叠件117。栅极掩模可以结合共用的掩蔽和牺牲材料,诸如(但不限于)氧化硅、氮氧化硅、SiCON、SiC、SiOC和/或氮化硅并且可以沉积至介于约和约之间的厚度。可以使用干蚀刻工艺来蚀刻伪栅电极111和伪栅极电介质109以形成图案化的短沟道伪栅极堆叠件115和图案化的长沟道伪栅极堆叠件117。
一旦已经图案化短沟道伪栅极堆叠件115和长沟道伪栅极堆叠件117(以及伪堆叠件116),可以形成第一间隔件113。第一间隔件113可以形成在短沟道伪栅极堆叠件115、伪堆叠件116和长沟道伪栅极堆叠件117的相对侧上。通常通过在之前形成的结构上毯式沉积间隔件层(未在图1中单独示出)来形成第一间隔件113。间隔件层可以包括SiN、氮氧化物、SiC、SiON、SiOCN、SiOC、氧化物等并且可以通过诸如化学气相沉积(CVD)、等离子体增强CVD、溅射的用于形成这样的层的方法和本领域已知的其他方法来形成。间隔件层可以包括与第一隔离区105内的介电材料具有不同的蚀刻特性的不同的材料或与第一隔离区105内的介电材料相同的材料。然后可以图案化第一间隔件113,诸如通过一个或多个蚀刻以从结构的水平表面去除间隔件层以形成第一间隔件113。
在实施例中,第一间隔件113可以形成为具有介于约和约之间的厚度。此外,一旦已经形成第一间隔件113,邻近短沟道伪栅极堆叠件115、伪堆叠件116和长沟道伪栅极堆叠件117的一个的第一间隔件113可以与邻近短沟道伪栅极堆叠件115、伪堆叠件116和长沟道伪栅极堆叠件117的另一个的第一间隔件113分隔开第一距离D1,第一距离D1介于约10nm和50nm之间,诸如约35nm。然而,可以利用任何合适的厚度和距离。
图1也示出了从未由短沟道伪栅极堆叠件115、伪堆叠件116、长沟道伪栅极堆叠件117和第一间隔件113保护的那些区域去除鳍107以及再生长源极/漏极区121。可以通过使用短沟道伪栅极堆叠件115、伪堆叠件116、长沟道伪栅极堆叠件117和第一间隔件113作为硬掩模的反应离子蚀刻(RIE)或通过任何其他合适的去除工艺来实施从未被保护的那些区域去除鳍107。可以继续该去除,直到鳍107与第一隔离区105的表面齐平(如图所示)或位于第一隔离区105的表面下方。
在另一实施例中,可以继续去除鳍107的工艺以去除位于鳍107之间的第一隔离区105的那些部分。由此,通过去除位于鳍107之间的第一隔离区105的那些部分,暴露了鳍107下方的衬底101,从而允许如下所述的源极/漏极区121的完全再生长。
一旦已经去除鳍107的这些部分,放置和图案化硬掩模(未单独示出)以覆盖伪栅电极111以防止生长,并且源极/漏极区121可以再生长至与每个鳍107接触。在实施例中,可以再生长源极/漏极区121,并且在一些实施例中,可以再生长源极/漏极区121以形成应力源,应力源将对位于短沟道伪栅极堆叠件115、伪堆叠件116和长沟道伪栅极堆叠件117下方的鳍107的沟道区施加应力。在鳍107包括硅并且FinFET是p型器件的实施例中,可以由诸如硅的材料或具有与沟道区不同的晶格常数的诸如硅锗的材料通过选择性外延工艺来再生长源极/漏极区121。在其他实施例中,源极/漏极区121可以包括诸如GaAs、GaP、GaN、InP、InAs、InSb、GaAsP、AlGaN、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP、这些的组合等的材料。外延生长工艺可以使用诸如硅烷、二氯硅烷、锗烷等的前体并且可以持续介于约5分钟和约120分钟,诸如约30分钟。
在实施例中,源极/漏极区121可以形成为具有介于约和约之间的厚度,并且可以具有在第一隔离区105的上表面之上的介于约5nm和约250nm之间(诸如约100nm)的高度。然而,可以利用任何合适的高度。
一旦已经形成源极/漏极区121,可以将掺杂剂注入源极/漏极区121内,通过注入适当的掺杂剂来补偿鳍107中的掺杂剂。例如,可以注入诸如硼、镓、铟等的p型掺杂剂以形成PMOS器件。可选地,可以注入诸如磷、砷、锑等的n型掺杂剂以形成NMOS器件。可以使用短沟道伪栅极堆叠件115、伪堆叠件116、长沟道伪栅极堆叠件117和第一间隔件113作为掩模来注入这些掺杂剂。应该注意,本领域技术人员将意识到,许多其他工艺、步骤等可以用于注入掺杂剂。例如,本领域技术人员将意识到,可以使用间隔件和衬垫的各种组合来实施多个注入以形成具有适用于特定目的的特定形状或特征的源极/漏极区。任何这些工艺可以用于注入掺杂剂,并且以上描述不旨在将本实施例限制于以上呈现的步骤。
此外,此时,去除在源极/漏极区121的形成期间覆盖伪栅电极111的硬掩模。在实施例中,可以使用例如对硬掩模的材料具有选择性的湿或干蚀刻工艺去除硬掩模。然而,可以利用任何合适的去除工艺。
图1也示出了位于短沟道伪栅极堆叠件115、伪堆叠件116、长沟道伪栅极堆叠件117、第一间隔件113和源极/漏极区121上方的层间介电(ILD)层122(在图1中以虚线示出以更清楚地示出下面的结构)的形成。在实施例中,可以通过首先在下面的结构上方形成衬垫层123(为了清楚,未在图1中单独示出,但是在图2中示出)来开始ILD层122的形成。衬垫层123可以是诸如TiN或TiAlC的介电材料,并且可以使用诸如化学气相沉积(CVD)、物理气相沉积(PVD)、原子层沉积(ALD)等的沉积工艺来沉积。衬垫层123可以沉积至介于约5nm和约10nm之间的厚度,诸如约5nm,然而可以利用任何合适的厚度。
ILD层122可以包括诸如二氧化硅、硼磷硅酸盐玻璃(BPSG)的材料,但是可以使用任何合适的电介质。可以使用诸如PECVD的工艺来形成ILD层122,但是可以可选地使用诸如LPCVD的其他工艺。ILD层122可以形成至介于约和约之间的厚度。一旦形成,可以例如使用诸如化学机械抛光工艺的平坦化工艺平坦化ILD层122与第一间隔件113,但是可以利用任何合适的工艺。
图2示出了第一硬掩模201的放置和图案化以及从伪堆叠件116去除伪栅电极111和伪栅极电介质109,其中图2是沿着线2-2’的图1的结构的截面图。在实施例中,第一硬掩模201可以是使用诸如CVD、PVD或ALD的沉积工艺沉积的诸如氮化硅的介电材料,其厚度介于约5nm和约10nm之间,诸如约10nm。然而,可以利用任何合适的材料、工艺和厚度。
一旦已经沉积第一硬掩模201,可以使用例如光刻掩蔽和蚀刻工艺图案化第一硬掩模201。在实施例中,在第一硬掩模201上方放置诸如光刻胶的光敏材料,然后将光敏材料暴露于图案化的能量源(例如光)以引起被能量影响的光敏材料的那部分中的化学反应。在化学反应已经改变光敏材料的曝光部分的物理性质之后,可以施加显影剂以将光敏材料的曝光部分与光敏材料的未曝光部分分离。
一旦已经图案化光敏材料,可以使用例如各向异性蚀刻工艺将图案转印至第一硬掩模201。在实施例中,例如,各向异性蚀刻工艺可以是蚀刻由光敏材料暴露的第一硬掩模201的部分的反应离子蚀刻。
在实施例中,图案化第一硬掩模201以暴露伪堆叠件116,同时保护短沟道伪栅极堆叠件115并且也保护长沟道伪栅极堆叠件117。一旦已经暴露伪堆叠件116,然后可以使用例如各项同性或各向异性蚀刻工艺去除伪堆叠件116的材料(例如,伪栅电极111)以形成第一开口203。例如,采用对伪栅电极111的材料具有选择性的蚀刻剂的反应离子蚀刻或湿蚀刻可以用于去除伪栅电极111的材料。
然而,除了简单地去除伪栅电极111的材料,在一些实施例中,伪栅电极111的去除也将去除由第一硬掩模201暴露的那些部分中的第一间隔件113、衬垫层123和ILD层122的材料。然而,由于使用的蚀刻剂对伪栅电极111更具有选择性,所以未完全去除第一间隔件113、衬垫层123和ILD层122的材料,但是在由第一硬掩模201暴露的那些部分中凹进。
在ILD层122具有介于约80nm和约100nm之间(诸如约90nm)的第一高度H1的具体实施例中,在制造工艺的这个时候,使第一间隔件113、衬垫层123和ILD层122的材料凹进,使得凹槽具有介于约50nm和约70nm之间(诸如约60nm)的第二高度H2。此外,第一开口203可以形成为具有介于约150nm和约170nm之间(诸如约160nm)的第四宽度W4。然而,可以利用任何合适的尺寸。
图3A至图3B示出了用介电材料301重新填充通过从伪堆叠件116去除伪栅电极111留下的第一开口203。在实施例中,可以沉积介电材料301以填充和过填充第一开口203并且也在第一硬掩模201(未在图3A中示出)上方延伸。介电材料301可以是诸如氮化硅的材料,并且可以使用诸如CVD、PVD、ALD、这些的组合等的沉积工艺沉积。然而,可以利用任何合适的材料和放置工艺。
一旦已经放置介电材料301以填充和/或过填充第一开口203,然后平坦化介电材料301以去除位于第一开口203外部的任何过量的材料。在实施例中,诸如化学机械抛光、一个或多个平坦化蚀刻工艺、这些的组合等的平坦化工艺可以用于平坦化介电材料301并且从第一开口203(通过从伪堆叠件116去除伪栅电极111而形成的)外部去除介电材料301。
此外,平坦化工艺可以用于去除第一硬掩模201。在实施例中,仅通过继续平坦化工艺,可以使用平坦化工艺(例如,CMP)去除第一硬掩模201,一旦暴露第一硬掩模201,并且然后继续平坦化工艺,直到去除第一硬掩模201。然而,任何合适的工艺可以用于去除第一硬掩模201。
此外,平坦化工艺也可以用于暴露短沟道伪栅极堆叠件115和长沟道伪栅极堆叠件117中的伪栅电极111。在实施例中,通过继续平坦化工艺暴露短沟道伪栅极堆叠件115和长沟道伪栅极堆叠件117中的伪栅电极111,以不仅从短沟道伪栅极堆叠件115和长沟道伪栅极堆叠件117中的伪栅电极111上方去除第一硬掩模201,而且从短沟道伪栅极堆叠件115和长沟道伪栅极堆叠件117中的伪栅电极111上方去除衬垫层123。由此,衬垫层123、第一间隔件113和至少部分ILD层122彼此齐平。
由此,在平坦化工艺的最后,伪栅电极111(以及伪栅极电介质109)、第一间隔件113和介电材料301可以均彼此齐平。此外,这些的每个可以具有介于约80nm和约100nm之间的第三高度H3,诸如约90nm。然而,可以利用任何合适的高度。
然而,通过将平坦化工艺用于平坦化所有这些层,在部件未紧密间隔的一些区域中的ILD层122将经历凹陷(在图3A由标记为303的虚线圆圈突出显示)。该凹陷在平坦化工艺(例如,CMP)期间由这些因素的组合引起:包括周围部件的结构强度、在CMP料浆内使用的蚀刻剂的选择性、ILD层122的材料等。该凹陷可以在随后的处理期间引起额外的问题,诸如栅电极(下面参照图6进一步讨论)的形成。在实施例中,ILD层122的材料可以经历小于ILD层122的高度的约25%的第一凹陷深度Dd1,诸如介于约和约之间,诸如约
此外,图3B示出了邻近ILD层122(已经经历凹陷)的顶面的虚线框305中的ILD层122的材料的特写(但不是按比例的)表示。在ILD层122是氧化硅的实施例中,ILD层122的材料包括与氧原子键合的硅原子的晶格。然而,在其他实施例中,ILD层122将具有取决于ILD层122所选择的材料的不同原子的晶格。
图4A至图4B示出了可以用于在随后的处理期间帮助防止发生额外的问题的第一注入工艺(在图4A中由标记401的箭头表示)。在实施例中,实施第一注入工艺401以将第一掺杂剂注入至ILD层122内。在实施例中,可以将第一掺杂剂注入至ILD层122内以改变ILD层122的化学结构,并且支持ILD层122的至少顶面的结构强度和/或蚀刻选择性。在实施例中,第一掺杂剂可以是可以帮助改变和支持ILD层122的材料的结构支撑或蚀刻选择性的任何合适的掺杂剂。例如,第一掺杂剂可以包括可以用于在ILD层122内形成平坦四配位复合物的诸如碳、硅、锗、锡和铅的IV族的四配位基配体的一种或多种。然而,可以利用任何合适的掺杂剂或掺杂剂的组合。
在实施例中,可以使用第一注入工艺401将第一掺杂剂注入至ILD层122内,由此期望的第一掺杂剂的离子加速并且导向ILD层122以形成第一注入区403。第一注入工艺401可以利用加速器系统以加速第一剂量浓度的期望的第一掺杂剂的离子。由此,虽然利用的精确的剂量浓度将至少部分地取决于ILD层122和所使用的物质,但是在一个实施例中,加速器系统可以利用从约1.0×1016原子/cm2至约2.0×1016原子/cm2的剂量浓度。此外,可以垂直于ILD层122或从垂直于ILD层122以介于约20°和约30°之间(诸如约25°)的角度注入第一掺杂剂。
通过将第一掺杂剂注入ILD层122,可以改变ILD层122的材料以增加ILD层122的至少部分的结构完整性和蚀刻选择性。在实施例中,可以将第一掺杂剂注入至ILD层122内至介于约1.0×1016原子/cm2和约2.0×1016原子/cm2(诸如约1.5×1016原子/cm2)的浓度。然而,可以利用任何合适的浓度。ILD层122内的第一注入区403可以具有介于约和约之间的注入深度Di,但是可以利用任何合适的深度。
此外,代替仅注入ILD层122内,第一注入工艺401将第一掺杂剂直接注入未被覆盖的剩余的材料。例如,第一注入工艺401也将第一掺杂剂注入短沟道伪栅极堆叠件115和长沟道伪栅极堆叠件117的伪栅电极111内,并且也将第一掺杂剂注入衬垫层123、第一间隔件113和介电材料301内,并且形成具有注入深度Di的第一注入区403。
图4B示出了图3B中所示的ILD层122的材料的部分的相同的特写图,但是其中已经使用第一注入工艺401注入第一掺杂剂。在ILD层122的材料是二氧化硅并且第一掺杂剂是硅的实施例中,第一掺杂剂将代替一些(如果不是大多数)二氧化硅内的氧原子,并且将用硅的晶格代替二氧化硅的晶格,从而形成富Si-X层,其中“X”是第一掺杂剂。通过用硅代替二氧化硅,可以增加沿着ILD层122的顶面的材料的结构完整性和/或蚀刻选择性以在进一步处理期间帮助邻近的结构。
图5示出了在形成第一注入区403之后,可以去除短沟道伪栅极堆叠件115和长沟道伪栅极堆叠件117中的伪栅电极111和伪栅极电介质109,并且代替为形成短沟道晶体管607和长沟道晶体管609(未在图5中示出,但是下面参照图6示出和描述)。在实施例中,可以使用例如利用对伪栅电极111的材料具有选择性的蚀刻剂的一个或多个湿或干蚀刻工艺(在图5中表示为标记501的箭头)去除伪栅电极111和伪栅极电介质109。然而,可以利用任何合适的去除工艺。
然而,当去除了伪栅电极111和伪栅极电介质109时,也可能去除ILD层122的材料,从而减小ILD层122的结构完整性。但是,由于在一个或多个湿或干蚀刻工艺501开始时存在第一注入区403,第一注入区403比没有注入第一掺杂剂的区域对蚀刻工艺更加具有抗性。
例如,在ILD层122最初是诸如二氧化硅的材料并且利用诸如HF的蚀刻剂的实施例中,通过第一注入工艺401形成“富Si-X”第一注入区403而开始的改变将改变第一注入区403的蚀刻选择性,使得第一注入区403以比ILD层122的初始二氧化硅材料更低的速率被蚀刻。由此,在一个或多个湿或干蚀刻工艺501期间比原本可能的去除更少的ILD层122的材料。例如,在实施例中,可以去除ILD层122的材料,使得ILD层122保持介于约40nm和约50nm之间的第四高度H4,诸如约45nm。
此外,关于在介电材料301的平坦化期间初始发生的ILD层122的凹陷(例如,见图3A),该凹陷在一个或多个湿或干蚀刻工艺501期间可以缓解。例如,由于ILD层122的材料的整体高度减小,初始第一凹陷深度Dd1也将减小。例如,在一个或多个湿或干蚀刻工艺501之后,ILD层122的材料可以具有介于约和约之间(诸如约)的第二凹陷深度Dd2。
图6示出了一旦已经去除短沟道伪栅极堆叠件115和长沟道伪栅极堆叠件117中的伪栅电极111和伪栅极电介质109,可以重新填充留下的开口以形成短沟道栅极堆叠件601和长沟道栅极堆叠件603。在实施例中,短沟道栅极堆叠件601和长沟道栅极堆叠件603均可以包括将形成用于晶体管的栅电极的栅电极605,并且栅电极605可以是诸如钨的导电材料,但是可以使用任何合适的材料。
在钨用作栅电极605的材料的实施例中,可以在形成栅极电介质之后使用诸如CVD、PVD、ALD、这些的组合等的沉积工艺来沉积栅电极605的材料。可以沉积栅电极605的材料以填充和/或过填充通过去除短沟道伪栅极堆叠件115和长沟道伪栅极堆叠件117中的伪栅电极111和伪栅极电介质109而留下的开口。一旦已经沉积栅电极605的材料以填充和/或过填充通过去除短沟道伪栅极堆叠件115和长沟道伪栅极堆叠件117中的伪栅电极111和伪栅极电介质109而留下的开口,可以使用诸如化学机械抛光(CMP)的平坦化工艺去除位于开口外部的栅电极605的过量材料,但是可以利用平坦化的任何合适的方法。
在另一实施例中,可以使用第一介电材料、第一金属材料、第二金属材料和第三金属材料(在图6中未单独示出该材料)来形成短沟道栅极堆叠件601和长沟道栅极堆叠件603。在实施例中,第一介电材料是通过诸如原子层沉积、化学气相沉积等沉积的诸如HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、LaO、ZrO、Ta2O5、这些的组合等的高k材料。第一介电材料可以沉积至介于约和约之间的厚度,但是可以利用任何合适的材料和厚度。
第一金属材料可以形成为邻近于第一介电材料并且可以由诸如Ti、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、TaN、Ru、Mo、WN、其他金属氧化物、金属氮化物、金属硅酸盐、过渡金属氧化物、过渡金属氮化物、过渡金属硅酸盐、金属的氮氧化物、金属铝酸盐、硅酸锆、铝酸锆、这些的组合等的金属材料形成。可以使用原子层沉积、化学气相沉积、溅射等的沉积工艺将第一金属材料沉积至介于约和约之间的厚度,但是可以利用任何合适的沉积工艺或厚度。
第二金属材料可以形成为邻近于第一金属材料,并且在具体实施例中可以类似于第一金属材料。例如,第二金属材料可以由诸如Ti、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、TaN、Ru、Mo、WN、其他金属氧化物、金属氮化物、金属硅酸盐、过渡金属氧化物、过渡金属氮化物、过渡金属硅酸盐、金属的氮氧化物、金属铝酸盐、硅酸锆、铝酸锆、这些的组合等的金属材料形成。此外,可以使用诸如原子层沉积、化学气相沉积、溅射等的沉积工艺将第二金属材料沉积至介于约和约之间的厚度,但是可以利用任何合适的沉积工艺或厚度。
第三金属材料填充通过去除短沟道伪栅极堆叠件115和长沟道伪栅极堆叠件117中的伪栅电极111和伪栅极电介质109而留下的开口的剩余部分。在实施例中,第三金属材料是诸如W、Al、Cu、AlCu、W、Ti、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、TiN、Ta、TaN、Co、Ni、这些的组合等的金属材料并且可以使用诸如原子层沉积、化学气相沉积、溅射等的沉积工艺沉积,以填充和/或过填充通过去除短沟道伪栅极堆叠件115和长沟道伪栅极堆叠件117中的伪栅电极111和伪栅极电介质109而留下的开口。在具体实施例中,第三金属材料可以沉积至介于约和约之间的厚度,但是可以利用任何合适的材料、沉积工艺和厚度。一旦沉积,可以使用例如化学机械平坦化工艺使材料彼此齐平。
然而,该平坦化工艺将不完全平坦化栅电极605的材料的每个部分。相反,短沟道栅极堆叠件601中的栅电极605的材料可以与第一间隔件113的材料齐平,但是位于长沟道栅极堆叠件603的开口内的栅电极605的材料将由于发生凹陷而出现额外的去除。例如,在实施例中,长沟道栅极堆叠件603中的栅电极605的材料可以出现介于约和约之间(诸如约)的第三凹陷深度Dd3,但是可以利用任何合适的尺寸。
然而,由于第一注入区403的存在而减少了ILD层122的材料的去除,存在ILD层122的额外的材料以为栅电极605的材料提供额外的结构支撑。由此,与不形成第一注入区403的工艺相比,栅电极605的材料经历的凹陷也保持最小。
图7示出了在已经形成和平坦化栅电极605的材料之后,可以使短沟道伪栅极堆叠件115和长沟道伪栅极堆叠件117中的栅电极605的材料凹进至ILD层122的表面下方以为覆盖层801(图7中未示出,但是下面参照图8示出和描述)的放置作准备。在实施例中,可以使用例如利用对栅电极605的材料具有选择性的蚀刻剂的湿或干蚀刻工艺来使栅电极605的材料凹进。在实施例中,可以使栅电极605的材料凹进,使得栅电极605具有介于约10nm和约20nm之间(诸如约15nm)的第三高度H3。然而,可以利用任何合适的工艺和距离。
然而,由于长沟道栅极堆叠件603中的栅电极605的凹陷已经保持为最小,由于该凹陷,栅电极605的凹进将暴露下面的鳍107的潜力更小。具体地,如果长沟道栅极堆叠件603中的栅电极605的凹陷足够大,形成短沟道栅极堆叠件601中的栅电极605所需的凹进也可以导致长沟道栅极堆叠件603中的栅电极暴露并且损坏下面的鳍107。然而,通过使用第一注入区403将栅电极605的凹陷保持为最小,可以减小或消除对下面的鳍的这种损坏,并且在不发生损坏的情况下,可以减小栅极堆叠件的整体高度。
图8示出了一旦已经使栅电极605的材料凹进,可以在栅电极605上方沉积覆盖层801。在实施例中,覆盖层801是使用诸如原子层沉积、化学气相沉积、溅射等的沉积工艺沉积的诸如SiN、SiON、SiCON、SiC、SiOC、这些的组合等的材料。可以沉积覆盖层801以填充和/或过填充通过从短沟道伪栅极堆叠件115和长沟道伪栅极堆叠件117去除伪栅电极111形成的开口的剩余部分。
图9示出一旦已经形成覆盖层801的材料,可以使用例如平坦化工艺去除位于开口(通过从短沟道伪栅极堆叠件115和长沟道伪栅极堆叠件117去除伪栅电极111形成的)外部的覆盖层801的过量材料。在实施例中,平坦化工艺可以是化学机械抛光(CMP),但是诸如研磨工艺或一系列的一个或多个蚀刻的任何合适的平坦化工艺可以用于从开口(通过从短沟道伪栅极堆叠件115和长沟道伪栅极堆叠件117去除伪栅电极111形成的)的外部去除覆盖层801的材料。
此外,用于去除覆盖层801的过量材料的平坦化工艺也可以用于减小器件的整体栅极高度。在实施例中,平坦化工艺可以用于将栅极高度减小至介于约40nm和约50nm之间(诸如约45nm)的第四高度H4。然而,可以利用任何合适的栅极高度。
图10示出了ILD层122的另一视图,为了清楚,示出为不同的比例。在图10所示的实施例中,在高器件密度区1003和低器件密度区1001中均存在ILD层122。例如,在高器件密度区1003中,可以存在介于约5个/200nm和约7个/200nm之间(诸如约6个/200nm)的第一器件密度,而在低器件密度区1001中,可以存在小于第一器件密度的第二器件密度,诸如介于约1个/200nm和约3个/200nm之间(诸如约2个/200nm)。然而,可以利用任何合适的密度。
在该实施例中,低器件密度区1001内的ILD层122具有较大的面积,并且以上讨论的工艺将导致某些ILD层122的外侧边缘向外弯曲。在具体实施例中,并且看低器件密度区1001内的ILD层122和邻近的高器件密度区1003内的介电材料301,本文描述的工艺将在ILD层122内生成弯曲,其中第一角度α1介于约130°和约140°之间,诸如大于约135°,其中,在从ILD层122的底部测量的ILD层122的高度的约50%和约70%之间的距离处测量第一角度α1。
此外,图10也示出了,在一些实施例中,从伪堆叠件116去除伪栅电极111可以蚀刻到第一隔离区105内。一旦在开口内沉积介电材料301,介电材料301的延伸件将延伸到第一隔离区105内。然而,考虑到本文讨论的工艺,当延伸件延伸到第一隔离区105内时,延伸件将具有相当一致的宽度。例如,在实施例中,该延伸件可以具有在延伸件的深度的10%的距离处的第五宽度W5和在延伸件的深度的90%的距离处的第六宽度W6,其中,第六宽度W6介于第五宽度W5的约80%和约100%之间。
根据实施例,提供了一种制造半导体器件的方法,包括沉积第一伪栅极堆叠件和第二伪栅极堆叠件,其中,第一伪栅极堆叠件具有第一沟道长度,并且第二伪栅极堆叠件具有与第一沟道长度不同的第二沟道长度。在第一伪栅极堆叠件和第二伪栅极堆叠件周围沉积层间电介质,并且平坦化第一伪栅极堆叠件、第二伪栅极堆叠件和层间电介质。将离子注入层间电介质以形成注入区,并且去除第一伪栅极堆叠件和第二伪栅极堆叠件以形成第一开口和第二开口,其中,去除第一伪栅极堆叠件和第二伪栅极堆叠件减小了层间电介质的高度。用导电材料填充第一开口和第二开口。
在上述方法中,还包括使所述导电材料凹进至所述第一开口内。
在上述方法中,还包括使所述导电材料凹进至所述第一开口内,还包括用覆盖材料填充所述第一开口的剩余部分。
在上述方法中,还包括使所述导电材料凹进至所述第一开口内,还包括用覆盖材料填充所述第一开口的剩余部分,还包括平坦化所述覆盖材料和所述层间电介质。
在上述方法中,其中,注入所述离子在所述层间电介质中生成四配位基配体。
在上述方法中,其中,所述层间电介质具有侧壁,所述侧壁的弯曲角度大于135°。
在上述方法中,其中,所述第二沟道长度至少为10nm。
根据另一实施例,提供了一种制造半导体器件的方法,包括形成邻近短沟道伪栅极的第一间隔件,形成邻近长沟道伪栅极的第二间隔件,以及形成邻近第一伪栅极的第三间隔件。邻近第一间隔件和第二间隔件沉积第一介电材料,并且在不去除短沟道伪栅极和长沟道伪栅极的情况下,去除第一伪栅极以形成第一开口。用第二介电材料填充第一开口,并且平坦化第二介电材料,其中,平坦化第二介电材料暴露短沟道伪栅极和长沟道伪栅极。将离子注入第一介电材料、短沟道伪栅极、长沟道伪栅极、第一间隔件和第二间隔件。去除短沟道伪栅极和长沟道伪栅极以形成第二开口,用导电材料填充第二开口,并且回蚀刻导电材料。
在上述方法中,其中,所述离子是IV族元素。
在上述方法中,其中,所述离子是IV族元素,其中,在注入所述离子之后,所述离子的浓度介于1.0×1016原子/cm2和2.0×1016原子/cm2之间。
在上述方法中,其中,所述长沟道伪栅极具有大于10nm的长度。
在上述方法中,其中,所述长沟道伪栅极具有大于10nm的长度,其中,所述短沟道伪栅极具有小于10nm的长度。
在上述方法中,还包括在回蚀刻所述导电材料之后,在所述导电材料上方沉积覆盖层。
在上述方法中,还包括在回蚀刻所述导电材料之后,在所述导电材料上方沉积覆盖层,还包括平坦化所述覆盖层与所述第一介电材料。
根据又另一实施例,提供了一种制造半导体器件的方法,包括形成多个伪栅极堆叠件,其中,多个伪栅极堆叠件的第一个比多个伪栅极堆叠件的剩余部分具有更大的长度。在多个伪栅极堆叠件周围沉积层间电介质,并且在不替换多个伪栅极堆叠件的第一个的情况下,用介电材料替换多个伪栅极堆叠件的一个。介电材料与层间电介质和多个伪栅极堆叠件的第一个齐平。沿着层间电介质和多个伪栅极堆叠件的顶面在注入区中改变组分的浓度。去除多个伪栅极堆叠件的第一个以形成第一开口,其中,去除多个伪栅极堆叠件的第一个还减小了层间电介质的高度,并且用栅电极材料填充第一开口。使栅电极材料凹进至第一开口内以形成栅电极,并且用覆盖材料填充第一开口的剩余部分。
在上述方法中,还包括平坦化所述覆盖材料与所述层间电介质,其中,平坦化所述覆盖材料与所述层间电介质将所述层间电介质的高度减小至小于50nm。
在上述方法中,其中,改变所述组分的浓度增大了IV族元素的浓度。
在上述方法中,其中,替换所述多个伪栅极堆叠件的一个还减小了邻近所述多个伪栅极堆叠件的一个的第一间隔件的高度。
在上述方法中,其中,替换所述多个伪栅极堆叠件的一个还减小了邻近所述多个伪栅极堆叠件的一个的第一间隔件的高度,其中,替换所述多个伪栅极堆叠件的一个不减小邻近所述第一间隔件的第二间隔件的高度。
在上述方法中,其中,在平坦化所述介电材料与所述层间电介质之后,所述层间电介质具有第一凹陷深度,并且其中,在去除所述多个伪栅极堆叠件的第一个之后,所述层间电介质具有小于所述第一凹陷深度的第二凹陷深度。
上面概述了若干实施例的特征,使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,本文中他们可以做出多种变化、替换以及改变。
Claims (10)
1.一种制造半导体器件的方法,所述方法包括:
沉积第一伪栅极堆叠件和第二伪栅极堆叠件,其中,所述第一伪栅极堆叠件具有第一沟道长度,并且所述第二伪栅极堆叠件具有与所述第一沟道长度不同的第二沟道长度;
在所述第一伪栅极堆叠件和所述第二伪栅极堆叠件周围沉积层间电介质;
平坦化所述第一伪栅极堆叠件、所述第二伪栅极堆叠件和所述层间电介质;
将离子注入所述层间电介质以形成注入区;
去除所述第一伪栅极堆叠件和所述第二伪栅极堆叠件以形成第一开口和第二开口,其中,去除所述第一伪栅极堆叠件和所述第二伪栅极堆叠件减小所述层间电介质的高度;以及
用导电材料填充所述第一开口和所述第二开口。
2.根据权利要求1所述的方法,还包括使所述导电材料凹进至所述第一开口内。
3.根据权利要求2所述的方法,还包括用覆盖材料填充所述第一开口的剩余部分。
4.根据权利要求3所述的方法,还包括平坦化所述覆盖材料和所述层间电介质。
5.根据权利要求1所述的方法,其中,注入所述离子在所述层间电介质中生成四配位基配体。
6.根据权利要求1所述的方法,其中,所述层间电介质具有侧壁,所述侧壁的弯曲角度大于135°。
7.根据权利要求1所述的方法,其中,所述第二沟道长度至少为10nm。
8.一种制造半导体器件的方法,所述方法包括:
形成邻近短沟道伪栅极的第一间隔件,形成邻近长沟道伪栅极的第二间隔件,并且形成邻近第一伪栅极的第三间隔件;
邻近所述第一间隔件和所述第二间隔件沉积第一介电材料;
在不去除所述短沟道伪栅极和所述长沟道伪栅极的情况下,去除所述第一伪栅极以形成第一开口;
用第二介电材料填充所述第一开口;
平坦化所述第二介电材料,其中,平坦化所述第二介电材料暴露所述短沟道伪栅极和所述长沟道伪栅极;
将离子注入所述第一介电材料、所述短沟道伪栅极、所述长沟道伪栅极、所述第一间隔件和所述第二间隔件;
去除所述短沟道伪栅极和所述长沟道伪栅极以形成第二开口;
用导电材料填充所述第二开口;以及
回蚀刻所述导电材料。
9.根据权利要求8所述的方法,其中,所述离子是IV族元素。
10.一种制造半导体器件的方法,所述方法包括:
形成多个伪栅极堆叠件,其中,所述多个伪栅极堆叠件的第一个比所述多个伪栅极堆叠件的剩余部分具有更大的长度;
在所述多个伪栅极堆叠件周围沉积层间电介质;
在不替换所述多个伪栅极堆叠件的第一个的情况下,用介电材料替换所述多个伪栅极堆叠件的一个;
平坦化所述介电材料与所述层间电介质和所述多个伪栅极堆叠件的第一个;
沿着所述层间电介质和所述多个伪栅极堆叠件的顶面改变注入区中的组分的浓度;
去除所述多个伪栅极堆叠件的第一个以形成第一开口,其中,去除所述多个伪栅极堆叠件的第一个还减小所述层间电介质的高度;
用栅电极材料填充所述第一开口;
使所述栅电极材料凹进至所述第一开口内以形成栅电极;以及
用覆盖材料填充所述第一开口的剩余部分。
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