CN108112195A - A kind of manufacturing method of multi-layer circuit board - Google Patents
A kind of manufacturing method of multi-layer circuit board Download PDFInfo
- Publication number
- CN108112195A CN108112195A CN201810064873.7A CN201810064873A CN108112195A CN 108112195 A CN108112195 A CN 108112195A CN 201810064873 A CN201810064873 A CN 201810064873A CN 108112195 A CN108112195 A CN 108112195A
- Authority
- CN
- China
- Prior art keywords
- circuit board
- manufacturing
- etching
- hole
- punching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0502—Patterning and lithography
- H05K2203/052—Magnetographic patterning
Abstract
The invention discloses a kind of manufacturing method of multi-layer circuit board, belong to wiring board technology field, specifically include sawing sheet → punching → pre-treatment → exposure → etching → riveted, the program is to be punched out step on the tabula rasa directly after sawing sheet, on the one hand the hole that perforating press is gone out can be used as target hole, on the other hand the rivet hole of process below is alternatively arranged as, i.e. a hole is mostly used.And subsequent exposure technology is then aligned using the target hole position gone out, in this way, can not only improve the aligning accuracy of exposure machine, can also reduce position aligning time, and then work efficiency is improved, improve product yield.
Description
Technical field
The present invention relates to wiring board technology field, more particularly, to a kind of manufacturing method of multi-layer circuit board.
Background technology
In the manufacturing process of assist side, the process sequence of traditional circuit inner cord punching includes step：Sawing sheet → exposure
→ etching → punching → brown → riveted；There is certain aligning accuracy requirement per step process flow device therefor, it is high-precision
It is unit independently working that contraposition requirement, which needs longer position aligning time and tradition major part, and upstream and downstream procedure connection is carried
Long time period can be generated and artificially scrapped, and production efficiency is relatively low, and yield is affected.In traditional process route, sawing sheet
First exposure technology afterwards, since internal layer tabula rasa does not have any target for exposure machine alignment, so two sides after being exposed above and below core material
Aligning degree it is not high, two sides is there are contraposition deviation after etching, rear process punching, is carried out pair according to the target etched on circuit board
Position, punching is compensated after contraposition.
The content of the invention
The technical problems to be solved by the invention are：Production process of the prior art, wiring board exposure aligning precision is not
Enough, time-consuming for contraposition, influences work efficiency and product yield.
In order to solve the above-mentioned technical problem, the present invention discloses a kind of manufacturing method of multi-layer circuit board, and this method includes following
Step：
S1, sawing sheet carry out sawing sheet processing according to the specification of required multilayer circuit board；
S2, punching are punched out wiring board obtained by sawing sheet, obtain exposure target hole and rivet hole；
S3, pre-treatment, the cleaning treatment before being exposed to the wiring board after punching；
S4, exposure are positioned using the target hole, processing are exposed to wiring board；
S5, etching are etched line pattern in etch process section；
Wiring board riveted of the polylith after etching process is formed multilayer line by S6, riveted using the rivet hole
Plate.
Further, in the S2 punching steps, the target hole is uniformly arranged on the edge of wiring board, target
Hole is also simultaneously as the part rivet hole in follow-up staking step.
Further, in the S2 punching steps, the rivet hole is arranged at the edge of wiring board surrounding, and rivet hole is
Accurately circular hole, and Circularhole diameter is all 3.175mm.
Further, in the S2 punching steps, circuit plate thickness used is 0.075-0.8mm, and punching speed is 8pnl/
Min, punching precision are ± 0.025mm, repeatable accuracy ± 0.013mm.
Further, in the S3 pre-treatment steps, include the wiring board after punching put successively plate → oil removing →
Overflow washing → microetch → overflow washing → drying and processing.
Further, in the S3 pre-treatment steps, processing speed 3.1-4.5m/min, except oil temperature is 25-35 DEG C,
Except oil pressure is 1.5-2.5kg/cm2, washing pressure is 1.3-2.3kg/cm2, microetch temperature is 30-34 DEG C, and microetch pressure is
2.0-2.4kg/cm2。
Further, in the S3 pre-treatment steps, during oil removing, the automatic additive amount of degreaser used is often produces 7500-
8500inch wiring boards plate adds 1400 ± 100mL, and during microetch, the automatic additive amount of micro-corrosion liquid used is often produces 150-
200inch wiring boards add 1400 ± 100mL.
Further, in the S4 step of exposure, exposure energy is 5-8 lattice exposure guide rules, and vacuum strength is -450- (- 350)
MmHg, egative film alignment precision are less than or equal to 30um, air pressure 0.4-0.6MPa, and egative film vacuum degree is less than or equal to -0.7bar.
Further, in the S5 etching steps, → dirt removal water → overflow water is washed including putting plate → development → new liquid successively
Wash → clear water washes → fine etching → sealing washes → overflow washing → clear water is washed → moves back film → new liquid and washes → dirt removal water → overflow water
It washes → clear water is washed → and dries flow.
Further, in the S5 etching steps, during development, developer pressure 1.5-2.1kg/cm2, development temperature 30-34
℃；During etching, 2.6-3.0kg/cm is sprayed on etching pressure2, lower spray 1.5-2.5kg/cm2, 48-52 DEG C of etch temperature, etching used
Liquid medicine is the etching solution that is made of mother liquor, hydrochloric acid and oxidant；When moving back film, film pressure 1.0-2.0kg/cm is moved back2, move back film temperature
40-50℃。
Manufacturing method of multi-layer circuit board disclosed by the invention, including sawing sheet → punching → pre-treatment → exposure → etching → riveting
It closes, key point is：Step is punched out on tabula rasa after sawing sheet, the hole that perforating press is gone out can be used as target hole, with
And the rivet hole of rear process.And subsequent exposure technology is aligned using the target hole position gone out, and can so improve exposure
The aligning accuracy of machine, it is possible to reduce position aligning time improves work efficiency, improves product yield.
Description of the drawings
The particular content of the present invention is described in detail below in conjunction with the accompanying drawings
Fig. 1 is a kind of flow chart of manufacturing method of multi-layer circuit board of the present invention.
Specific embodiment
For the technology contents that the present invention will be described in detail, the objects and the effects, below in conjunction with embodiment and coordinate attached
Figure is explained in detail.
With reference to Fig. 1, the invention discloses a kind of manufacturing method of multi-layer circuit board, this method specifically includes following step successively
Suddenly：
S1, sawing sheet carry out sawing sheet processing according to the specification of required multilayer circuit board；
S2, punching are punched out wiring board obtained by sawing sheet, obtain exposure target hole and rivet hole；
S3, pre-treatment, the cleaning treatment before being exposed to the wiring board after punching；
S4, exposure are positioned using the target hole, processing are exposed to wiring board；
S5, etching are etched line pattern in etch process section；
Wiring board riveted of the polylith after etching process is formed multilayer line by S6, riveted using the rivet hole
Plate.
In the program, multilayer electricity is carried out using the such step of sawing sheet → punching → pre-treatment → exposure → etching → riveted
The making of road plate, the punching technology of the program eliminate alignment system inside original optics, but directly through outer after using sawing sheet
In portion after board device upper plate, plate is sent into inside perforating press by perforating press before system, in being taken using novel precise machinery alignment system
Heart positioning method will feed and position, and is then punched out according to the Tooling confirmed, feed mechanism sends out plate after punching
Next station carries out operation.With regard to carrying out punching step directly on tabula rasa i.e. after sawing sheet, target hole and rivet hole are completed
Subsequent exposure and etching step are carried out again after making.Before punching step is located at step of exposure, so as to be different from the prior art
Middle punching step is located at after etching step, and new scheme causes wiring board when being exposed, and has had thereon corresponding
Target hole, exposure technology are aligned using the target hole and give up traditional alignment mode, so can significantly be mentioned
The aligning accuracy of exposure machine, while the aligning accuracy of subsequent step wiring board is had an effect on, reduce the contraposition of entire production process
Time improves work efficiency, improves product yield.
On the basis of said program, in the S2 punching steps, the target hole is uniformly arranged on the surrounding of wiring board
At edge, and target hole is also simultaneously as the part rivet hole in follow-up staking step.I.e. target hole is when needing contraposition, as target
Mark hole is used, that is, is made inner layer exposure contraposition and be used, and in follow-up staking step, target hole is then used as rivet hole, a hole
It is multi-purpose.And each rivet hole is arranged at the edge of wiring board surrounding, so as to not influence the making of line pattern on wiring board, riveting
Conjunction hole is accurately circular hole, and Circularhole diameter is all 3.175mm.Wherein, target hole can be 4, and rivet hole can be 12 in total.
In addition, in the step, circuit plate thickness used is 0.075-0.8mm, and punching speed is 8pnl/min, punching precision for ±
0.025mm, repeatable accuracy ± 0.013mm.
On the basis of said program, in the S3 pre-treatment steps, include carrying out the wiring board after punching successively automatic
Manipulator puts plate → oil removing → overflow 4 sections → microetch of washing 2 sections → overflow, 5 sections → drying and processing of washing.And processing speed is
3.1-4.5m/min, except oil temperature is 25-35 DEG C, except oil pressure is 1.5-2.5kg/cm2, washing pressure is 1.3-2.3kg/
cm2, microetch temperature is 30-34 DEG C, and microetch pressure is 2.0-2.4kg/cm2.In addition, in oil removing, degreaser used adds automatically
It measures often to produce 7500-8500inch wiring boards plate and adds 1400 ± 100mL, during microetch, the automatic additive amount of micro-corrosion liquid used is
It often produces 150-200inch wiring boards and adds 1400 ± 100mL.
In addition, in the S4 step of exposure, exposure energy is 5-8 lattice exposure guide rules, and vacuum strength is -450- (- 350)
MmHg, egative film alignment precision are less than or equal to 30um, air pressure 0.4-0.6MPa, and egative film vacuum degree is less than or equal to -0.7bar.
Finally, in the S5 etching steps, 2 sections of plate → development → new liquid is put including automatic manipulator successively and wash → dirt removal water
→ overflow wash 7 sections → clear water wash → 3 sections → sealing of fine etching washes → overflow washing 3 sections → clear water is washed → moves back 3 sections of film → new
Liquid washes → and dirt removal water → overflow washing 6 sections → clear water is washed → dries flow.Meanwhile during development, developer pressure 1.5-2.1kg/
cm2, 30-34 DEG C of development temperature；During etching, 2.6-3.0kg/cm is sprayed on etching pressure2, lower spray 1.5-2.5kg/cm2, etching temperature
48-52 DEG C of degree, etching solution used are the etching solution being made of mother liquor, hydrochloric acid and oxidant, such as AET-102；When moving back film, move back
Film pressure 1.0-2.0kg/cm2, move back 40-50 DEG C of film temperature.
Manufacturing method of multi-layer circuit board disclosed by the invention, including sawing sheet → punching → pre-treatment → exposure → etching → riveting
Close and etc., and prior art processes step includes：The flows such as sawing sheet → exposure → etching → punching → brown → riveted, are compared
In the prior art, this programme is punched out step on the tabula rasa after sawing sheet, on the one hand the hole gone out using perforating press can be made
For target hole, the part rivet hole of rear process is on the other hand alternatively arranged as.Meanwhile the target gone out can be used in subsequent exposure technology
Mark hole position is exposed contraposition, so can not only improve the aligning accuracy of exposure machine, can also reduce position aligning time, Jin Erti
High work efficiency, improves final product yield.
The foregoing is merely the embodiment of the present invention, are not intended to limit the scope of the invention, every to utilize this hair
The equivalent process transformation that bright specification and accompanying drawing content are made directly or indirectly is used in other related technical areas,
Similarly it is included within the scope of the present invention.
Claims (10)
1. a kind of manufacturing method of multi-layer circuit board, which is characterized in that comprise the following steps：
S1, sawing sheet carry out sawing sheet processing according to the specification of required multilayer circuit board；
S2, punching are punched out wiring board obtained by sawing sheet, obtain exposure target hole and rivet hole；
S3, pre-treatment, the cleaning treatment before being exposed to the wiring board after punching；
S4, exposure are positioned using the target hole, processing are exposed to wiring board；
S5, etching are etched line pattern in etch process section；
Wiring board riveted of the polylith after etching process is formed multilayer circuit board by S6, riveted using the rivet hole.
2. manufacturing method of multi-layer circuit board as described in claim 1, it is characterised in that：In the S2 punching steps, the target
Mark hole is uniformly arranged on the edge of wiring board, and target hole is also simultaneously as the part rivet hole in follow-up staking step.
3. manufacturing method of multi-layer circuit board as claimed in claim 2, it is characterised in that：In the S2 punching steps, the riveting
The edge that hole is arranged at wiring board surrounding is closed, rivet hole is accurately circular hole, and Circularhole diameter is all 3.175mm.
4. manufacturing method of multi-layer circuit board as claimed in claim 3, it is characterised in that：In the S2 punching steps, line used
Road plate thickness be 0.075-0.8mm, punching speed be 8pnl/min, punching precision be ± 0.025mm, repeatable accuracy ±
0.013mm。
5. manufacturing method of multi-layer circuit board as described in claim 1, it is characterised in that：In the S3 pre-treatment steps, successively
Including carrying out putting plate → oil removing → overflow washing → microetch → overflow washing → drying and processing to the wiring board after punching.
6. manufacturing method of multi-layer circuit board as claimed in claim 5, it is characterised in that：In the S3 pre-treatment steps, processing
Speed is 3.1-4.5m/min, except oil temperature is 25-35 DEG C, except oil pressure is 1.5-2.5kg/cm2, washing pressure is 1.3-
2.3kg/cm2, microetch temperature is 30-34 DEG C, and microetch pressure is 2.0-2.4kg/cm2。
7. manufacturing method of multi-layer circuit board as claimed in claim 6, it is characterised in that：In the S3 pre-treatment steps, oil removing
When, the automatic additive amount of degreaser used adds 1400 ± 100mL often to produce 7500-8500inch wiring boards plates, during microetch, institute
With the automatic additive amount of micro-corrosion liquid 1400 ± 100mL is added often to produce 150-200inch wiring boards.
8. manufacturing method of multi-layer circuit board as described in claim 1, it is characterised in that：In the S4 step of exposure, energy is exposed
It measures as 5-8 lattice exposure guide rules, vacuum strength is -450- (- 350) mmHg, and egative film alignment precision is less than or equal to 30um, air pressure 0.4-
0.6MPa, egative film vacuum degree are less than or equal to -0.7bar.
9. manufacturing method of multi-layer circuit board as described in claim 1, it is characterised in that：In the S5 etching steps, wrap successively
Include put plate → development → new liquid wash → dirt removal water → overflow washing → clear water washes → fine etching → sealing washes → overflow washing →
Clear water wash → move back film → new liquid wash → dirt removal water → overflow washing → clear water is washed → dries flow.
10. manufacturing method of multi-layer circuit board as claimed in claim 9, it is characterised in that：In the S5 etching steps, development
When, developer pressure 1.5-2.1kg/cm2, 30-34 DEG C of development temperature；During etching, 2.6-3.0kg/cm is sprayed on etching pressure2, lower spray
1.5-2.5kg/cm2, 48-52 DEG C of etch temperature, etching solution used is the etching that is made of mother liquor, hydrochloric acid and oxidant
Liquid；When moving back film, film pressure 1.0-2.0kg/cm is moved back2, move back 40-50 DEG C of film temperature.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810064873.7A CN108112195B (en) | 2018-01-23 | 2018-01-23 | Method for manufacturing multilayer circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810064873.7A CN108112195B (en) | 2018-01-23 | 2018-01-23 | Method for manufacturing multilayer circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108112195A true CN108112195A (en) | 2018-06-01 |
| CN108112195B CN108112195B (en) | 2020-07-17 |
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ID=62220349
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810064873.7A Active CN108112195B (en) | 2018-01-23 | 2018-01-23 | Method for manufacturing multilayer circuit board |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110602887A (en) * | 2019-09-17 | 2019-12-20 | 四川深北电路科技有限公司 | Manufacturing method of high-frequency multilayer circuit board |
| CN110958774A (en) * | 2019-12-12 | 2020-04-03 | 苏州市惠利华电子有限公司 | Drilling method for false eight-layer board layer |
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| WO2007109682A3 (en) * | 2006-03-20 | 2008-06-12 | Duetto Integrated Systems Inc | Improved system and method for manufacturing laminated circuit boards |
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| CN107484357A (en) * | 2017-07-20 | 2017-12-15 | 深圳崇达多层线路板有限公司 | A kind of preparation method of the more sheet material nesting tiled mixed-compression boards of asymmetric |
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2018
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007109682A3 (en) * | 2006-03-20 | 2008-06-12 | Duetto Integrated Systems Inc | Improved system and method for manufacturing laminated circuit boards |
| CN102843875A (en) * | 2011-06-21 | 2012-12-26 | 昆山华扬电子有限公司 | Alignment control method for multiple layers of PCBs |
| CN102905471A (en) * | 2012-10-21 | 2013-01-30 | 蔡新民 | Method for manufacturing polytetrafluoroethylene high-frequency circuit board |
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| CN105555046A (en) * | 2015-12-31 | 2016-05-04 | 东莞市优森电子有限公司 | Production technology of double-sided PCB |
| CN107484357A (en) * | 2017-07-20 | 2017-12-15 | 深圳崇达多层线路板有限公司 | A kind of preparation method of the more sheet material nesting tiled mixed-compression boards of asymmetric |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110602887A (en) * | 2019-09-17 | 2019-12-20 | 四川深北电路科技有限公司 | Manufacturing method of high-frequency multilayer circuit board |
| CN110958774A (en) * | 2019-12-12 | 2020-04-03 | 苏州市惠利华电子有限公司 | Drilling method for false eight-layer board layer |
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| Publication number | Publication date |
|---|---|
| CN108112195B (en) | 2020-07-17 |
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