CN107925564B - 用于多相时钟数据恢复电路校准的方法和装置 - Google Patents

用于多相时钟数据恢复电路校准的方法和装置 Download PDF

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CN107925564B
CN107925564B CN201680050195.8A CN201680050195A CN107925564B CN 107925564 B CN107925564 B CN 107925564B CN 201680050195 A CN201680050195 A CN 201680050195A CN 107925564 B CN107925564 B CN 107925564B
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frequency
recovery circuit
clock recovery
clock
signal
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Chinese (zh)
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CN107925564A (zh
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Y·段
C·李
H·丹恩
O·翁
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Qualcomm Inc
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Qualcomm Inc
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4917—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes
    • H04L25/4923—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes using ternary codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/003—Arrangements for allocating sub-channels of the transmission path
    • H04L5/0048—Allocation of pilot signals, i.e. of signals known to the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/08—Speed or phase control by synchronisation signals the synchronisation signals recurring cyclically
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Power Engineering (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Information Transfer Systems (AREA)
  • Pulse Circuits (AREA)
CN201680050195.8A 2015-09-01 2016-08-09 用于多相时钟数据恢复电路校准的方法和装置 Active CN107925564B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202011577819.6A CN112751660B (zh) 2015-09-01 2016-08-09 用于多相时钟数据恢复电路校准的方法和装置

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/842,610 2015-09-01
US14/842,610 US9485080B1 (en) 2015-09-01 2015-09-01 Multiphase clock data recovery circuit calibration
PCT/US2016/046208 WO2017039984A1 (en) 2015-09-01 2016-08-09 Multiphase clock data recovery circuit calibration

Related Child Applications (1)

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CN202011577819.6A Division CN112751660B (zh) 2015-09-01 2016-08-09 用于多相时钟数据恢复电路校准的方法和装置

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CN107925564A CN107925564A (zh) 2018-04-17
CN107925564B true CN107925564B (zh) 2020-12-29

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CN202011577819.6A Active CN112751660B (zh) 2015-09-01 2016-08-09 用于多相时钟数据恢复电路校准的方法和装置

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US (1) US9485080B1 (enExample)
EP (2) EP3345333B1 (enExample)
JP (2) JP7027307B2 (enExample)
KR (1) KR102523235B1 (enExample)
CN (2) CN107925564B (enExample)
BR (1) BR112018004151B1 (enExample)
CA (1) CA2992750A1 (enExample)
ES (1) ES2794527T3 (enExample)
HU (1) HUE049096T2 (enExample)
TW (1) TWI699974B (enExample)
WO (1) WO2017039984A1 (enExample)

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US10419246B2 (en) * 2016-08-31 2019-09-17 Qualcomm Incorporated C-PHY training pattern for adaptive equalization, adaptive edge tracking and delay calibration
US10033519B2 (en) * 2016-11-10 2018-07-24 Qualcomm Incorporated C-PHY half-rate clock and data recovery adaptive edge tracking
US10284361B2 (en) 2017-05-05 2019-05-07 Mediatek Inc. Channel skew calibration method and associated receiver and system
US10298381B1 (en) * 2018-04-30 2019-05-21 Qualcomm Incorporated Multiphase clock data recovery with adaptive tracking for a multi-wire, multi-phase interface
US10333690B1 (en) 2018-05-04 2019-06-25 Qualcomm Incorporated Calibration pattern and duty-cycle distortion correction for clock data recovery in a multi-wire, multi-phase interface
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US11108604B2 (en) * 2019-08-19 2021-08-31 Qualcomm Incorporated Driver architecture for multiphase and amplitude encoding transmitters
US11095425B2 (en) 2019-10-25 2021-08-17 Qualcomm Incorporated Small loop delay clock and data recovery block for high-speed next generation C-PHY
US11240077B2 (en) * 2019-10-29 2022-02-01 Qualcomm Incorporated C-PHY half-rate wire state encoder and decoder
US11038666B1 (en) * 2019-12-11 2021-06-15 Qualcomm Incorporated Open-loop, super fast, half-rate clock and data recovery for next generation C-PHY interfaces
US11327914B1 (en) * 2021-01-29 2022-05-10 Qualcomm Incorporated C-PHY data-triggered edge generation with intrinsic half-rate operation
CN113114190B (zh) * 2021-04-08 2024-02-06 格科微电子（上海）有限公司 时钟恢复电路及方法、数据处理芯片、电子设备
JP7712138B2 (ja) * 2021-08-04 2025-07-23 株式会社アドバンテスト 装置
TWI769046B (zh) * 2021-08-10 2022-06-21 瑞昱半導體股份有限公司 具有頻率校正機制的訊號中繼裝置及方法
CN113886300B (zh) * 2021-09-23 2024-05-03 珠海一微半导体股份有限公司 一种总线接口的时钟数据自适应恢复系统及芯片
CN113886315B (zh) * 2021-09-23 2024-05-03 珠海一微半导体股份有限公司 一种时钟数据恢复系统、芯片及时钟数据恢复方法
US11967964B1 (en) * 2022-03-31 2024-04-23 Amazon Technologies, Inc. Clock synchronization in a network using a distributed pulse signal
CN115903998B (zh) * 2022-11-11 2025-08-26 深圳天德钰科技股份有限公司 校准方法、电路、存储介质、时钟恢复电路及电子装置
CN116825170B (zh) * 2023-08-31 2023-11-07 芯砺智能科技(上海)有限公司 晶粒到晶粒互连的自动校准架构和芯片
CN117056269B (zh) * 2023-10-11 2024-02-09 芯耀辉科技有限公司 用于并行接口连接的数据对齐方法、计算机设备及介质

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Also Published As

Publication number Publication date
JP2018529284A (ja) 2018-10-04
BR112018004151A2 (pt) 2018-10-02
JP7258199B2 (ja) 2023-04-14
JP2022075665A (ja) 2022-05-18
EP3345333B1 (en) 2020-03-18
CN112751660B (zh) 2024-03-08
CA2992750A1 (en) 2017-03-09
JP7027307B2 (ja) 2022-03-01
EP3345333A1 (en) 2018-07-11
BR112018004151B1 (pt) 2023-12-12
KR20180048950A (ko) 2018-05-10
US9485080B1 (en) 2016-11-01
TW201711388A (zh) 2017-03-16
CN112751660A (zh) 2021-05-04
EP3678323B1 (en) 2022-06-08
TWI699974B (zh) 2020-07-21
ES2794527T3 (es) 2020-11-18
EP3678323A1 (en) 2020-07-08
HUE049096T2 (hu) 2020-09-28
KR102523235B1 (ko) 2023-04-18
CN107925564A (zh) 2018-04-17
WO2017039984A1 (en) 2017-03-09

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