CN107924874B - 复合型半导体装置 - Google Patents

复合型半导体装置 Download PDF

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CN107924874B
CN107924874B CN201680045947.1A CN201680045947A CN107924874B CN 107924874 B CN107924874 B CN 107924874B CN 201680045947 A CN201680045947 A CN 201680045947A CN 107924874 B CN107924874 B CN 107924874B
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gate
semiconductor device
normally
terminal
electrode
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CN107924874A (zh
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木原诚一郎
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Rohm Co Ltd
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Rohm Co Ltd
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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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  • Semiconductor Integrated Circuits (AREA)

Abstract

提供一种抑制了布线面积的增大的同时,改善了应答性能及可靠性的复合型半导体装置。指状电极1配置成多行多列,经由栅极端子(3)输入的信号,从与指状电极1中、同一行或相邻的两行的指状电极1的各个栅极电极(G)连接且沿上述行形成的栅极布线(18)的上述行方向上的中间区域被供给。

Description

复合型半导体装置
技术领域
本发明涉及一种包含半导体装置和常导通型(normally-on type)场效应晶体管的复合型半导体装置,所述半导体装置具备多个常断开型(normally-off type)场效应晶体管。
背景技术
在目前的半导体装置中主要使用的Si(硅)系场效应晶体管是常断开型的。常断开型场效应晶体管是一种在向栅极电极(G)和源极电极(S)之间施加正电压时导通,在栅极电极(G)和源极电极(S)之间未施加正电压时成为非导通的晶体管。作为该常断开型场效应晶体管的实现方法之一,存在一种横向双扩散MOS场效应晶体管(LDMOSFET:The LateralDouble-Diffused MOS field effect transistor)。该横向双扩散MOS场效应晶体管具有如下特征:源极电极(S)和漏极电极(D)形成在半导体基板的同一面上,并且,能够通过从源极电极(S)贯穿半导体之中的沟槽而与位于半导体背面的电极连接。
另一方面,为了具备高耐压、低损耗、高速切换以及高温运行等特征而正在推进实用化研究的GaN等III-N型场效应晶体管则是常导通型的。常导通型场效应晶体管具有负的阈值电压,在栅极电极(G)和源极电极(S)之间的电压较阈值电压低时成为非导通,在栅极电极(G)和源极电极(S)之间的电压较阈值高时导通。如果在半导体装置中使用这种常导通型场效应晶体管的话,将会产生无法使用现有的栅极驱动电路等诸多问题。
因此,在下述专利文献1中,提出了一种将常导通型场效应晶体管与常断开型场效应晶体管串联连接来构成常断开型的复合型半导体装置的方案。此外,在下述专利文献2中,为了防止因常断开型场效应晶体管的漏极电极(D)和源极电极(S)之间的电压升高而导致上述常断开型场效应晶体管遭到破坏,提出了一种在上述常断开型场效应晶体管的漏极电极(D)和源极电极(S)之间连接稳压二极管,并将漏极电极(D)和源极电极(S)之间的电压限制在上述常断开型场效应晶体管的耐压以下的方法。在下述专利文献3中,提出了一种通过与栅极电极分流用基板布线连接来降低栅极电阻的方法。在下述专利文献4中,记载了一种使介于功率MOSFET的栅极电极和n+型漏极区域之间的偏位(offset)漏极区域成为双偏位结构,并使导通电阻(Ron)和反馈电容(Cgd)均降低的结构。在下述专利文献5中,记载了一种用于抑制源/漏极布线电阻的上升,实现栅极布线的低电阻化的方法。下述专利文献6中,记载了一种通过改良栅极布线图案、有效利用芯片面积来增加有效单元的数量或者使芯片面积能够得到减小的结构。
现有技术文献
专利文献
专利文献1:日本国公开专利公报“特开2006-158185号公报(2006年6月15日公开)”
专利文献2:日本国公开专利公报“特开2006-324839号公报(2006年11月30日公开)”
专利文献3:日本国公开专利公报“特开2012-244039号公报(2012年12月10日公开)”
专利文献4:日本国公开专利公报“特开2010-171433号公报(2010年8月5日公开)”
专利文献5:日本国公开专利公报“特开2010-123774号公报(2010年6月3日公开)”
专利文献6:日本国公开专利公报“平8-181307号公报(1996年7月12日公开)”
发明内容
本发明所要解决的技术问题
但是,上述现有的常断开型的复合型半导体装置所具备的常断开型的半导体装置在大多的情形是由被称为指状电极(finger)的小型常断开型场效应晶体管的集合体构成的。其中每一个指状电极的栅极电极(G)通过金属布线与上述常断开型半导体装置的栅极端子连接。因此,与被传输到配置在上述常断开型半导体装置的栅极端子附近的指状电极的栅极电极上的栅极信号相比,被传输到配置在上述常断开型半导体装置的栅极端子所在边的相反侧的指状电极的栅极电极上的栅极信号将会大大延迟。由此,导致了复合型半导体装置应答性能的降低。此外,在这种情形下,容易产生因电力集中到特定的常断开型场效应晶体管所导致的破坏,因此,作为复合型半导体装置的可靠性也存在问题。
在上述专利文献1和2所公开的结构中,会产生应答性能降低的问题以及可靠性的问题。
在上述专利文献3至6所公开的结构中,虽然对降低栅极布线的电阻这一点有所关注,但对于抑制因晶体管相对于栅极端子的配置位置而导致的经由栅极端子输入的信号的传输延迟的偏差这一点并未特别关注,因此并不足以改善应答性能降低的问题以及可靠性的问题。
本发明的目的在于提供一种抑制了布线面积的增大的同时,改善了应答性能及可靠性的复合型半导体装置。
解决问题的手段
为了解决上述问题,本发明的复合型半导体装置包含多个常断开型场效应晶体管,且包含具备栅极端子、漏极端子及源极端子的半导体装置、常导通型场效应晶体管、第2栅极端子、第2漏极端子以及第2源极端子,其特征在于,在上述多个常断开型场效应晶体管的各者中,栅极电极与上述栅极端子连接,漏极电极与上述漏极端子连接,源极电极与上述源极端子连接,在上述半导体装置中,上述栅极端子、与上述漏极端子及上述源极端子中的任一者形成在第1面上,上述漏极端子及上述源极端子中的另一者形成在上述第1面的背面即第2面上,上述第2漏极端子与上述常断开型场效应晶体管的漏极电极连接,上述第2源极端子与上述常断开型场效应晶体管的栅极电极以及上述半导体装置的源极端子连接,上述第2栅极端子与上述半导体装置的栅极端子连接,上述常断开型场效应晶体管的源极电极与上述半导体装置的漏极端子连接,上述多个常断开型场效应晶体管配置成多行多列,经由上述栅极端子输入的信号,从与上述多个常断开型场效应晶体管中、同一行或相邻的两行的场效应晶体管的各个栅极电极连接且沿上述行形成的栅极布线的上述行方向上的中间区域被供给。
根据上述结构,上述多个常断开型场效应晶体管配置成多行多列,经由上述栅极端子输入的信号,从与上述多个常断开型场效应晶体管中、同一行或相邻的两行的场效应晶体管的各个栅极电极连接且沿上述行形成的栅极布线的上述行方向上的中间区域被供给,因此,能够抑制因布线电阻的影响,由上述多个常断开型场效应晶体管的配置位置所导致的经由上述栅极端子输入的信号的传输延迟的偏差,同时能够防止因电力集中到特定的常断开型场效应晶体管而导致的破坏,因此能够实现抑制了布线面积的增大的同时,改善了应答性能及可靠性的复合型半导体装置。
发明效果
根据本发明的一个实施例,能够实现抑制了布线面积的增大的同时,改善了应答性能及可靠性的复合型半导体装置。
附图说明
图1是表示本发明的实施方式1所涉及的复合型半导体装置所具备的包含常断开型指状电极的半导体装置的概略结构的电路图。
图2是从形成有栅极端子的面方向观察图1所示的半导体装置的图。
图3是表示图1所示的半导体装置所具备的常断开型指状电极的概略结构的图,其中,(a)是指状电极的俯视图,(b)是指状电极的剖视图。
图4是表示图1所示的半导体装置所具备的多个单元块的图。
图5是表示评价电路的概略结构的电路图,该评价电路用于评价图1所示的半导体装置的动作。
图6是表示图1所示的半导体装置的动作时机的图。
图7是具备半导体装置和常导通型场效应晶体管的复合型半导体装置的电路图,所述半导体装置具备图1所示的常断开型指状电极。
图8是表示图7所示的复合型半导体装置的概略结构的图。
图9是从形成有栅极端子的面方向观察本发明的实施方式2所涉及的复合型半导体装置所具备的半导体装置的图。
图10是表示本发明的实施方式3所涉及的复合型半导体装置所具备的半导体装置中的由多个常断开型指状电极构成的单元块的一部分的图。
图11是表示本发明的实施方式4所涉及的复合型半导体装置所具备的半导体装置中的由多个常断开型指状电极构成的单元块的一部分的图。
具体实施方式
以下,根据附图对本发明的实施方式进行详细说明。但是,这些实施方式中记载的结构的尺寸、材质、形状、相对位置、加工方法等只不过是一种实施方式,不应用它们来限定解释本发明的范围。另外,附图为示意图,其尺寸比例和形状与实物不同。
若根据图1至图11对本发明的实施方式进行说明则如以下。
[实施方式1]
以下,针对本发明的一实施方式,根据图1至图8进行说明。
图1是表示复合型半导体装置40所具备的包含常断开型指状电极1的半导体装置30的概略结构的电路图。
如图所示,常断开型半导体装置(常断开型横向场效应晶体管)30包含配置成5行×2n列的小型场效应晶体管即5×2n个常断开型指状电极1、漏极端子2、栅极端子3、源极端子4以及稳压二极管5。另外,上述n只要是2以上的自然数即可,而在本实施方式中,以n为1000的情形为例进行说明。
图2是从形成有栅极端子3的面方向观察图1所示的常断开型半导体装置30的图。
如图所示,在常断开型半导体装置30中,作为指状电极1的集合体的块17配置在图中左侧,稳压二极管5以与块17相邻的方式配置在图中右侧。
漏极端子2形成为外露于块17的最上部,栅极端子3经由设置在漏极端子2的中央部的漏极端子开口部20而外露。漏极端子2和栅极端子3由同一层形成,利用以包围栅极端子3的方式形成的绝缘层(未图示)的横向厚度来确保漏极端子2与栅极端子3之间的电绝缘。
(指状电极)
如图1所示,由于常断开型半导体装置(常断开型横向场效应晶体管)30是常断开型的,因此指状电极1为常断开型的小型场效应晶体管,其具备栅极电极(G)、漏极电极(D)以及源极电极(S)。常断开型半导体装置30具备这一被称为指状电极1的小型场效应晶体管的集合体(块17)。另外,指状电极1的个数n根据电流容量而为几千至几万,且构成几千至几万个指状电极的集合体(块)是很一般的。
在本实施方式中,以常断开型半导体装置30具备沿行方向及列方向配置成5行×2000列的5×2000个指状电极1的集合体(块17)的情形为例进行说明,但如上所述,指状电极1的个数并不限于此,而由于常断开型半导体装置30是常断开型的横向场效应晶体管,因此列数较行数多。
另外,(1,1)至(5,2n)的指状电极1的源极电极(S)必须如后文所述那样与配置在背面的源极端子4连接。因此,指状电极1优选具有横向双扩散MOS场效应晶体管(LSMOSFET:The Lateral Double-Diffused MOS field effect transistor)的结构,在本实施方式中,指状电极1即为横向双扩散MOS场效应晶体管。这是由于横向双扩散MOS场效应晶体管具有源极电极和漏极电极形成在半导体基板的相同面的特征,但能够进而通过从源极电极贯穿半导体之中的沟槽而与位于半导体背面的电极连接。
图3是表示图1所示的半导体装置30所具备的常断开型指状电极1的概略结构的图,其中,图3的(a)是指状电极1的俯视图,图3的(b)是指状电极1在图的3(a)中的A-A线的剖视图。
如图3的(a)及图3的(b)所图示,块17中所包含的各个指状电极1例如可以具有如以下的结构。
在指状电极1所具备的P++型Si系基板(P++sub)的上表面上,形成有P型外延层(P-epi)作为半导体区域。而且,在P型外延层(P-epi)的上部,P型主体区域(PB)与n型扩散层(nhv)形成在相分开的位置上,由P型主体区域(PB)和n+层(n+)形成指状电极1的源极区域,由n型扩散层(nhv)和n+层(n+)形成指状电极1的漏极区域。
如图3的(b)所图示,包含源极电极(S)的源极布线23经由贯通孔(通孔(through-hole))而与上述源极区域及P++型Si系基板(P++sub)连接,因此,源极布线23也与形成在P++型Si系基板(P++sub)下表面的基板电极即源极端子4连接。另一方面,包含漏极电极(D)的漏极布线24经由贯通孔(通孔)而与上述漏极区域连接,并且经由漏极接点(漏极通孔)25也与漏极端子2(又称漏极垫)连接。而且,如图3的(a)所图示,指状电极1的多晶硅栅极22经由栅极接点(栅极通孔)21而与包含栅极电极(G)的栅极布线18连接。
另外,包含栅极电极(G)的栅极布线18、包含源电极(S)的源极布线23以及包含漏电极(D)的漏极布线24形成在同一层上,漏极端子2和此处未图示的栅极端子3形成在同一层上,栅极端子3存在于漏极端子2的漏极端子开口部20中的一部分。而且,此处未图示的栅极端子3、与栅极布线18或者后述的栅极布线的干布线19(未图示)经由未图示的贯通孔(通孔)连接。
此外,由于上述图1是用来表示栅极端子3与指状电极1的栅极电极(G)的相对位置关系及其电连接关系的电路图,因此以在同一行的各个指状电极1的栅极电极(G)连接一条栅极布线18的方式简略化地图示,而在本实施方式中,如图3的(a)所图示,在同一行的各个指状电极1的栅极电极(G)连接两条栅极布线18,这些栅极布线18在相邻的两行上成为共通的栅极布线。然而并不限定于此,也可以在同一行的各个指状电极1的栅极电极(G)连接一条栅极布线18。
(常断开型半导体装置的栅极端子)
虽能够通过使常断开型半导体装置的栅极端子与各个指状电极的栅极电极之间的布线距离为等距离来解决因布线电阻的偏差的影响而产生的信号传输延迟的偏差的问题,但要使布线距离为等距离的话,将会导致布线面积的增大而不切实际。
因此,在本实施方式中,采用了如以下说明的配置,该配置能够使常断开型半导体装置的栅极端子3与各个指状电极1的栅极电极(G)之间的布线距离的偏差为最小,并且能够在不使布线面积增大之下抑制信号的传输延迟的偏差。
如图1所图示,常断开型半导体装置30的栅极端子3与(1,1)至(5,2n)中的各个指状电极1的栅极电极(G)连接。而且,例如为了使栅极端子3与(3,n)这一指状电极1的栅极电极(G)之间的布线电阻、和栅极端子3与(1,1)这一指状电极1的栅极电极(G)之间的布线电阻的差变小,如图2及图3所示,在本实施方式中,为了能够从与配置成5行×2n列的指状电极1中、同一行的指状电极1(例如(1,1)至(1,2n)的指状电极1)或者相邻的两行的指状电极1(例如(1,1)至(2,2n)的指状电极1)中的各个栅极电极(G)连接且沿行方向形成的各个栅极布线18的上述行方向上的中间区域供给经由栅极端子3输入的信号,而将栅极端子3配置在配置成5行×2n列的指状电极1的集合体(块17)的中央区域,并且使用栅极布线的干布线19,将栅极端子3与各栅极布线18的上述行方向上的中间区域进行了连接。
通过将栅极端子3配置在指状电极1的集合体(块17)的中央区域,能够抑制因指状电极1的栅极电极(G)与栅极端子3之间的距离差所产生的布线电阻的差。此外,还能够通过提供从栅极布线18的上述行方向上的中间区域经由栅极端子3输入的信号,来抑制因同一行中的、指状电极1的栅极电极(G)与经由栅极端子3输入的信号的供应开始点之间的距离的差所产生的信号的传输延迟的偏差。
另外,栅极布线18的上述行方向上的中间区域是指在如本实施方式那样在1行配置有2000个指状电极1的情形下,在第1000个指状电极1与第1001个指状电极1之间,例如(1,n)这一指状电极1与(1,n+1)这一指状电极1之间所存在的栅极布线18。
此外,配置成5行×2n列的指状电极1的集合体(块17)的中央区域是指在如本实施方式那样指状电极1配置成5行×2000列的情形下,(3,n)这一指状电极1与(3,n+1)这一指状电极1之间的区域。
根据上述结构,能够在抑制布线面积的增大的同时,抑制因布线电阻的影响而在多个指状电极1间产生的经由栅极端子3输入的信号的传输延迟的偏差,并且能够防止电力集中到特定的指状电极1而导致的损坏,因此能够实现改善了应答性能及可靠性的半导体装置30以及具备半导体装置30的复合型半导体装置40。
(常断开型半导体装置的漏极端子及源极端子)
如图1所图示,(1,1)至(5,2n)的各个指状电极1的漏极电极(D),与常断开型半导体装置30的漏极端子2连接。另一方面,(1,1)至(5,2n)的各个指状电极1的源极电极(S),与常断开型半导体装置30的源极端子4连接。
(稳压二极管)
如图1所图示,于常断开型半导体装置30有时会有被施加其耐压以上的电压的情形,于该情形下,为了防止故障,常断开型半导体装置30具备稳压二极管5。稳压二极管5的阳极电极(A)与源极端子4连接,阴极电极(C)与漏极端子2连接。稳压二极管5由于受上述布线电阻的影响小,因此无需特别考虑其配置位置,在本实施方式中,如图2所图示,配置在指状电极1的集合体(块17)的外侧。
(块)
图4是表示构成块17的单元块29的一部分的俯视图,所述块17是集成5×2000个指状电极1而成的。
在本实施方式中,单元块29由1000个指状电极1构成,块17由10个单元块29构成。
以下,根据图5及图6针对常断开型半导体装置30的动作进行说明。
(评价电路)
图5是表示评价电路的概略结构的电路图,该评价电路用于评价图1所示的常断开型半导体装置30的动作。
如图所示,评价电路包含常断开型半导体装置30、脉冲发生器13、终端电阻14、负载电阻15及电源16。脉冲发生器13的一端接地,脉冲发生器13的另一端则与一端接地的终端电阻14的另一端连接,并与常断开型半导体装置30的栅极端子3连接。常断开型半导体装置30的漏极端子2与负载电阻15的一端连接,负载电阻15的另一端则与一端接地的电源16的+端子连接。常断开型半导体装置30的源极端子4接地。
(关于常断开型半导体装置的动作)
一般在常断开型半导体装置中,由于布线电阻的影响,而断开的延迟时间(从V(栅极端子)成为低电平的时刻起至V(漏极端子)成为高电平的时刻为止的时间)有比导通的延迟时间(从V(栅极端子)成为高电平的时刻起至V(漏极端子)成为低电平的时刻为止的时间)变得更长的倾向。
而且,在由几千至几万个指状电极构成的一般的常断开型半导体装置中,为了断开的延迟时间的减少,布线电阻的降低是必要的,必须要有不会电流集中到布线电阻格外高的特定的指状电极上而破坏特定的指状电极的那样的对策。
因此,在本实施方式的常断开型半导体装置30中,以能够从与配置成5行×2n列的指状电极1中、同一行(例如(1,1)至(1,2n)的指状电极1)或相邻的两行的指状电极1(例如(1,1)至(2,2n)的指状电极1)的各个栅极电极(G)连接且沿行方向形成的各个栅极布线18的上述行方向上的中间区域供给经由栅极端子3输入的信号的方式,将栅极端子3配置在配置成5行×2n列的指状电极1的集合体(块17)的中央区域,并使用栅极布线的干布线19将栅极端子3与各栅极布线18的上述行方向上的中间区域进行了连接。
图6是表示图1所示的常断开型半导体装置30的动作时机的图。
图6所图示的各电压示出了图1所示的常断开型半导体装置30的点A、点F及点G的电压变化。V(栅极端子)表示常断开型半导体装置30的栅极端子3的电压,V(点A)表示图1中的点A的电压,V(点F)表示图1中的点F的电压,V(点G)表示图1中的点G的电压,V(漏极端子)表示常断开型半导体装置30的漏极端子2的电压。
如V(栅极端子)所示,当常断开型半导体装置30导通时的栅极电压以上的电压(高电平)被输入到栅极端子3时,首先,会如图中V(点A)所示,受到最小布线电阻的影响而延迟,从而最接近栅极端子3的(3,n)这一指状电极1成为导通时的栅极电压以上的电压(高电平)将会被输入到(3,n)这一指状电极的栅极电极(G)。当最接近栅极端子3的(3,n)这一指状电极1导通时,会有电流流动于常断开型半导体装置30,因此其会出现在V(漏极端子)上,V(漏极端子)在最接近栅极端子3的(3,n)这一指状电极1导通的时刻从高电平变成低电平。
之后,受到与距栅极端子3的距离相应的布线电阻的影响而依序延迟,相应的指状电极1导通时的栅极电压以上的电压(高电平)将被输入到相应的指状电极1的栅极电极(G)。然后,如图中V(点F)所示,在(1,2)这一指状电极1导通时的栅极电压以上的电压(高电平)被输入到(1,2)这一指状电极1的栅极电极(G)之后,将会如V(点G)所示,受到最大布线电阻的影响而延迟,从而距栅极端子3最远的(1,1)这一指状电极1导通时的栅极电压以上的电压(高电平)将被输入到(1,1)这一指状电极1的栅极电极(G)。另外,由于在这些的各时刻中,V(漏极端子)已经由高电平变成低电平,因此在这些时刻中,V(漏极端子)上并不会出现电压变化,而维持低电平。
另外,虽然作为受到最大布线电阻的影响的、配置在距栅极端子3最远的位置上的指状电极1,以(1,1)这一指状电极1为例进行了说明,但在本实施方式中,由于(1,1)这一指状电极1、(1,2n)这一指状电极1、(5,1)这一指状电极1以及(5,2n)这一指状电极1距栅极端子3的距离相等,因此毋庸置疑其等均受到最大布线电阻的影响。
如图中V(栅极端子)所示,在常断开型半导体装置30导通时的栅极电压以上的电压(高电平)被输入到栅极端子3一定时间后,恢复成低电平时,如图中V(点A)所示,因布线电阻的影响而延迟,(3,n)这一指状电极1将会断开,但由于其他指状电极1仍处于导通状态,因此其电流变化不会出现在V(漏极端子)。随着时间的经过,其他指状电极1同样因布线电阻的影响而延迟而依序断开,在(1,2)这一指状电极1断开后,最终(1,1)这一指状电极将会断开,但直到(1,1)这一指状电极1断开为止,V(漏极端子)都会维持低电平,在(1,1)这一指状电极1断开的时刻,V(漏极端子)变成高电平。
根据上述结构,能够在不使布线面积增大之下抑制因布线电阻的影响而在多个指状电极1间产生的经由栅极端子3输入的信号的传输延迟的偏差,并且能够防止因电力集中到特定的指状电极1而导致的破坏,因此能够实现改善了应答性能及可靠性的半导体装置30。
(常断开型的复合型半导体装置)
图7是表示复合型半导体装置40的概略结构的电路图。
如图所示,常断开型的复合型半导体装置40具备常断开型半导体装置30、常导通型场效应晶体管31、漏极端子32、栅极端子33及源极端子34。
常导通型场效应晶体管31的漏极电极(D)与复合型半导体装置40的漏极端子32连接,常导通型场效应晶体管31的栅极电极(G)与复合型半导体装置40的源极端子34连接,常导通型场效应晶体管31的源极电极(S)与横向场效应晶体管20的漏极端子2连接。
而且,常断开型半导体装置30的栅极端子3与复合型半导体装置40的栅极端子33连接,常断开型半导体装置30的源极端子4与复合型半导体装置40的源极端子34连接。另外,复合型半导体装置40的源极端子34分别与常导通型场效应晶体管31的栅极电极(G)以及常断开型半导体装置30的源极端子4连接。
在复合型半导体装置40中,由于耐压控制由常导通型场效应晶体管31进行,电流控制由常断开型场效应晶体管、具体来讲是由常断开型半导体装置30来进行,因此常断开型半导体装置30的断开的延迟时间是决定复合型半导体装置40中的断开的延迟时间的最大因素。
在复合型半导体装置40中,由于使用了能够在不使布线面积增大之下抑制因布线电阻的影响而在多个指状电极1间产生的经由栅极端子3输入的信号的传输延迟的偏差,并且能够抑制电力集中到特定的指状电极1而导致的破坏的、改善了应答性能及可靠性的半导体装置30,因此能够实现改善了应答性能及可靠性的半导体装置40。
图8是表示已封装化的复合型半导体装置40的概略结构的图。
如图所示,形成在Si系基板上的常断开型半导体装置30、和形成在GaN等III-N系基板上的常导通型场效应晶体管31接合(die bond)在复合型半导体装置40所具备的芯片垫41上。
常导通型场效应晶体管31的栅极电极(G)与一端为复合型半导体装置40的源极端子34的芯片垫41通过第1引线45连接,常断开型半导体装置30的栅极端子3与复合型半导体装置40的栅极端子33通过第2引线46连接,常断开型半导体装置30的漏极端子2与常导通型场效应晶体管31的源极电极(S)通过第3引线47连接,常导通型场效应晶体管31的漏极电极(D)与复合型半导体装置40的漏极端子32通过第4引线48连接,在常断开型半导体装置30中,通过沟槽而与源极布线连接的形成于芯片背面的基板电极即源极端子4(未图示)与芯片垫41连接。
将漏极端子32、栅极端子33及源极端子34这3个端子的一部分以封装体49密封而构成复合型半导体装置40。
另外,如果对较薄的金属层进行引线接合,则金属层恐将被穿破,因此在本实施方式中,包括常断开型半导体装置30的漏极端子2及栅极端子3在内的需要进行引线接合之处的金属层,是通过也被称为强力金属(power metal)的较厚金属层来形成。
另外,由于流过常导通型场效应晶体管31的电流流经第3引线47和第4引线48,因此常导通型场效应晶体管31的背面主要被使用于固定芯片,其通过导电性材料而与芯片垫41相固定,但也可以通过绝缘物而与芯片垫41相固定。
此外,由于在GaN等III-N系基板上形成的常导通型场效应晶体管31,与在Si系基板上形成的常断开型半导体装置30相比,其单位面积的导通电阻低,因此当两个场效应晶体管为相同尺寸的情形时,常导通型场效应晶体管31能够比常断开型半导体装置30流过更大的电流。
为了将常导通型场效应晶体管31和常断开型半导体装置30的两个芯片接合于芯片垫41并且确保引线的形成空间,且使在Si系基板上形成的常断开型半导体装置30能够流过较大的电流,如图8所示,将两个芯片均形成为长方形的形状在面积上是效率最高的。
复合型半导体装置40由于具备长方形形状的常导通型场效应晶体管31及常断开型半导体装置30,因此在常断开型半导体装置30能够流过较大的电流,并且能够实现面积上效率佳的配置。
此外,复合型半导体装置40由于在常断开型半导体装置30中内置有稳压二极管5,因此当常断开型半导体装置30被施加其耐压以上的电压的情形时,能够防止发生故障。
在本实施方式中,虽以常导通型场效应晶体管31的栅极电极(G)与漏极电极(D)以及源极电极(S)形成在同一面上的情形为例进行了说明,但并不限定于此,例如,也可以是常导通型场效应晶体管31的栅极电极(G)及漏极电极(D)形成在同一面(上表面),而常导通型场效应晶体管31的源极电极(S)形成在上述同一面的背面(下表面)。在这种情形下,优选为:常断开型半导体装置30的栅极端子3及源极端子4形成在同一面(上表面),漏极端子2形成在上述同一面的背面(下表面)。
另外,在对复合型半导体装置40要求高的耐压的情形时,复合型半导体装置40所具备的常导通型场效应晶体管31需要有高的耐压和低的导通电阻,因此常导通型场效应晶体管31的尺寸有增大的倾向。
此外,在常断开型半导体装置30上需要有较大面积的漏极电极(D)用来与常导通型场效应晶体管31的源极电极(S)连接,并且为了防止故障而需要高阈值电压和低导通电阻。
一般在具备有常断开型半导体装置和常导通型场效应晶体管的常断开型的复合型半导体装置中,存在有常断开型半导体装置的漏极电极与源极电极间的电压升高的现象,与仅由常断开型场效应晶体管构成的其他设备相比,导通时的电力要更高,当常断开型半导体装置中的各个指状电极的一部分先导通时,会产生因电力集中而产生的热破坏。
在本实施方式的复合型半导体装置40中,由于使用了能够在不使布线面积增大之下抑制因电力集中到特定的指状电极1上而导致的破坏的改善了可靠性的半导体装置30,因此能够实现改善了可靠性的复合型半导体装置40。
另外,在本实施方式中,虽以横向场效应晶体管为例进行了说明,但本发明不仅适用于横向场效应晶体管,而且也能够普遍适用于所有场效应晶体管。
[实施方式2]
接下来,根据图9针对本发明的实施方式2进行说明。在本实施方式中的常断开型半导体装置30a中,在栅极端子3配置于块17外侧的这一点上是与实施方式1不同,其他方面则如实施方式1中已说明。为了便于说明,对于具有与实施方式1的附图中所示的部件相同功能的部件,标记相同符号并省略其说明。
图9是从形成有栅极端子3的面方向观察常断开型半导体装置30a的图。
如图所示,在常断开型半导体装置30a中,栅极端子3配置在块17的外侧。而且,常断开型半导体装置30a具备与各个栅极布线18的行方向上的中间区域连接且沿上述列方向形成的一条栅极布线的干布线19a、以及沿栅极布线18形成且连接栅极布线的干布线19a的上述列方向的中间区域和栅极端子3的连接线19b。
另外,栅极布线18、栅极布线的干布线19a、连接线19b、源极布线23以及漏极布线24能够由同一层图案形成,栅极端子3与连接线19b经由未图示的贯通孔(通孔)连接。
而且,虽未图示出,但在形成连接线19b的位置,由于连接线19b、源极布线23以及漏极布线24形成在同一层上,因此为了避免彼此重叠而将源极布线23及漏极布线24以不与连接线19b重叠的方式分别分为两条。
在本实施方式中,使栅极端子3与各个栅极布线18的行方向上的中间区域经由栅极布线的干布线19a与连接线19b而连接,因此能够抑制例如在将栅极端子3与栅极布线18的端部连接时会产生的布线电阻的偏差。
在本实施方式中,连接线19b只要避免和相邻的栅极布线18接触,并连接于栅极布线的干布线19a的上述列方向的中间区域即可。另外,栅极布线的干布线19a的上述列方向的中间区域是指在如本实施方式这种在列方向上配置有5个指状电极1的情形下,存在于第3列的指状电极1之间的栅极布线的干布线19a。
根据这种常断开型半导体装置30a,由于仅加入栅极布线的干布线19a和连接线19b作为布线,因此能够在不使布线面积大幅地增大之下抑制因布线电阻的影响而在多个指状电极1间产生的经由栅极端子3输入的信号的传输延迟的偏差,并且能够防止因电力集中到特定的指状电极1而导致的破坏,因此能够实现改善了应答性能及可靠性的半导体装置30a及复合型半导体装置。
另外,在本实施方式中,为了排除稳压二极管5存在于栅极端子3与块17之间的情形时,连接线19b的长度变长会产生的整体性的布线延迟的影响,而将稳压二极管5配置在常断开型半导体装置30a的一端部上,将栅极端子3配置在常断开型半导体装置30a的与上述一端部相反侧的另一端部上,但并不限定于此,稳压二极管5也可以存在于栅极端子3与块17之间。
[实施方式3]
接下来,根据图10针对本发明的实施方式3进行说明。本实施方式的常断开型半导体装置中所具备的的连接线19c,在通过相应的行的指状电极1的中央的这一点上是与实施方式2不同,其他方面则如实施方式2中已说明。为了便于说明,对于具有与实施方式2的附图中所示的部件相同功能的部件,标记相同符号并省略其说明。
图10是表示形成有连接线19c的单元块的一部分29a的图。
连接线19c沿着栅极布线18形成,且将未图示的栅极布线的干布线19a的上述列方向的中间区域与未图示的栅极端子3连接。
如图所示,连接线19c配置成通过单元块中的指状电极的列方向的中央部、即单元块的列方向的中央部。
而且,由于在形成连接线19c的部位,连接线19c与源极布线23以及漏极布线24形成在同一层中,因此为了避免彼此重叠而将源极布线23及漏极布线24以不与连接线19c重叠的方式分别分为两条。
根据这种结构,由于将指状电极中栅极电阻最大的指状电极的列方向的中央部用作为布线区域,因此可去除与栅极电容构成的最大延迟要素,降低因设置连接线19c而会产生的对常断开型半导体装置的应答特性的影响,且能够在不使布线面积大幅地增大之下,抑制因布线电阻的影响而在多个指状电极1间产生的经由栅极端子3输入的信号的传输延迟的偏差,并且能够防止电力集中到特定的指状电极1而导致的破坏,因此能够实现改善了应答性能及可靠性的半导体装置及复合型半导体装置。
[实施方式4]
接下来,根据图11针对本发明的实施方式4进行说明。在本实施方式的常断开型半导体装置中所具备的的连接线19d的列方向的宽度较栅极布线18的列方向的宽度更宽的这一点上,与实施方式2及3不同,其他方面则如实施方式2及3中已说明。为了便于说明,对于具有与实施方式2及3的附图中所示的部件相同功能的部件,标记相同符号并省略其说明。
图11是表示形成有连接线19d的单元块的一部分29b的图。
连接线19d沿着栅极布线18形成,且将未图示的栅极布线的干布线19a的上述列方向的中间区域与未图示的栅极端子3连接。
如图所示,连接线19d的列方向的宽度较栅极布线18的列方向的宽度更宽。而且,在形成连接线19d的部位,由于连接线19d与源极布线23以及漏极布线24形成在同一层上,因此为了避免彼此重叠,而将源极布线23及漏极布线24以不与连接线19d重叠的方式分别分为两条。
如上所述,通过使连接线19d的列方向的宽度大于栅极布线18的列方向的宽度,能够降低经由栅极端子3输入的信号最集中流过的连接线19d的布线电阻。其结果,能够在不使布线面积大幅地增大之下,抑制因布线电阻的影响而在多个指状电极1间产生的经由栅极端子3输入的信号的传输延迟的偏差,并且能够防止电力集中到特定的指状电极1而导致的破坏,因此能够实现改善了应答性能及可靠性的半导体装置及复合型半导体装置。
另外,在本实施方式中,虽为了通过将指状电极中栅极电阻最大的指状电极的列方向的中央部用作为布线区域,来去除与栅极电容构成的最大延迟要素,而将连接线19d配置在指状电极的列方向的中央部,但只要能够将连接线19d与未图示的栅极布线的干布线19a的上述列方向的中间区域连接,则也可以不将其配置在指状电极的列方向的中央部。
[结论]
本发明的方式1中的复合型半导体装置包含多个常断开型场效应晶体管,且包含具备栅极端子、漏极端子及源极端子的半导体装置、常导通型场效应晶体管、第2栅极端子、第2漏极端子以及第2源极端子,其特征在于,在上述多个常断开型场效应晶体管的各者中,栅极电极与上述栅极端子连接,漏极电极与上述漏极端子连接,源极电极与上述源极端子连接,在上述半导体装置中,上述栅极端子、与上述漏极端子及上述源极端子中的任一者形成在第1面上,上述漏极端子及上述源极端子中的另一者形成在上述第1面的背面即第2面上,上述第2漏极端子与上述常导通型场效应晶体管的漏极电极连接,上述第2源极端子与上述常导通型场效应晶体管的栅极电极及上述半导体装置的源极端子连接,上述第2栅极端子与上述半导体装置的栅极端子连接,上述常导通型场效应晶体管的源极电极与上述半导体装置的漏极端子连接,上述多个常断开型场效应晶体管配置成多行多列,经由上述栅极端子输入的信号,从与上述多个常断开型场效应晶体管中、同一行或相邻的两行的场效应晶体管的各个的栅极电极连接且沿上述行形成的栅极布线的上述行方向上的中间区域被供给。
根据上述结构,上述多个常断开型场效应晶体管配置成多行多列,经由上述栅极端子输入的信号,从与上述多个常断开型场效应晶体管中、同一行或相邻的两行的场效应晶体管的各个的栅极电极连接且沿上述行形成的栅极布线的上述行方向上的中间区域被供给,因此,能够抑制因布线电阻的影响,由上述多个常断开型场效应晶体管的配置位置所导致的经由上述栅极端子输入的信号的传输延迟的偏差,并且能够防止因电力集中到特定的常断开型场效应晶体管而导致的破坏,因此能够实现抑制了布线面积的增大的同时,改善了应答性能及可靠性的复合型半导体装置。
本发明的方式2中的复合型半导体装置优选为:在上述方式1中,上述栅极端子配置在包含上述配置成多行多列的常断开型场效应晶体管的块的中央区域。
根据上述结构,能够抑制因各个常断开型场效应晶体管的栅极电极与栅极端子之间的距离差所产生的布线电阻的差。
本发明的方式3中的复合型半导体装置优选为:在上述方式1中,上述栅极端子配置在包含上述配置成多行多列的常断开型场效应晶体管的块的外部,该复合型半导体装置具备与上述栅极布线的上述行方向上的中间区域连接且沿上述列方向形成的一条干布线、以及沿上述栅极布线形成且连接上述干布线的上述列方向的中间区域与上述栅极端子的连接线。
根据上述结构,由于仅加入一条干布线和连接线作为布线,因此能够在不使布线面积大幅地增大之下,抑制因布线电阻的影响,由上述多个常断开型场效应晶体管的配置位置所导致的经由上述栅极端子输入的信号的传输延迟变化,并且能够防止电力集中到特定的常断开型场效应晶体管而导致的破坏,因此能够实现改善了应答性能及可靠性的复合型半导体装置。
本发明的方式4中的复合型半导体装置优选为:在上述方式3中,上述连接线的上述列方向的宽度较上述栅极布线的上述列方向的宽度更宽。
根据上述结构,能够降低经由栅极端子输入的信号最集中流过的连接线的布线电阻。
本发明的方式5中的复合型半导体装置优选为:在上述方式3或4中,上述连接线配置在上述列方向的中间区域的行的上述多个常断开型场效应晶体管的上述列方向的中央部。
根据上述结构,由于将上述常断开型场效应晶体管中栅极电阻最大的上述常断开型场效应晶体管的列方向的中央部用作为布线区域,因此能够去除与栅极电容构成的最大延迟要素,降低因设置连接线而会产生的对复合型半导体装置的应答特性的影响。
本发明的方式6中的复合型半导体装置优选为:在上述方式1至5的任一者中,上述常导通型场效应晶体管具备由GaN或SiC构成的半导体层。
根据上述结构,由于能够实现每单位面积的导通电阻较低的常导通型场效应晶体管,因此能够流过更大的电流。
本发明的方式7中的复合型半导体装置优选为:在上述方式1、3、4以及5的任一者中,具备阳极电极与上述源极端子连接、阴极电极与上述漏极端子连接的稳压二极管,上述稳压二极管位于上述半导体装置的一端部,上述栅极端子位于与上述半导体装置的一端部相反侧的另一端部。
根据上述结构,由于具备有稳压二极管,因此即便是在上述半导体装置被施加了其耐压以上的电压的情形,也能够防止故障。此外,根据上述结构,上述稳压二极管位于上述半导体装置的一端部,上述栅极端子位于与上述半导体装置的一端部相反侧的另一端部,因此能够排除稳压二极管存在于栅极端子与块之间的情形时会产生的信号延迟的影响。
本发明的方式8中的复合型半导体装置优选为:在上述方式1至7的任一者中,在上述第1面上,上述栅极端子经由形成于上述漏极端子及上述源极端子中的任一者上的开口部而外露于上述半导体装置的外部。
根据上述结构,能够在上述第1面上,通过同一层的图案来形成上述栅极端子、与上述漏极端子及上述源极端子中的任一者。
另外,本发明并不限定于上述的各实施方式,可在权利要求范围内进行各种的变更,关于适当地组合已分别公开于不同实施方式中的技术手段而获得的实施方式也包含在本发明的技术范围内。
产业上的可利用性
本发明特别适用于半导体装置和复合型半导体装置。
符号说明
1 指状电极(常断开型场效应晶体管)
2 漏极端子
3 栅极端子
4 源极端子
5 稳压二极管
13 脉冲发生器
14 终端电阻
15 负载电阻
16 电源
17 块
18 栅极布线
19 栅极布线的干布线(干布线)
19a 栅极布线的干布线(干布线)
19b 连接线
19c 连接线
19d 连接线
20 漏极端子开口部
21 栅极接点
22 多晶硅栅极
23 源极布线
24 漏极布线
25 漏极接点
26 基板
29 单元块
29a 单元块的一部分
29b 单元块的一部分
30 半导体装置
30a 半导体装置
31 常导通型场效应晶体管
32 复合型半导体装置的漏极端子(第2漏极端子)
33 复合型半导体装置的栅极端子(第2栅极端子)
34 复合型半导体装置的源极端子(第2源极端子)
40 复合型半导体装置
41 芯片垫
45 第1引线
46 第2引线
47 第3引线
48 第4引线
49 封装体
G 指状电极的栅极电极
S 指状电极的源极电极
D 指状电极的漏极电极
A 阳极电极
C 阴极电极

Claims (3)

1.一种复合型半导体装置,包含:半导体装置,其包括多个常断开型场效应晶体管,且具备栅极端子、漏极端子及源极端子;常导通型场效应晶体管;第2栅极端子;第2漏极端子以及第2源极端子,其特征在于,
在所述多个常断开型场效应晶体管的各个中,栅极电极与所述栅极端子连接,漏极电极与所述漏极端子连接,源极电极与所述源极端子连接;
在所述半导体装置中,所述漏极端子和所述源极端子中的任意一个与所述栅极端子形成在第1面上,所述漏极端子和所述源极端子中的另一个形成在所述第1面的背面即第2面上;
所述第2漏极端子与所述常导通型场效应晶体管的漏极电极连接,所述第2源极端子与所述常导通型场效应晶体管的栅极电极及所述半导体装置的源极端子连接,所述第2栅极端子与所述半导体装置的栅极端子连接,所述常导通型场效应晶体管的源极电极与所述半导体装置的漏极端子连接;
所述多个常断开型场效应晶体管配置成多行多列;
具备栅极布线,所述栅极布线与所述多个常断开型场效应晶体管中、同一行或相邻的两行的场效应晶体管的各个栅极电极连接且沿所述行形成;
所述栅极端子配置在包含所述配置成多行多列的常断开型场效应晶体管的块的外部;
具备与所述栅极布线的所述行方向上的中间区域连接且沿所述列方向形成的一条干布线、以及沿所述栅极布线形成且用于连接所述干布线的所述列方向的中间区域和所述栅极端子的连接线;
经由所述栅极端子、所述连接线及所述干布线输入的信号,从所述栅极布线的所述行方向上的中间区域被供给。
2.根据权利要求1所述的复合型半导体装置,其特征在于,
所述连接线的所述列方向的宽度较所述栅极布线的所述列方向的宽度更宽。
3.根据权利要求1或2所述的复合型半导体装置,其特征在于,
所述连接线配置在所述列方向的中间区域的行中的所述多个常断开型场效应晶体管的所述列方向的中央部。
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