CN107887358B - 膜型半导体封装及其制造方法 - Google Patents

膜型半导体封装及其制造方法 Download PDF

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CN107887358B
CN107887358B CN201710679505.9A CN201710679505A CN107887358B CN 107887358 B CN107887358 B CN 107887358B CN 201710679505 A CN201710679505 A CN 201710679505A CN 107887358 B CN107887358 B CN 107887358B
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metal
layer
type semiconductor
semiconductor package
lead
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CN107887358A (zh
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金正雨
金云培
卢宝仁
G.成
朴智镛
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

本发明公开了膜型半导体封装以及制造膜型半导体封装的方法。该膜型半导体封装包括布置在膜基板上的金属引线部分、包括焊垫的半导体芯片以及将金属引线部分连接到半导体芯片的焊垫的凸块。凸块包括：金属柱，布置在焊垫上并且包括第一金属；以及焊接部分，布置在金属柱的整个表面上，接合到金属引线部分并且包括第一金属和不同于第一金属的第二金属。

Description

膜型半导体封装及其制造方法
技术领域
发明构思涉及膜型半导体封装及其制造方法，和/或涉及利用膜基板的膜型半导体封装及其制造方法。
背景技术
膜型半导体封装，例如，膜上芯片(COF)半导体封装，通常通过接合布置在半导体芯片的焊垫上的凸块与布置在膜基板上的金属引线部分而制造。
随着电子器件的小型化、纤薄、轻重量和高性能的趋势，通常存在于膜型半导体封装中的凸块已经变得越来越精细。因此，当制造膜型半导体封装时，当应用于凸块与金属引线部分之间时，可靠的接合工艺会是有利的。此外，当凸块和金属引线部分被彼此接合时，在凸块被接合到金属引线部分时膜基板的弯曲可以被减小。
发明内容
发明构思涉及能够减小膜基板的弯曲并且更可靠地将凸块和金属引线部分彼此接合的膜型半导体封装。
发明构思涉及制造膜型半导体封装的方法。
根据发明构思的一示例实施方式，膜型半导体封装包括布置在膜基板上的金属引线部分、包括焊垫的半导体芯片、以及连接金属引线部分与半导体芯片的焊垫的凸块。凸块可以包括：金属柱，布置在焊垫上并且包括第一金属；以及焊接部分，在金属柱的整个表面上，接合到金属引线部分并且包括第一金属和不同于第一金属的第二金属。
根据发明构思的另一示例实施方式，膜型半导体封装包括从在膜基板的一个侧部分处的外部引线接合部分延伸到内部引线接合部分的金属引线部分、包括焊垫的半导体芯片、以及连接内部引线接合部分的金属引线部分与半导体芯片的焊垫的凸块。凸块可以包括：金属柱，在焊垫上并且包括第一金属；以及焊接部分，在金属柱的整个表面上，接合到金属引线部分并且可以包括第一金属和不同于第一金属的第二金属。
根据发明构思的另一示例实施方式，膜型半导体封装包括在膜基板上并且包括铜层的金属引线部分、包括焊垫的半导体芯片、以及连接金属引线部分与半导体芯片的焊垫的凸块。凸块可以包括：金属柱，在焊垫上并且包括金层或者铜层；以及焊接部分，在金属柱的整个表面上，可以包括金-锡共晶合金层并且可以被接合到金属引线部分。
根据发明构思的另一示例实施方式，制造膜型半导体封装的方法包括：形成包括金属引线部分的膜基板；在半导体芯片的焊垫上形成金属柱；在金属柱上形成第一焊料层；在第一焊料层上形成第二焊料层以形成包括金属柱、第一焊料层和第二焊料层的初级凸块；以及热压金属引线部分以及初级凸块的第一焊料层和第二焊料层以形成包括焊接部分的凸块，该焊接部分将金属引线部分接合到半导体芯片的焊垫。
一些示例实施方式涉及接合到半导体封装中的引线部分的接合凸块，接合凸块包括包含第一金属的金属柱以及在金属柱上的焊接部分，焊接部分被接合到金属引线部分并且包括第一金属和第二金属的共晶合金层。
附图说明
通过结合附图的以下详细说明，发明构思的示例实施方式将被更清楚地理解，在附图中：
图1是示出采用根据一示例实施方式的膜型半导体封装的显示装置的框图；
图2是示意地示出根据一示例实施方式的膜型半导体封装的俯视图；
图3是示出图2的膜型半导体封装的半导体芯片与膜基板之间的连接的沿Y-Z面的截面图；
图4是示出根据一示例实施方式的膜型半导体封装的沿Y-Z面的截面图；
图5是示出根据一示例实施方式的膜型半导体封装的凸块的结构的沿X-Z面的截面图；
图6是示出根据一示例实施方式的膜型半导体封装的凸块的结构的沿X-Z面的截面图；
图7是示出根据一示例实施方式的制造膜型半导体封装的方法的流程图；
图8至12是示出根据一示例实施方式的制造膜型半导体封装的方法的沿X-Z面的截面图；
图13和14是示出根据一示例实施方式的准备用于制造膜型半导体封装的初级凸块的构造的沿X-Z面的截面图；
图15是构成根据一示例实施方式的膜型半导体封装的焊料层的元素的相图；以及
图16是示出包括根据一示例实施方式的膜型半导体封装的显示装置的构造的框图。
具体实施方式
在下文，将参考附图详细描述示例实施方式。
当术语“大约”或“基本上”结合数值用在本说明书中时，意图是相关的数值包括所述数值周围的±10％的公差。此外，当在本说明书中提到百分比时，意图是那些百分比是基于重量的，例如是重量百分比。表述“直到......”包括零和所述上限的量以及其间的所有值。当指定范围时，该范围包括具有诸如0.1％的增量的其间的所有值。此外，当与几何形状相关地使用措辞“总体上”和“基本上”时，意图是不需要几何形状的精确性而是所述形状的选择范围(latitude)在本公开的范围内。虽然实施方式的管形元件可以是圆柱形，但其它管形截面形式也被构想到，诸如正方形、矩形、椭圆形、三角形等。
膜型半导体封装，例如膜上芯片半导体封装，可以被应用于移动终端设备、膝上型计算机或者显示装置，例如平板显示装置。由于显示装置由包括配置为执行各种功能的输入/输出端子的半导体芯片驱动并且已经变得更薄，所以膜型半导体封装可以应用于显示装置。
在下文，为了说明的方便起见，应用于半导体芯片(例如，包括在显示装置中的显示驱动IC(集成电路))的膜型半导体封装将作为代表示例被描述。显示驱动IC可以被称为“显示驱动器IC”。
图1是示出根据一示例实施方式的采用膜型半导体封装的显示装置500的框图。
具体地，显示装置500可以包括膜型半导体封装100、源极驱动印刷电路板(PCB)300、栅极驱动PCB 400以及图像显示面板550。
源极驱动PCB 300和栅极驱动PCB 400可以提供信号到图像显示面板550以允许图像通过图像显示面板550的每个像素或者至少一个像素显示。图像显示面板550可以基于施加到其的信号而显示图像。
膜上芯片半导体封装可以用作膜型半导体封装100。膜型半导体封装100可以接收从源极驱动PCB 300和栅极驱动PCB 400输出的信号并且将接收的信号传送到图像显示面板550。
图2是示意地示出根据一示例实施方式的膜型半导体封装的俯视图，图3是示出图2的膜型半导体封装的半导体芯片与膜基板之间的连接的沿Y-Z面的截面图，其中X、Y和Z方向可以彼此垂直。
具体地，膜型半导体封装100可以包括膜基板110、金属引线部分130、半导体芯片210以及凸块230。输出引脚OPIN布置在膜基板110的一个端部，并且输入引脚IPIN布置在膜基板110的另一端部。
膜基板110可以是聚酰亚胺基板，但不限于此。金属引线部分130可以包括铜层。如后面描述的，金属引线部分130可以包括金属引线例如铜层以及保护铜层的引线保护层例如锡层。膜基板110和金属引线部分130可以被称为“膜构件”。膜基板110和金属引线部分130可以被称为“载带(tape carrier)”。
膜型半导体封装100可以包括半导体芯片210，半导体芯片210提供有布置在半导体芯片210的一个表面中的焊垫220以及布置在半导体芯片210的焊垫220上的凸块230。半导体芯片210可以被安装在膜基板110上。半导体芯片210可以被提供为封装形式，因此半导体芯片210可以是半导体封装。
焊垫220可以包括例如铜层或者铝层，但不限于此。半导体芯片210的焊垫220可以是布置在芯片本体210s的周边部分处的边缘焊垫。必要时，焊垫220可以是布置在芯片本体210s的中心部分处的中心焊垫。根据应用于膜型半导体封装100的设计，焊垫220的数目或者布置可以以各种各样的方式实现。焊垫220可以包括电源焊垫、接地焊垫以及信号输入/输出焊垫。
膜型半导体封装100可以通过将布置在半导体芯片210的所述一个表面上的凸块230接合到布置在膜基板110上的金属引线部分130而形成。凸块230和金属引线部分130可以通过如下文所述的热压工艺而彼此接合。
凸块230可以布置在半导体芯片210的有源表面上，例如，其上形成电路的表面上。凸块230可以从半导体芯片的有源表面突出。凸块230可以布置在芯片本体210s的下表面上。凸块230可以布置在半导体芯片210的周边部分处。根据焊垫220的位置，凸块230可以布置在半导体芯片210的中心部分处。
半导体芯片210和金属引线部分130可以通过位于膜型半导体封装100的半导体芯片210的所述一个表面上的凸块230彼此电连接。
金属引线部分130可以电连接到膜基板110上的输入引脚IPIN和输出引脚OPIN。半导体芯片210的焊垫220可以通过凸块230连接到位于膜基板110上的金属引线部分130。根据应用于膜型半导体封装100的设计，金属引线部分130可以以各种各样的方式布置在膜基板110上。焊垫220可以通过凸块230和金属引线部分130电连接到输入引脚IPIN和输出引脚OPIN。
金属引线部分130可以包括外部引线接合部分OLB和内部引线接合部分ILB。金属引线部分130可以从在膜基板110的一个侧部分处的外部引线接合部分OLB延伸到内部引线接合部分ILB。
内部引线接合部分ILB可以是在该处半导体芯片210接合到膜基板110的部分。外部引线接合部分OLB可以是在该处图像显示面板550(参照图1)接合到源极驱动PCB 300和栅极驱动PCB 400(参照图1)的部分。
随着电子装置的小型化、纤薄、轻重量和高性能的趋势，焊垫220和凸块230的数目可以增加。膜型半导体封装100可以有利地具有位于半导体芯片210的所述一个表面上的凸块230与位于膜基板110上的金属引线部分130之间的接合的高可靠性。此外，膜型半导体封装100中的凸块230与金属引线部分130的接合工艺被容易地执行可以是有利的，并且膜基板110不弯曲可以是有利的。
因此，膜型半导体封装100可以包括凸块230，该凸块230具有焊接部分230f以便改善接合可靠性并且阻碍或者防止膜基板110弯曲。凸块230的结构和材料将在下面被更详细地描述。
图4是示出根据一示例实施方式的膜型半导体封装100-1的沿Y-Z面的截面图。
在图4中，相同的附图标记表示与图1至3中的元件相同的元件。膜型半导体封装100-1可以对应于图1至3的膜型半导体封装100。膜型半导体封装100-1可以还包括电子元件232、支撑板234、连接器236和238以及底部填充层240。
膜型半导体封装100-1可以包括布置在膜基板110上的金属引线部分130以及布置在金属引线部分130上从而暴露一部分金属引线部分130的抗蚀层(resist layer)132。虽然在图4中，抗蚀层132仅布置在膜基板110的上表面上，但附加的抗蚀层可以布置在膜基板110的下表面上。半导体芯片210和电子元件232可以安装在金属引线部分130上。
半导体芯片210可以通过包括焊接部分230f的凸块230而接合到金属引线部分130。半导体芯片210可以用布置在膜基板110上的底部填充层240保护凸块230。电子元件232可以通过粘合层242接合到金属引线部分130。电子元件232可以配置为作为表面安装器件执行各种功能。电子元件232可以包括例如有源元件、无源元件和半导体芯片。
在膜型半导体封装100-1中，连接器236和238可以在膜基板110的相反端部(例如膜基板110的一个端部和另一端部)分别布置在金属引线部分130处作为外部引线接合部分OLB。连接器236和238可以接合到图像显示面板550(参照图1)以及源极驱动PCB 300和栅极驱动PCB 400(参照图1)。在一些示例实施方式中，在膜型半导体封装100-1中，支撑板234可以布置在膜基板110的下表面上以支撑膜基板110。
图5是示出根据一示例实施方式的膜型半导体封装的凸块的结构的沿X-Z面的截面图。
具体地，图5示出在图1至4的膜型半导体封装100和100-1中的凸块结构以及膜基板110与半导体芯片210的焊垫220之间利用凸块230的连接关系100a。在图5中，相同的附图标记表示与图1至4中示出的元件相同的元件。
布置在膜基板110上的金属引线部分130可以经由凸块230连接到半导体芯片210的焊垫220。图1至4中示出的膜型半导体封装100和100-1可以通过将布置在半导体芯片210的所述一个表面上的凸块230接合到膜基板110上的金属引线部分130而被制造。
凸块230和金属引线部分130可以通过如下文所述的热压工艺而彼此接合。在图5中，膜基板110相对于凸块230和/或金属引线部分130处于相对较高的位置，半导体芯片210相对于凸块230和/或金属引线部分130处于相对较低的位置。因此，金属引线部分130和凸块230可以通过利用加压和加热单元施加压力和热到膜基板110而接合到彼此。
金属引线部分130可以包括金属引线130a和保护金属引线130a的表面的引线保护层130b。金属引线130a可以包括铜层，引线保护层130b可以包括锡层。
被焊垫保护层224保护的焊垫220可以设置在半导体芯片210的表面上。焊垫220可以包括铜层和铝层。焊垫保护层224可以包括绝缘层，例如硅氮化物层。凸块230可以设置在焊垫220上以连接到金属引线部分130。
凸块230可以布置在焊垫220上方并且可以包括包含第一金属例如金或者铜的金属柱230a。凸块230可以包括焊接部分230f，该焊接部分230f布置在金属柱230a的整个表面上方，接合到金属引线部分130，并且包含可以不同于第一金属的第二金属，例如锡。换言之，凸块230可以包括布置在焊垫220上方的金属柱230a以及布置在金属柱230a的整个表面上方并接合到金属引线部分130的焊接部分230f。
金属柱230a可以包括金层或铜层。金属柱230a可以包括相对于焊接部分230f具有低的反应性或者低的相互原子扩散率的金层。必要时，凸块230可以还包括布置在焊垫220上的阻挡层230r。阻挡层230r可以促进在焊垫220上形成金属柱230a。阻挡层230r可以包括金属性层，例如，钛层、钛氮化物层等等。
焊接部分230f可以包括包含如上所述的第一金属和第二金属的金-锡共晶合金(eutectic alloy)层。如下文所述，焊接部分230f可以包括通过使第二焊料层例如金层与第一焊料层例如锡层形成合金而获得的金-锡共晶合金层，锡层具有比金层的熔点低的熔点。金-锡共晶合金层包含大约25at％至大约45at％的锡原子。焊接部分230f可以围绕金属引线部分130的底表面和相反的侧表面。
除了焊接部分230f之外，凸块230可以还包括第二焊料层例如金层，并且第一焊料层例如锡层具有比第二焊料层的熔点低的熔点，以便降低在将金属引线部分130连接到凸块230(或者图12的初级凸块230p)的热压工艺期间加压和加热单元的加压压力和加压温度。
因此，膜型半导体封装100和100-1的金属引线部分130和焊垫220可以通过凸块230可靠地连接到彼此。此外，膜型半导体封装100和100-1可以降低在将金属引线部分130连接到凸块230的热压工艺期间加压和加热单元的加压压力和加压温度，因此可以减小或者防止膜基板110的弯曲。
图6是示出根据一示例实施方式的膜型半导体封装的凸块的结构的沿X-Z面的截面图。
具体地，图6示出在图1至4的膜型半导体封装100和100-1中的凸块结构以及膜基板110与半导体芯片210的焊垫220之间利用凸块230-1的连接关系100b。在图6中，相同的附图标记表示与图1至5中的元件相同的元件。
图6的膜基板110与半导体芯片210的焊垫220之间的连接关系100b可以具有与图5的连接关系100a的结构相同的结构，除了凸块230-1还包括扩散防止层230s之外。相同的元件的详细描述将被省略以免重复。
凸块230-1可以将布置在膜基板110上的金属引线部分130连接到半导体芯片210的焊垫220。凸块230-1可以包括布置在焊垫220上并且包括第一金属例如金或者铜的金属柱230a、布置在金属柱230a上并且包括不同于第一金属和第二金属的第三金属例如镍的扩散防止层230s、以及焊接部分230f，该焊接部分230f布置在扩散防止层230s的整个表面上，接合到金属引线部分130并且包括第一金属和不同于第一金属或者第三金属的第二金属，例如锡。
金属柱230a可以包括金层或者铜层。扩散防止层230s可以包括具有比焊接部分230f中的锡的熔点高的熔点。扩散防止层230s可以包括镍层。
扩散防止层230s可以阻碍或者防止构成金属柱230a的元素诸如铜在扩散之后对焊接部分230f施加影响。当扩散防止层230s如图6所示地形成时，金属柱230a可以包括铜层，因为金属柱230a相对于焊接部分230f的反应性或者相互原子扩散率可以不被考虑。
图7是示出根据一示例实施方式的制造膜型半导体封装的方法的流程图，图8至12是示出根据一示例实施方式的制造膜型半导体封装的方法的沿X-Z面的截面图。
具体地，如图7和8中所示出的，膜型半导体封装的制造方法包括形成包含金属引线部分130的膜基板110(S310)。金属引线部分130形成在膜基板110的表面上。如上所述，金属引线部分130包括金属引线130a例如铜层以及引线保护层130b例如锡层。
如图7和9中所示出的，阻挡层230r和金属柱230a形成在半导体芯片210的焊垫220上(S320)。焊垫220可以被焊垫保护层224限制。阻挡层230r可以根据需要形成。
阻挡层230r可以包括金属性层例如钛层或者钛氮化物层，如上所述。金属柱230a可以包括金层或者铜层。阻挡层230r和金属柱230a可以与焊垫220对准。换言之，阻挡层230r和金属柱230a可以形成在由形成在半导体芯片210上的掩模层226限制的焊垫220上。
如图7、10和11中所示出的，扩散防止层230s形成在金属柱230a上(S330)。如上所述，扩散防止层230s可以根据需要形成。例如，扩散防止层230s可以包括镍层。
焊料层230e可以形成(例如，随后形成)在扩散防止层230s上(S340)。焊料层230e可以包括形成在扩散防止层230s上的第一焊料层230b以及形成在第一焊料层230b上的第二焊料层230c。
第一焊料层230b可以包括具有比第二焊料层230c的熔点低的熔点的金属层。第一焊料层230b可以包括锡层。第二焊料层230c可以包括金层。配置为包括阻挡层230r、金属柱230a、第一焊料层230b以及第二焊料层230c的初级凸块230p可以通过上述工艺形成在焊垫220上，如图10所示。
以上描述的阻挡层230r、金属柱230a、第一焊料层230b和第二焊料层230c可以例如通过各种方法形成，诸如热沉积方法、电子束沉积方法、溅射方法、电镀方法、化学镀方法等等。
当掩模层226(参照图10)被去除时，初级凸块230p可以完成，如图11所示。初级凸块230p可以被提供为其中初级凸块230p电连接到半导体芯片210上的焊垫220的状态。
参照图5、6、7和12，金属引线部分130和初级凸块230p可以被热压以形成共晶合金层，由此形成具有焊接部分230f(参照图5和6)的凸块230和230-1(参照图5和6)(S350)。图12示出其中包括金属引线部分130的膜基板110与其上形成了初级凸块230p的半导体芯片210分离的状态。
初级凸块230p可以用于描述其中半导体芯片210没有接合到金属引线部分130的状态，并且初级凸块230p可以是如一般概念的凸块。初级凸块230p可以形成为具有包括金属柱230a、第一焊料层230b和第二焊料层230c的三层结构。初级凸块230p可以形成为具有金属柱230a、扩散防止层230s、第一焊料层230b和第二焊料层230c的四层结构。
用于金属引线部分130和初级凸块230p的热压工艺可以是通过经由加压和加热单元施加压力和热到膜基板110和初级凸块230p而将金属引线部分130接合到初级凸块230p的工艺。焊接部分230f(参照图5和6)可以通过熔化第一焊料层230b和第二焊料层230c(这导致形成共晶合金层)而形成。
由于用于金属引线部分130和初级凸块230p的热压工艺，在金属引线部分130和初级凸块230p如图12的箭头所示出地经由加压和加热单元彼此接触之后形成共晶合金层。
例如，接合工艺可以通过在大约300℃至大约400℃的温度施加大约10kgf/cm2至大约20kgf/cm2的压力到膜基板110和初级凸块230p几秒至几十秒的时间而执行。然而，上述示例接合工艺条件可以改变，可以使用导致金属引线部分130和初级凸块230p通过形成共晶合金层而接合到彼此的其它接合条件。
为了更容易地形成共晶合金层，焊接部分230f(参照图5和6)可以包括通过使第二焊料层230c例如金层与第一焊料层230b例如锡层形成合金而获得的金-锡共晶合金层，锡层具有比金层的熔点低的熔点。金-锡共晶合金层包含大约25at％至大约45at％的锡原子。
图13和14是示出根据一示例实施方式的准备用于制造膜型半导体封装的初级凸块的构造的沿X-Z面的截面图。
在一些示例实施方式中，如上所述，当膜型半导体封装被制造时，初级凸块230p-1或者初级凸块230p-2可以形成在焊垫220上，初级凸块230p-1包括阻挡层230r、金属柱230a、第一焊料层230b和第二焊料层230c-1，初级凸块230p-2包括阻挡层230r、金属柱230a、第一焊料层230b和第二焊料层230c-2。图13中示出的初级凸块230p的第二焊料层230c-1可以具有与图14中示出的初级凸块230p-2的第二焊料层230c-2的厚度T4不同的厚度T3。
金属柱230a可以具有大约几十微米(μm)的厚度T1。第一焊料层230b可以具有大约几微米(μm)的厚度T2。图13中示出的第一焊料层230b的厚度T2可以大于第二焊料层230c-1的厚度T3。
图13中示出的第二焊料层230c-1的厚度T3可以相应于第一焊料层230b的厚度T2的大约50％。图14中示出的第一焊料层230b的厚度T2可以大于第二焊料层230c-2的厚度T4。图14中示出的第二焊料层230c-2的厚度T4可以相应于第一焊料层230b的厚度T2的大约10％至大约30％。
在图13和14中，当金属引线部分130以及初级凸块230p-1和230p-2被热压时，初级凸块230p-1和230p-2中的第一焊料层230b中的焊料原子例如锡原子可以在金属柱230a以及第二焊料层230c-1和230c-2中形成固溶体，如图13和14中的箭头所示出的，因此可以形成焊接部分230f(参照图5)。
如上所述，金属柱230a可以比第一焊料层230b厚。第一焊料层230b的厚度T2可以大于第二焊料层230c-1的厚度T3以及第二焊料层230c-2的厚度T4。在这种情况下，焊接部分230f(参照图5)可以通过金属引线部分130以及初级凸块230p-1和230p-2的热压工艺而形成。
图15是构成根据一示例实施方式的膜型半导体封装的焊料层的元素的相图。
具体地，图15示出上述示例膜型半导体封装的焊料层例如金-锡共晶合金层的相图。如参照图12描述的，焊接部分230f(参照图5和6)可以经由对金属引线部分130和初级凸块230p执行的热压工艺而形成。
初级凸块230p(参照图12)可以包括第一焊料层230b(参照图12)例如锡层以及第二焊料层230c(参照图12)例如金层。焊接部分230f(参照图5和6)可以包括通过第一焊料层203b和第二焊料层230c的共晶反应形成的金-锡共晶合金层。
如图15所示，当温度是大约280℃并且金-锡合金中的锡原子是大约29.0at％时发生共晶反应的点可以被称为共晶点。当温度等于或小于大约280℃并且金-锡合金中锡原子的含量等于或大于大约17at％并且等于或小于大约50at％时，金-锡合金可以以ζ相存在。当温度等于或小于大约280℃并且金-锡合金中锡原子的含量等于或大于大约50at％时，金-锡合金可以以δ相存在。
基于以上描述，当对金属引线部分130和初级凸块230p执行热压工艺时，金-锡焊料层中的锡原子的含量可以保持在大约25at％与大约45at％之间，并且加压(接合)温度可以保持在大约300℃与大约400℃之间。此外，加压压力(接合压力)可以保持在大约10kgf/cm2与大约20kgf/cm2之间，并且加压(接合)工艺在几秒至几十秒的持续时间内执行。金-锡焊料层通过加压(接合)工艺形成固溶体，因此可以形成金-锡共晶合金层。
根据膜型半导体封装，当包括金属柱230a以及焊料层230b和230c的初级凸块230p被热压时，加压(接合)温度和压力可以通过上述加压(接合)工艺降低。此外，膜型半导体封装的膜基板110(参照图12)的弯曲可以被减小或防止，并且金-锡共晶合金层可以被容易地形成。
图16是示出包括根据一示例实施方式的膜型半导体封装的显示装置的构造的框图。
参照图16，平板显示装置500可以包括图像显示面板550以及通过膜型半导体封装100施加驱动信号到图像显示面板550的源极驱动PCB 300。图像显示面板550可以包括例如液晶显示面板。
虽然在图中未示出，但源极驱动PCB 300可以包括被建造在其中的电力单元、存储单元、程序单元以及缓冲单元。从外部电源提供到源极驱动PCB300的电力单元的电力被施加到源极驱动PCB 300的电路，诸如存储单元、程序单元以及缓冲单元。源极驱动PCB 300的电力单元通过膜型半导体封装100的电力线172施加电源电压到图像显示面板550以显示图像。
半导体芯片210诸如源极驱动IC被安装在膜型半导体封装100上以将来自源极驱动PCB 300的驱动信号施加到图像显示面板550。如上所述，用于图像显示面板550的显示的电源电压和操作信号通过膜基板110(参照图2)和安装在膜基板110上的半导体芯片210诸如源极驱动IC被传输到图像显示面板550。
信号线152连接在膜型半导体封装100上的源极驱动PCB 300和图像显示面板550之间。信号线152可以构成输入电路。信号线154形成在膜型半导体封装100上的半导体芯片210和图像显示面板550之间。信号线154可以构成输出电路。
电力线172和接地线174连接在膜型半导体封装100上的源极驱动PCB300和半导体芯片210之间。电源线162和接地线164形成在膜型半导体封装100上的半导体芯片210和图像显示面板550之间。电力线162和172以及接地线164和174被制备以施加电力到图像显示面板550。
虽然已经结合示例实施方式描述了发明构思，但本领域技术人员将理解，发明构思不局限于所公开的示例实施方式，而是相反，旨在涵盖包括在权利要求的精神和范围内的各种变型、替代物和等同布置。示例实施方式可以被独立地构造和/或使用，或者与这里包含的任何其它示例实施方式结合地构造和/或使用。
因此，公开的主题不应该限于这里描述的任何单个示例实施方式，并且上述示例实施方式将被认为是示例性的而不是限制性的。因此，发明构思的范围应该仅根据权利要求来确定。
本申请要求享有于2016年9月29日在韩国知识产权局提交的韩国专利申请第10-2016-0125590号的优先权权益，其公开通过引用整体合并在此。

Claims (20)

1.一种膜型半导体封装，包括：
在膜基板上的金属引线部分；
包括焊垫的半导体芯片；以及
将所述金属引线部分连接到所述半导体芯片的所述焊垫的凸块，所述凸块包括：
在所述焊垫上的金属柱；以及
焊接部分，在所述金属柱的整个表面上，接合到所述金属引线部分，并且包括第一金属和不同于所述第一金属的第二金属，所述第二金属的熔点低于所述第一金属的熔点，
其中所述金属引线部分包括金属引线和保护所述金属引线的表面的引线保护层，所述金属引线包括铜层，并且所述引线保护层包括锡层，
其中所述焊接部分包括金-锡共晶合金层，其中锡原子的含量等于或大于25at％并且等于或小于45at％。
2.如权利要求1所述的膜型半导体封装，其中所述金属柱包括金层或者铜层。
3.如权利要求1所述的膜型半导体封装，其中所述焊接部分具有平坦的顶表面，所述金属引线的底表面低于所述焊接部分的所述顶表面并在所述顶表面内。
4.如权利要求3所述的膜型半导体封装，其中所述焊接部分围绕所述金属引线部分的底表面和相反的侧表面。
5.如权利要求1所述的膜型半导体封装，还包括：
在所述金属柱上的扩散防止层，所述扩散防止层包括不同于所述第一金属和所述第二金属的第三金属。
6.如权利要求5所述的膜型半导体封装，其中所述扩散防止层包括镍层。
7.如权利要求1所述的膜型半导体封装，其中：
所述第一金属包括金；并且
所述第二金属包括锡。
8.一种膜型半导体封装，包括：
金属引线部分，从在膜基板的一个侧部分处的外部引线接合部分延伸到内部引线接合部分；
包括焊垫的半导体芯片；以及
将所述内部引线接合部分的所述金属引线部分连接到所述半导体芯片的所述焊垫的凸块，所述凸块包括：
在所述焊垫上的金属柱；以及
焊接部分，在所述金属柱的整个表面上，接合到所述金属引线部分，并且包括第一金属和不同于所述第一金属的第二金属，所述第二金属的熔点低于所述第一金属的熔点，
其中所述金属引线部分包括金属引线和保护所述金属引线的表面的引线保护层，所述金属引线包括铜层，并且所述引线保护层包括锡层，
其中所述焊接部分包括金-锡共晶合金层，其中锡原子的含量等于或大于25at％并且等于或小于45at％。
9.如权利要求8所述的膜型半导体封装，其中所述外部引线接合部分包括接合到图像显示面板或者印刷电路板的连接部分。
10.如权利要求8所述的膜型半导体封装，其中：
所述金属柱包括金层或者铜层。
11.如权利要求8所述的膜型半导体封装，还包括：
在所述金属柱上的扩散防止层，所述扩散防止层包括镍层。
12.如权利要求8所述的膜型半导体封装，还包括：
在所述焊垫和所述金属柱之间的阻挡层。
13.如权利要求8所述的膜型半导体封装，其中：
所述第一金属包括金；并且
所述第二金属包括锡。
14.一种制造膜型半导体封装的方法，所述方法包括：
形成包括金属引线部分的膜基板；
在半导体芯片的焊垫上形成金属柱；
在所述金属柱上形成第一焊料层；
在所述第一焊料层上形成第二焊料层以形成包括所述金属柱、所述第一焊料层和所述第二焊料层的初级凸块；以及
热压所述金属引线部分以及所述初级凸块的所述第一焊料层和所述第二焊料层以形成包括焊接部分的凸块，所述焊接部分将所述金属引线部分接合到所述半导体芯片的所述焊垫，
其中所述金属引线部分包括金属引线和保护所述金属引线的表面的引线保护层，所述金属引线包括铜层，并且所述引线保护层包括锡层，
其中所述第一焊料层的熔点低于所述第二焊料层的熔点，
其中所述焊接部分包括通过所述第一焊料层和所述第二焊料层的共晶反应形成的金-锡共晶合金层，其中锡原子的含量等于或大于25at％并且等于或小于45at％。
15.如权利要求14所述的方法，其中所述第一焊料层的厚度大于所述第二焊料层的厚度。
16.如权利要求14所述的方法，其中：
所述第一焊料层包括锡层，
所述第二焊料层包括金层。
17.如权利要求14所述的方法，其中热压所述金属引线部分以及所述初级凸块的所述第一焊料层和所述第二焊料层在300℃至400℃的加压温度以及10kgf/cm2至20kgf/cm2的加压压力下执行。
18.一种膜型半导体封装，所述膜型半导体封装具有接合到引线部分的接合凸块，所述接合凸块包括：
金属柱；以及
在所述金属柱上的焊接部分，所述焊接部分被接合到所述引线部分，
其中所述引线部分包括金属引线和保护所述金属引线的表面的引线保护层，所述金属引线包括铜层，并且所述引线保护层包括锡层，
其中所述焊接部分包括金-锡共晶合金层，其中锡原子的含量等于或大于25at％并且等于或小于45at％。
19.如权利要求18所述的膜型半导体封装，其中：
所述金属柱包括金和铜中的至少一种。
20.如权利要求18所述的膜型半导体封装，还包括在所述焊接部分与所述金属柱之间的扩散防止层，所述扩散防止层包括镍层。
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