CN107799505A - 半导体封装件及其制造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 226
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 97
- 239000010410 layer Substances 0.000 claims abstract description 66
- 239000012790 adhesive layer Substances 0.000 claims abstract description 34
- 239000000463 material Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 12
- 239000011159 matrix material Substances 0.000 claims description 9
- 239000004020 conductor Substances 0.000 claims description 8
- 230000006378 damage Effects 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims 2
- -1 wherein Substances 0.000 claims 1
- 239000011241 protective layer Substances 0.000 description 9
- 238000004806 packaging method and process Methods 0.000 description 6
- 230000005611 electricity Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000011230 binding agent Substances 0.000 description 3
- 229920006336 epoxy molding compound Polymers 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L25/0657—Stacked arrangements of devices
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
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- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
-
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- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H01L2924/181—Encapsulation
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Abstract
公开了一种半导体封装件及其制造方法。该半导体封装件包括第一基底和布置在第一基底上方的第一半导体芯片。第二半导体芯片布置在第一半导体芯片的顶表面上方。粘合层在第一半导体芯片与第二半导体芯片之间。第二基底设置在第二半导体芯片上。第二基底基本覆盖第二半导体芯片的顶表面。成型层设置在第一基底与第二基底之间。
Description
本申请要求于2016年9月5日提交的第10-2016-0114018号韩国专利申请的优先权,该韩国专利申请的公开内容通过引用全部包含于此。
技术领域
本发明构思的示例性实施例涉及一种半导体封装件,更具体而言,涉及一种制造半导体封装件的方法。
背景技术
半导体装置可以是重量相对轻、尺寸相对紧凑、速度相对高和性能相对高的装置。半导体封装件可以包括在电子产品中可用的集成电路芯片。通电极(through electrode)(例如,TSV)可以被包括在半导体封装件中。
发明内容
本发明构思的一个或更多个示例性实施例提供一种具有减少翘曲的特性的半导体封装件。
根据本发明构思的示例性实施例,一种半导体封装件包括第一基底和布置在第一基底上方的第一半导体芯片。第二半导体芯片布置在第一半导体芯片的顶表面上方。粘合层在第一半导体芯片与第二半导体芯片之间。第二基底设置在第二半导体芯片上。第二基底基本覆盖第二半导体芯片的顶表面。成型层设置在第一基底与第二基底之间。
根据本发明构思的示例性实施例,一种制造半导体封装件的方法包括在第一基底的顶表面上安装芯片堆叠件。每个芯片堆叠件包括多个堆叠的半导体芯片和位于半导体芯片之间的粘合层。在第一基底的顶表面上形成成型层。去除成型层的一部分和每个芯片堆叠件的最顶部的芯片的一部分。在每个芯片堆叠件的最顶部的芯片和成型层上形成第二基底。
根据本发明构思的示例性实施例,一种半导体封装件包括:第一基底;多个半导体芯片,堆叠在第一基底上方,其中,所述多个半导体芯片中的每个半导体芯片具有彼此相同的厚度;粘合层,包括粘合材料,其中,粘合层形成在所述多个半导体芯片中的每相邻半导体芯片之间,其中,粘合层比所述多个堆叠的半导体芯片的宽度宽,其中,与所述多个半导体芯片中的最顶部的半导体芯片相邻的粘合材料的第一量和与所述多个半导体芯片中的最底部半导体芯片相邻的粘合材料的第二量基本相同;以及成型层,形成在粘合层的侧表面上。
附图说明
通过参照附图详细描述发明构思的示例性实施例,发明构思的以上和其它特征将变得更加清楚,在附图中:
图1至图7是示出根据本发明构思的示例性实施例制造半导体封装件的方法的剖视图。
图8至图9是示出根据本发明构思的示例性实施例的封装件单元的剖视图。
具体实施方式
以下,将参照附图来更详细地描述本发明构思的示例性实施例。在这方面,本发明构思可具有不同形式并不应被理解为限于在此描述的本发明构思的示例性实施例。
在整个说明书和附图中,同样的附图标记可以始终表示同样的元件。
第一方向D1可以表示与第一基底100的顶表面垂直的方向(例如,参见图1至图7),第二方向D2可以表示与第一基底100的顶表面平行的方向(例如,参见图1至图7)。
图1至图7是示出根据本发明构思的示例性实施例的制造半导体封装件的方法的剖视图。
参照图1,可以在载体基底200上形成第一基底100。作为示例,载体粘合层300可以将第一基底100附着到载体基底200。
第一基底100可以包括基体半导体芯片110。例如,第一基底100可以是包括诸如硅的半导体材料的晶圆级半导体基底。基体半导体芯片110可以包括基体电路层114和基体通电极112。可以在基体半导体芯片110的底表面上布置基体电路层114。例如,基体电路层114的上表面可以与基体半导体芯片110的底表面直接接触。基体电路层114可以包括集成电路。例如,基体电路层114可以包括存储器电路、逻辑电路或它们的组合。基体通电极112可以在第一方向D1上穿透基体半导体芯片110。基体通电极112可以电连接到基体电路层114。基体半导体芯片110的底表面可以是有源表面。第一基底100可以包括基体半导体芯片110(例如,多个基体半导体芯片110可以被包括在第一基底100中),然而本发明构思的示例性实施例不限于此。在本发明构思的示例性实施例中,第一基底100不必包括基体半导体芯片110。
第一基底100可以包括保护层102和外部互连端子104。可以在第一基底100的下方布置保护层102。保护层102可以基本覆盖基体电路层114。例如,保护层102的上表面可以与基体电路层114的底表面直接接触。保护层102可以包括氮化硅(SiN)层。可以在基体半导体芯片110的底表面上布置多个外部互连端子104。外部互连端子104均可以电连接到基体电路层114。保护层102可以通过外部互连端子104而被暴露。
参照图2,可以在第一基底100上布置芯片堆叠件S。可以在第一基底100的基体半导体芯片110上方布置芯片堆叠件S。芯片堆叠件S可以在第二方向D2上彼此间隔开。每个芯片堆叠件S可以包括在第一方向D1上堆叠的多个半导体芯片120和130a。作为示例,每个芯片堆叠件S可以包括第一半导体芯片120和第二半导体芯片130a。
可以在第一基底100的基体半导体芯片110上布置第一半导体芯片120。第一半导体芯片120和第一基底100的基体半导体芯片110可以具有晶圆上芯片(COW)结构。第一半导体芯片120可以包括第一电路层124和第一通电极122。第一电路层124可以包括存储器电路。第一通电极122可以在第一方向D1上穿透第一半导体芯片120。第一通电极122可以电连接到第一电路层124。第一半导体芯片120的底表面可以是有源表面。可以在第一半导体芯片120的底表面上布置多个第一凸块126。可以在基体半导体芯片110与第一半导体芯片120之间布置第一凸块126,其中,基体半导体芯片110与第一半导体芯片120可以通过第一凸块126彼此电连接。第一半导体芯片120可以包括可以布置在基体半导体芯片110上的多个第一半导体芯片120或单个第一半导体芯片120。例如,可以在基体半导体芯片110上堆叠多个第一半导体芯片120。在此构造中,还可以在相邻的第一半导体芯片120之间形成第一凸块126。
可以在第一半导体芯片120上布置第二半导体芯片130a。第二半导体芯片130a可以是芯片堆叠件S中的最顶部的芯片。作为示例,可以在包括半导体芯片120和130a的芯片堆叠件S的最顶部的水平处布置第二半导体芯片130a。第二半导体芯片130a的底表面可以是有源表面。第二半导体芯片130a可以包括第二电路层134。第二电路层134可以包括存储器电路。可以在第二半导体芯片130a的底表面上布置多个第二凸块136。可以在第一半导体芯片120与第二半导体芯片130a之间布置第二凸块136,其中,第一半导体芯片120和第二半导体芯片130a可以通过第二凸块136彼此电连接。第二半导体芯片130a可以具有比第一半导体芯片120的第一厚度H1大的第二厚度H2。
可以在半导体芯片110、120和130a之间形成粘合层140。粘合层140可以包括非导电膜(NCF)。例如,粘合层140可以是包括绝缘材料的聚合物胶带。可以在凸块126与136之间形成粘合层140,因此,可以减少或消除在凸块126与136之间的电短路的发生。例如,可以将焊球和粘合材料附着到第一半导体芯片120的底表面,可以布置第一半导体芯片120使得第一半导体芯片120的底表面面对第一基底100的顶表面。在此构造中,粘合材料可以朝着第一半导体芯片120的侧面溢出。作为示例,粘合材料可以流到第一半导体芯片120的外部。因此,粘合层140可以具有比半导体芯片120和130a的宽度大的宽度。也可以以与上面关于第一半导体芯片120讨论的基本相同的方式来安装第二半导体芯片130a。在本发明构思的示例性实施例中,粘合层140可以基本覆盖半导体芯片120和130a的侧表面。可选择地,可以以与如上所述的粘合层140基本相同的方式来在半导体芯片110、120和130a之间形成底部填充层。
参照图3,可以在第一基底100的顶表面上形成成型层150。成型层150可以基本覆盖芯片堆叠件S。成型层150可以具有比第二半导体芯片130a的顶表面高的顶表面。如平面图中所观察到的,成型层150可以基本围绕芯片堆叠件S。成型层150可以包括绝缘聚合物材料。例如,成型层150可以包括环氧树脂模塑化合物(EMC)。
参照图4,可以去除成型层150和第二半导体芯片130a的一部分。作为示例,可以在成型层150的顶表面上执行研磨工艺。如虚线指示的,可以部分地去除成型层150的上部。在部分地去除成型层150之后,成型层150的上表面可以沿着第二方向D2与第二半导体芯片130的上表面基本对齐。也可以基本同时地研磨第二半导体芯片130a的上部和成型层150的上部。因此,第二半导体芯片130的厚度可以从第二厚度H2调整为第三厚度H3。第三厚度H3可以小于第二厚度H2。第二半导体芯片130的研磨后的第三厚度H3可以与第一半导体芯片120的第一厚度H1基本相同。如这里使用的,术语“相同”可以表示约0%至约10%的误差(例如,第三厚度H3与第一厚度H1之间的厚度差的误差测量)。
如果第二半导体芯片130比第一半导体芯片120厚,则可以将粘合层140布置为相对更靠近第一基底100。粘合层140可以具有与成型层150的热膨胀系数(CTE)不同的热膨胀系数。当半导体封装件经历温度的变化时,在半导体封装件的下部(例如,邻近第一基底100)和上部(例如,邻近第二半导体芯片130)之间可以提供沿第二方向D2的不同的膨胀长度。这会引起半导体封装件经受由温度变化造成的翘曲。
根据本发明构思的示例性实施例,堆叠在第一基底100上的第一半导体芯片120和与最顶部的芯片对应的第二半导体芯片130可以(例如,在第一方向D1上)具有彼此基本相同的厚度。作为示例,在(例如,通过研磨)去除第二半导体芯片130的上部之后,第二半导体芯片130可以具有与第一半导体芯片120基本相同的厚度。作为示例,根据本发明构思的示例性实施例的半导体封装件在其上部和下部可以包括基本等量的粘合层140。因此,根据本发明构思的示例性实施例的半导体封装件在其上部和下部可以具有基本相同或相似的热膨胀系数,因此,可以减少或消除由温度变化造成的翘曲的发生。
参照图5,可以在第二半导体芯片130上形成第二基底160。作为示例,可以在第二半导体芯片130和第二基底160之间形成粘合构件162。可以将第二基底160附着到第二半导体芯片130的顶表面和成型层150的顶表面。第二基底160可以包括与第一基底100相同的材料。例如,第二基底160可以是硅(Si)晶圆。
在本发明构思的示例性实施例中,第二基底160可以基本覆盖半导体封装件的整个顶表面。第二基底160可以比粘合层140和成型层150相对更硬并且对机械破坏更有抵抗力。因此,当半导体封装件经历弯曲力时,第二基底160可以坚固地支撑半导体封装件,并且可以减少或消除在半导体封装件中翘曲的发生。
参图6,可以去除载体基底200和载体粘合层300。作为示例,可以去除载体基底200和载体粘合层300以暴露第一基底100的外部互连端子104和保护层102。
参照图7,可以使第一基底100经受切割工艺。可以沿着点划线SL(例如,参见图6)执行切割工艺。例如,点划线SL可以在芯片堆叠件S之间的成型层150中沿着第一方向D1延伸。因此,可以形成多个封装件单元10。
图8至图9是示出根据本发明构思的示例性实施例的封装件单元的剖视图。参照图8和图9描述的组件与上面参照图1至图7描述的组件具有相同的附图标记,这些组件可以基本彼此相同,因此可以省略重复的描述。
参照图8,可以设置第一基底100。第一基底100可以包括基体半导体芯片110。基体半导体芯片110可以包括基体电路层114和基体通电极112。在本发明构思的示例性实施例中,第一基底100不必包括基体半导体芯片110。第一基底100可以在其底表面上包括保护层102和外部互连端子104。保护层102可以基本覆盖基体电路层114。外部互连端子104可以电连接到基体电路层114。
芯片堆叠件S可以安装在第一基底100上。芯片堆叠件S可以安装在第一基底100的基体半导体芯片110上。芯片堆叠件S可以包括堆叠的第一半导体芯片120和第二半导体芯片130。
第一半导体芯片120可以安装在基体半导体芯片110上。第一半导体芯片120可以包括第一电路层124和第一通电极122。多个第一凸块126可以将第一半导体芯片120电连接到基体半导体芯片110。第一半导体芯片120可以包括堆叠在基体半导体芯片110上的多个第一半导体芯片120。
第二半导体芯片130可以安装在第一半导体芯片120上。第二半导体芯片130可以是最顶部的芯片。第二半导体芯片130可以包括第二电路层134。多个第二凸块136可以将第二半导体芯片130电连接到第一半导体芯片120。第二半导体芯片130可以具有与第一半导体芯片120的第一厚度H1基本相同的第三厚度H3。
粘合层140可以在半导体芯片110、120和130之间。粘合层140可以在凸块126与136之间,因此,可以减少或消除在凸块126与136之间的电短路。粘合层140可以具有比半导体芯片120和130的宽度大的宽度。粘合层140可以基本覆盖半导体芯片120和130的侧表面。可选择地,参照图9,粘合层140不必覆盖半导体芯片120和130的侧表面。
成型层150可以设置在第一基底100的顶表面上。作为示例,成型层150可以基本覆盖第一基底100的顶表面,并且可以基本围绕芯片堆叠件S。成型层150可以具有沿着第二方向与第二半导体芯片130的顶表面基本共面的顶表面。成型层150可以包括环氧树脂模塑化合物(EMC)。
第二基底160可以设置在第二半导体芯片130上。第二基底160可以基本覆盖第二半导体芯片130的顶表面和成型层150的顶表面。第二基底160可以是硅晶圆。粘合构件162可以设置在第二半导体芯片130和成型层150中的每个与第二基底160之间。
根据本发明构思的示例性实施例,可以对堆叠在第一基底上的第一半导体芯片和与最顶部的芯片对应的第二半导体芯片给予相同的厚度。作为示例,在半导体封装件的上部和下部两者中,半导体封装件其中可以包括基本相同或相似的量的粘合层。因此,半导体封装件在其上部和下部可以具有基本相同或相似的热膨胀系数,因此,可以减少或消除由温度变化造成的翘曲的发生。
根据本发明构思的示例性实施例,第二基底可以基本覆盖半导体封装件的顶表面。第二基底可以具有比粘合层和成型层大的刚度和/或强度(例如,对因机械应力而造成的破坏的抵抗力)。因此,当半导体封装件经历弯曲力时,第二基底可以坚固地支撑半导体封装件,并且可以减少或消除半导体封装件中翘曲的发生。
虽然已经参照本发明构思的示例性实施例具体地示出并描述了本发明构思,但是本领域普通技术人员将理解的是,在不脱离本发明构思的精神和范围的情况下,在此可做出形式和细节上的各种改变。
Claims (20)
1.一种半导体封装件,所述半导体封装件包括:
第一基底;
第一半导体芯片,布置在第一基底上方;
第二半导体芯片,布置在第一半导体芯片的顶表面上方;
粘合层,位于第一半导体芯片与第二半导体芯片之间;
第二基底,设置在第二半导体芯片上,其中,第二基底基本覆盖第二半导体芯片的顶表面;以及
成型层,设置在第一基底与第二基底之间。
2.根据权利要求1所述的半导体封装件,其中,第一半导体芯片具有与第二半导体芯片的厚度基本相同的厚度。
3.根据权利要求1所述的半导体封装件,其中,第二半导体芯片的顶表面沿着与第二半导体芯片的顶表面平行的方向与成型层的顶表面基本对齐。
4.根据权利要求1所述的半导体封装件,其中,
第一半导体芯片包括穿透第一半导体芯片的通电极,
第一半导体芯片包括面对第一基底的有源表面,
第二半导体芯片包括面对第一半导体芯片的有源表面。
5.根据权利要求1所述的半导体封装件,其中,第一半导体芯片包括堆叠在第一基底上方的多个第一半导体芯片。
6.根据权利要求5所述的半导体封装件,其中,粘合层还设置在所述多个第一半导体芯片中的相邻的第一半导体芯片之间。
7.根据权利要求1所述的半导体封装件,其中,粘合层具有比第一半导体芯片和第二半导体芯片的宽度大的宽度。
8.根据权利要求1所述的半导体封装件,所述半导体封装件还包括位于第一半导体芯片与第二半导体芯片之间的凸块,
其中,凸块将第二半导体芯片电连接到第一半导体芯片。
9.根据权利要求1所述的半导体封装件,其中,第一基底包括:
氮化硅层,位于第一基底的底表面上;以及
外部互连端子,位于第一基底的底表面上,其中,外部互连端子电连接到第一半导体芯片。
10.根据权利要求1所述的半导体封装件,其中,第一基底包括基体半导体芯片,基体半导体芯片包括穿透基体半导体芯片的基体通电极,
其中,第一半导体芯片电连接到基体半导体芯片。
11.一种制造半导体封装件的方法,所述方法包括:
在第一基底的顶表面上安装芯片堆叠件,每个芯片堆叠件包括多个堆叠的半导体芯片和位于半导体芯片之间的粘合层;
在第一基底的顶表面上形成成型层;
去除成型层的一部分和每个芯片堆叠件的最顶部的芯片的一部分;以及
在每个芯片堆叠件的最顶部的芯片和成型层上形成第二基底。
12.根据权利要求11所述的方法,其中,在去除每个芯片堆叠件的最顶部的芯片的一部分之后,堆叠的半导体芯片中的每个具有基本相同的厚度。
13.根据权利要求11所述的方法,其中,在去除每个芯片堆叠件的最顶部的芯片的一部分之后,每个最顶部的芯片的顶表面沿着与成型层的顶表面平行的方向与成型层的顶表面基本对齐。
14.根据权利要求11所述的方法,其中,通过研磨工艺去除成型层的一部分和最顶部的芯片的一部分。
15.根据权利要求11所述的方法,其中,粘合层具有比半导体芯片的宽度大的宽度。
16.一种半导体封装件,所述半导体封装件包括:
第一基底;
多个半导体芯片,堆叠在第一基底上方,其中,所述多个半导体芯片中的每个半导体芯片具有彼此相同的厚度;
粘合层,包括粘合材料,其中,粘合层形成在所述多个半导体芯片中的每相邻半导体芯片之间,其中,粘合层比所述多个堆叠的半导体芯片的宽度宽,其中,与所述多个半导体芯片中的最顶部的半导体芯片相邻的粘合材料的第一量和与所述多个半导体芯片中的最底部半导体芯片相邻的粘合材料的第二量基本相同;以及
成型层,形成在粘合层的侧表面上。
17.根据权利要求16所述的半导体封装件,其中,与所述多个半导体芯片中的最顶部的半导体芯片相邻的粘合材料中的第一热膨胀系数和与所述多个半导体芯片中的最底部半导体芯片相邻的粘合材料的第二热膨胀系数基本相同。
18.根据权利要求16所述的半导体封装件,其中,所述多个半导体芯片中的最顶部的半导体芯片的上表面与成型层的上表面基本对齐。
19.根据权利要求18所述的半导体封装件,所述半导体封装件还包括第二基底,第二基底设置在所述多个半导体芯片中的最顶部的半导体芯片的上表面和成型层的上表面上。
20.根据权利要求19所述的半导体封装件,其中,第二基底对响应于机械应力的破坏的抵抗力大于粘合层和成型层的对响应于机械应力的破坏的抵抗力。
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US20180068958A1 (en) | 2018-03-08 |
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