CN107785322A - 半导体工艺方法 - Google Patents

半导体工艺方法 Download PDF

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Publication number
CN107785322A
CN107785322A CN201710232837.2A CN201710232837A CN107785322A CN 107785322 A CN107785322 A CN 107785322A CN 201710232837 A CN201710232837 A CN 201710232837A CN 107785322 A CN107785322 A CN 107785322A
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Prior art keywords
fin
film
area
semiconductor
dielectric layer
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王参群
陈亮吟
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种半导体工艺方法,包含形成包括N型掺质的第一介电层于第一鳍之上,第一鳍延伸于基板的第一区域之上,及形成包括P型掺质的第二介电层于第一鳍及第二鳍之上,第二鳍延伸于基板的第二区域之上,第二介电层位于第一介电层上,及形成隔离层,介于相邻的第一鳍之间,以及介于相邻的第二鳍之间。本方法更加包括以第一掺质进行第一注入工艺,注入工艺改变隔离层的蚀刻速率,以及凹蚀隔离层、第一介电层及第二介电层,其中在凹蚀之后,第一鳍及第二鳍延伸于隔离层的上表面之上。

Description

半导体工艺方法
技术领域
本公开实施例涉及形成半导体装置的隔离区域的结构及方法,且于特定实施例中涉及形成鳍式场效晶体管(fin field effect transistors,简称FinFET)的浅沟槽隔离(shallow trench isolation,简称STI)区的结构及方法。
背景技术
半导体工业因电子元件(例如晶体管、二极管、电阻及电容等等)集成密度的持续改进已经历快速成长。此集成密度的改进大部分是来自不断地降低最小特征尺寸而来,而可允许更多元件被集成于给定区域。
随着晶体管尺寸下降,每一特征的尺寸也随之下降。其中一种特征为用于主动区域之间以隔绝两半导体装置的STI,而另一特征为栅结构间的层间介电层(inter-layerdielectric,简称ILD)。降低特征尺寸通常会增加深宽比,这是因为开口的宽度减少,但深度通常与以前相同。用于填充较低深宽比开口(例如基板中的STI或栅结构间的ILD)的技术可能对于由技术改进造成的高深宽比(如8:1或更高)开口有着较差的填充结果。
改进填充的选择之一为关于使用可流动的介电材料。如其名,可流动的介电材料可流动以填补间隙中的空洞。通常来说,加入数种化学物质于含硅的前驱物中以让沉积后的膜可流动。于沉积可流动膜后固化之,随后退火以去除添加的化学物质进而形成介电层(例如氧化硅)。可流动膜通常于高温(例如大于1000℃)固化及退火以得到所欲的机械性质。在一些制造过程中因例如设计限制,于低温下(例如介于300℃及700℃之间)固化及退火可流动膜。当固化于如此低温时,可流动膜的机械性质(例如湿蚀刻速率(wet etchrate,简称WER))变差(例如有较快的湿蚀刻速率),且当以后续工艺(如湿蚀刻工艺)凹蚀可流动膜时,可能会发生碟型化。
发明内容
本公开实施例包括一种半导体工艺方法,包含形成包含N型掺质的第一介电层于第一鳍之上,第一鳍延伸于一基板的第一区域之上,形成包括P型掺质的第二介电层于第一鳍及第二鳍之上,第二鳍延伸于基板的第二区域之上,第二介电层位于第一介电层上,及形成隔离层,介于相邻的第一鳍之间,以及介于相邻的第二鳍之间。此方法更加包括以第一掺质进行第一注入工艺,注入工艺改变隔离层的蚀刻速率,以及凹蚀隔离层、第一介电层及第二介电层,其中在凹蚀之后,第一鳍及第二鳍延伸于隔离层的上表面之上。
本公开实施例亦包括一种形成FinFET装置的方法,包括形成PSG膜于基板的第一区域中的第一鳍上,形成BSG膜于PSG膜及基板的第二区域中的第二鳍上,形成介电层于基板中的第一区域及第二区域中及接邻第一鳍及第二鳍,及注入掺质于介电层中,其中注入降低介电层的蚀刻速率。
本公开实施例亦包括一种半导体结构包括第一上鳍,于基板的PMOS区域中的第一长条半导体之上,第二上鳍,于基板的NMOS区域中的第二长条半导体之上,及多个STI区,于每一第一鳍及第二鳍的相反侧,其中第一上鳍延伸于接近第一上鳍的第一STI区域的第一上表面之上,其中第二上鳍延伸于接近第二上鳍的第二STI区域的第二上表面之上。半导体结构也包括第一介电膜,介于第一STI区域及第一长条半导体之间,以及介于第二STI区域及第二长条半导体之间,第一介电膜与第二长条半导体接触,以及一第二介电膜,介于第一长条半导体及第一介电层之间,第二介电层与第一长条半导体接触。
附图说明
以下将配合所附附图详述本公开的各面向。
图1至图11是根据一些实施例绘示的鳍式场效晶体管于各种制造阶段中的剖面图。
图12至图19是根据其他实施例绘示的鳍式场效晶体管于各种制造阶段中的剖面图。
图20是根据一些实施例绘示以本公开的方法所形成的半导体装置中掺质浓度的模拟结果。
图21为根据本公开的一些实施例绘示的一种半导体制造方法的流程图。
其中,附图标记说明如下:
100~半导体基板
101~第一区域
103~第二区域
110~基板
113~沟槽
120、120A、120B~鳍式半导体
120A’、120B’~上鳍
121A、121B~长条半导体
122、122A、122B~垫氧化层
123~虚线
124、124A、124B~垫氮化层
124A_t、124B_t~上表面
126~凹槽
129A、129B~抗接面击穿区
130、140、150~介电膜
150U、150UA、150UB~上表面
160~介电层
171、172、173~掩模层
210~退火工艺
220~低温退火工艺
230~阱区工艺
240、260、270、280~注入工艺
250~高温退火工艺
1000~流程图
1010、1020、1030、1040、1050~流程图步骤
2011、2013~曲线
a~偏移
W1~第一宽度
W2~第二宽度
具体实施方式
以下公开许多不同的实施方法或是例子来实行本公开的不同特征,以下描述具体的元件及其排列的实施例以阐述本公开。当然这些实施例仅用以例示,且不该以此限定本公开的范围。例如第一特征形成于第二特征之上,其包括第一特征与第二特征是直接接触的实施例,另外也包括于第一特征与第二特征之间另外有其他特征的实施例,亦即,第一特征与第二特征并非直接接触。另外,本公开在不同例子中可能重复使用相同的元件符号及/或标号。此重复的目的是为了简洁性与清楚性且除非另有说明,否则不代表所讨论的各种实施例和配置之间有特定的关系。
此外,其中可能用到与空间相关用词,例如“在…下方”、“下方”、“较低的”、“上方”、“较高的”及类似的用词,这些空间相关用词是为了便于描述图示中一个(些)元件或特征与另一个(些)元件或特征之间的关系,这些空间相关用词包括使用中或操作中的装置的不同方位,以及附图中所描述的方位。当装置被转向不同方位时(旋转90度或其他方位),则其中所使用的空间相关形容词也将依转向后的方位来解释。
本公开实施例的各面向涉及形成隔离区域于半导体装置中的方法与其结构,尤其是以可流动式化学气相沉积(flowable chemical vapor deposition,简称FCVD)于FinFET上形成STI区的方法与其结构。在一些实施例中,硅磷玻璃(phosphosilicate glass,简称PSG)膜及硅硼玻璃(borosilicate glass,简称BSG)膜分别形成于半导体装置中的PMOS区及NMOS区中的半导体鳍之上。可流动膜以FCVD工艺于鳍之间形成。在凹蚀可流动膜以形成有着大抵上平坦上的表面的STI区之前,先以注入工艺修改可流动膜的WER。以凹蚀工艺移除于STI区上表面之上的PSG膜和BSG膜。之后以高温热退火工艺于鳍下的长条半导体中形成抗接面击穿(anti-punch through,简称APT)区。
请参照图1,绘示有着延伸自基板110的多个鳍式半导体120A/120B(也称为鳍120A/120B)的半导体100装置的剖面图。于图1的例子中,半导体装置100有第一区域101及第二区域103。第一区域101可为用作制造p型半导体装置(如p型金属氧化物半导体场效晶体管(metal-oxide-semiconductor field-effect transistors,简称PMOSFETs))的PMOS区域101,及第二区域103可为用作制造n型半导体装置(如n型金属氧化物半导体场效晶体管(metal-oxide-semiconductor field-effect transistors,简称NMOSFETs))的NMOS区域103。虽然图1绘示两区域101及103且于其中分别有三片鳍120A/120B,半导体装置100可包含其他数目的鳍120A/120B及半导体区域,例如一或两个以上的区域,且半导体装置100的不同区域可为相同或不同种类(例如PMOS区或NMOS区)。为了说明的目的,随后的讨论以一PMOS区101及一NMOS区103为例子,本领域技术人士于阅读本公开后可应用本公开的原理于有任何鳍数量、其他数目和/或区域种类的半导体装置中。
请参照图1,基板110可为半导体基板,如块状半导体、绝缘体上半导体(semiconductor-on-insulator,简称SOI)基板或类似物,其可为已掺杂的(如以p型或n型掺质掺杂)或未掺杂的。基板110可为晶圆,如硅晶圆。通常来说,SOI基板包含形成于绝缘层上的一层半导体材料。举例来说,绝缘层可为埋氧(buried oxide,简称BOX)层、氧化硅层或类似物。提供隔离层于基板之上,通常为硅或玻璃基板。也可使用其他基板如多层或梯度基板。在一些实施例中,基板110的半导体材料可包含硅;锗;半导体化合物包含碳化硅、砷化镓、磷化镓、磷化铟、砷化铟,及/或锑化铟;半导体合金包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP,及/或GaInAsP;或其组合。半导体装置或如晶体管、电容、电阻、二极管或类似物等部分完成的半导体装置,可形成于基板110之上或之中。
为了形成多个鳍120(例如于PMOS区101中的鳍120A及NMOS区103中的鳍120B),可用如光刻技术图案化基板110。举例来说,可于基板110之上形成掩模层如垫氧化层122(如122A和122B)以及位于其之上的垫氮化层124(如124A及124B)。垫氧化层可为包含如使用热氧化工艺形成的氧化硅的薄膜。垫氧化层122可作为于其上的垫氮化层124及基板110间的接合层,且可作为蚀刻垫氮化层时的蚀刻停止层。于一些实施例中,垫氮化层124以氮化硅形成,例如以低压化学气相沉积(low-pressure chemical vapor deposition,简称LPCVD)或等离子体辅助化学气相沉积(plasma enhanced chemical vapor deposition,简称PECVD)形成。
掩模层可以光刻技术图案化。通常来说,光刻技术使用沉积的光致抗蚀剂材料(未显示),接着曝光,随后显影以去除部分光致抗蚀剂材料。残留的光致抗蚀剂材料于随后的工艺步骤中(如蚀刻)保护其下的材料(如于此例子中的掩模层)。于此例子中,图案化光致抗蚀剂材料以定义垫氧化层122及垫氮化层124,其共同包含区域101中图案化的掩模124A/122A及区域103中图案化的掩模124B/122B。
如图1所示,随后使用图案化后的掩模以图案化基板110中暴露的部分进而形成沟槽,如沟槽111和113,从而定义于相邻沟槽间的多个鳍120。如图1所示,于鳍120上设置图案化后的垫氧化层122(例如区域101中的122A和区域103中的122B)和图案化后的垫氮化层124(例如区域101中的124A和区域103中的124B)。于图1的例子中,沟槽113比沟槽111更进一步地延伸至基板110中,例如可通过更进一步蚀刻基板110中对应于沟槽113的部分。如图1所示,鳍120延伸自基板110的上表面110A。于图1中,基板110的上表面110B(其形成沟槽113的底部)低于上表面110A。沟槽113的深度被定义为鳍120的上表面与上表面110B的距离,于一些实施例中其值大约为于其他实施例中,鳍可由于基板上的介电层中的沟槽中外延成长的材料形成。
请参照图2,介电膜130形成于鳍120及基板110之上。介电膜130包含一或多种n型掺质,如磷、砷及类似的材料或其组合,且其由任何适当的沉积法形成,如化学气相沉积(chemical vapor deposition,简称CVD)或等离子体辅助化学气相沉积(plasma-enhancedCVD,简称PECVD)。于一示例性实施例中,介电膜130为含磷的膜,例如PSG膜。于随后的讨论中,膜130可被称为PSG膜130,应当理解也可使用其他适合的膜。于各种实施例中,PSG膜130可保形地形成于鳍120、图案化掩模122/124及基板110之上,且PSG膜130的厚度可介于大约1nm至大约6nm之间,虽然也可能为其他尺寸,取决于例如设计需求和/或使用的工艺技术(如40nm或28nm)。
接下来,如图3所示,以任何适合的去除工艺从NMOS区103去除PSG膜130,如以光刻和蚀刻。PMOS区101上的PSG膜130于去除工艺后仍残留下来,且将于随后的工艺中被用于形成抗接面击穿(anti-punch through,简称APT)区(如图11中的APT区129)。
请参照图4,介电膜140形成于PSG膜130、鳍120、图案化掩模122/124及基板110上。介电膜140包含一种或多种p型掺质,如硼,且由任何适合的沉积法如CVD或PECVD形成。于一示意性实施例中,介电膜140为包含硼的膜,如BSG膜。于接下来的讨论中,介电膜140可被称为BSG膜140,应当理解也可使用其他适合的膜。BSG膜140可保形化地形成。于各种实施例中,BSG膜的厚度可介于大约1nm至大约6nm之间,虽然也可能为其他尺寸,取决于例如设计需求和/或使用的工艺技术(如40nm或28nm)。须注意不须去除PMOS区域101中的BSG膜140,因PSG膜130可于随后的工艺中作为扩散阻挡层以降低或预防膜140的掺质(如硼)扩散至鳍120A中。
接下来,请参照图5,介电膜150形成于BSG膜140之上以填补沟槽(如图1中的沟槽111和113)。沉积的介电材料150可延伸于鳍120的上表面之上(如于BSG膜140的上表面之上)。于随后的工艺中,固化及凹蚀介电材料150以形成STI区,更多细节将会于随后描述。
介电膜150可由FCVD工艺形成。于FCVD工艺中,第一含硅前驱物被导入具有半导体装置100的沉积腔室中。于一些实施例中,含硅前驱物为聚硅氮烷(polysilazane)。聚硅氮烷为具有硅及氮原子交错排列基本结构的高分子。于聚硅氮烷中,每一硅原子通常与两氮原子键结,或每一氮原子与两硅原子键结,因此其主要可被描述为具有[R1R2Si-NR3]n结构的分子链。R1-R3可为氢原子或有机取代基。当只有氢原子作为取代基时,此高分子被称为全氢聚硅氮烷(perhydropolysilazanes)[H2Si-NH]n。若有机取代基与硅和/或氮键结,此化合物被称为有机聚硅氮烷(organopolysilazanes)。
于一些实施例中,含硅前驱物为硅烷胺(silylamine),如三硅烷胺(trisilylamine,简称TSA)、二硅烷胺(disilylamine,简称DSA)或其组合。含硅前驱物中也可包括一或多种载气。载气可包含氦(He)、氩(Ar)、氮(N2)及类似气体或其组合。
接下来,提供第二前驱物于沉积腔室中。于一些实施例中,第二前驱物为含氮的前驱物。含氮前驱物可包含氨(NH3)、氮(N2)及类似气体或其组合。于一些实施例中,含氮前驱物于沉积腔室外的远距等离子体系统(remote plasma system,简称RPS)中被激发成等离子体。含氮前驱物可包含氧源气体如O2或类似的气体且于RPS中被激发成等离子体。于一些实施例中,RPS中产生的等离子体被以如He、Ar、Ne及类似气体或其组合的载气带入沉积腔室中。
于沉积腔室中,含硅前驱物及含氮前驱物混合反应且于半导体装置100上沉积含硅和氮的膜150。于一些实施例中,沉积后的膜150有着可流动性。形成的可流动性令膜150可流动至半导体装置100的沉积表面上的狭窄之间隙、沟槽及其他结构之中。
继续参照图5,于一些实施例中,于FCVD沉积工艺之后进行退火工艺210以固化沉积后的膜150。在一些实施例中,退火工艺210为持续约数小时且进行于介于大约300℃及大约700℃温度的热退火工艺,如大约550℃。可使用干退火或湿退火。于一些实施例中,退火工艺有助于打断膜150中的Si-N及Si-H键且促进形成Si-Si及Si-O键。根据一些实施例,具有较多的Si-Si及Si-O键可改进介电膜150的机械性质,如硬度。由于沉积膜150的整体厚度,退火工艺210只能转化膜150的上部(如膜150中接近上表面的部分)以形成较强的Si-O键,因而至少改变膜150上部的机械性质(如硬度)。较硬的膜150可使随后用于凹蚀介电膜150的去除工艺较易进行,如化学机械平坦化(chemical mechanical planarization,简称CMP)工艺。
于图5中的退火工艺210,低温(例如介于大约300℃及大约700℃)退火被用于有效地降低或预防于此制造阶段中的界面氧化及掺质(如PSG膜130中的磷及BSG膜140中的硼)扩散至鳍120A/120B中。举例来说,低温退火工艺210降低或预防PSG膜130中的磷及BSG膜140中的硼扩散至对应的鳍120A及120B的沟道区中,进而降低或预防沟道区的伤害。然而低温退火工艺210可能导致较差的机械性能。举例来说,低温退火工艺之后的膜150的WER于大约为高温(例如大于1000℃)退火工艺后的膜的WER的两倍。若不处理,膜150可能会于随后的湿蚀刻工艺后出现凹陷区(divots,有时也称为dishing),造成STI区的不平上表面(也被称为鳍凹槽不均匀,fin recess non-uniformity)及鳍高不一致。如同本公开于随后描述的工艺,进行注入工艺240(请参阅图9)以改进膜150的机械和/或物理性质,从而降低或预防鳍凹槽不均匀。因此,本公开公开的方法同时有着低温退火以及预防或降低鳍凹槽不均匀的优点。
请参阅图6,进行平坦化工艺如CMP工艺以去除膜150的上部,进而达成大抵上水平的膜150的上表面。垫氮化层124A和124B可作为CMP工艺的蚀刻停止层。于一些实施例中,垫氮化层124A和124B的上表面124A_t和124B_t于CMP工艺后被暴露。于一些实施例中,于平面化工艺后进行另一低温退火工艺220,以进一步转化膜150的剩余部分且改进膜150的机械性质。可于与退火工艺210相似的条件下进行退火工艺220。举例来说,退火工艺220可为持续约数小时且进行于介于大约300℃及大约700℃的温度的热退火工艺,如大约550℃。可使用干退火或湿退火。
接下来,如图7所示,去除垫氮化层124A和124B,且形成暴露垫氧化层122A和122B的凹槽126。于一些实施例中,以不攻击其他层(如PSG膜130、BSG膜140及膜150)的去除工艺选择性地去除垫氮化层124A和124B。举例来说,垫氮化层124A/124B若由氮化硅形成,可由使用热磷酸的湿蚀刻工艺去除。
请参阅图8,以本领域已知的方法进行阱区工艺230以形成半导体装置100的阱区。阱区工艺230形成半导体装置100的p型阱及n型阱,且可包含依顺序进行的多个工艺步骤。工艺步骤可包括于PMOS区域101中形成n型阱,于此同时NMOS区域103被以如图案化的光致抗蚀剂层(未显示)遮蔽,和于NMOS区域101中形成p型阱,于此同时PMOS区域101被以如光致抗蚀剂的掩模层遮蔽。P型或n型掺质可用注入工艺注入以形成p型阱和n型阱。阱区工艺是本领域所已知的,因此细节将不予赘述。
接着请参照图9,进行注入工艺240以修改膜150的机械和/或物理性质(硬度和/或蚀刻速率,如WER)。于一示例性实施例中,He被用作注入工艺240的掺质,其以介于大约3keV及大约5keV之间的注入能量,介于大约200℃及大约500℃之间的温度,及介于大约1E15cm-2及大约1E16cm-2之间的剂量进行。于先前以He为掺质的实施例中,注入工艺240的投射范围(projectionrange,其描述膜150中具有峰值掺质浓度的区域从膜150的表面量起的深度)大约为注入工艺240中的精确材料改性(precise material modification,简称PMM)区描述在膜150中掺质浓度为峰值掺质浓度内区域的深度范围,其值为大约因此于先前的实施例中,具有峰值掺质浓度的区域大约于膜150之下自膜150表面延伸至大约深度为的区域具有峰值掺质浓度内的掺质浓度。
注入工艺240改进了膜150的性质。举例来说,膜150的WER于低温热退火工艺210/220之后大约为每分钟而膜150的WER以注入工艺240处理之后大约为每分钟因此在膜150的WER中达成大约两倍的改进,其可有利地于随后凹蚀膜150以形成STI区的工艺中降低鳍凹槽不均匀,如图10所示。由于He质量很小,于注入工艺240中,鳍120A/120B仅受到少量或未受到伤害。举例来说,于注入工艺后,鳍120A/120B仍维持直侧壁及平坦上表面,鳍120A/120B的侧壁和上表面间的夹角大抵上为直角。因此,通过使用低质量掺质如He,进而改善膜150的性质(如两倍的WER改进)且仅有少量或无因鳍伤害造成的装置效能衰退。于一些实施例中,掺质如He、O2、N2、C或其组合可被用为注入工艺240的掺质。先前提及的掺质仅为范例,于本实施例的范围中,也可使用其他可修改膜150的性质(如WER)且对鳍120仅造成少量或无伤害的合适掺质。此外,本领域技术人士将理解注入工艺240可被用于修改其他以FCVD工艺形成的层(如ILD层)的性质。
接下来请参照图10,以合适的蚀刻工艺(也被称为凹蚀工艺)凹蚀膜150,如以湿蚀刻工艺和/或干蚀刻工艺,且膜150于凹蚀工艺后的残留部分形成STI区150。于湿蚀刻工艺中,蚀刻剂如稀释的氢氟酸可被用于凹蚀膜150。于一些实施例中,稀释的氢氟酸也可于湿蚀刻工艺中去除垫氧化层122A/122B。于本公开的一些实施例中,以干蚀刻方法凹蚀膜150,其使用的工艺气体包含NH3和HF。于一些实施例中,于凹蚀工艺(如干蚀刻工艺和湿蚀刻工艺)中去除STI区150的上表面150U上的PSG膜130及BSG膜140的部分,若凹蚀工艺中所用的蚀刻剂不去除PSG膜130和/或BSG膜140,也可于凹蚀工艺后以一或多种可选择性地去除PSG膜130和/或BSG膜140的蚀刻剂去除它们。由于膜150改进后的性质(如改进后的WER),于凹蚀工艺后可获得STI区150大抵上平坦的上表面150U。在STI区150形成后,鳍120A/120B的上部120A’/120B’延伸于STI区150的上表面150U之上且被称为上鳍120A’和120B’,鳍120A/120B的下部121A/121B延伸于STI区150的上表面150U之下且被称为长条半导体121A和121B。图10及图18中的虚线123示意上鳍120A’/120B’和长条半导体121A/121B之间的边界。为了简化起见,虚线123将不会被绘示于所有图中的所有鳍中。
大抵平坦的STI区150的上表面150U减少鳍高L(其被定义为上鳍120A’(或120B’)的上表面及与上鳍120A’(或120B’)接触的STI区150上表面之间距离)的损耗。若无注入工艺240,于用以形成STI区150的凹蚀工艺(如湿蚀刻工艺)后,STI区150的上表面可能会凹陷,接触上鳍120A’/120B’的STI区部分会比位于两接邻鳍间的STI区高,因此造成鳍高的损失。由于注入工艺240形成大抵上平坦的上表面150U,其改善于PMOS区与CMOS区中鳍高的一致性,造成半导体装置100的启动电流Ion的改善及漏极电流Idrain较佳的均匀性。此外,STI区150大抵上平坦的上表面150U提供较佳的阱隔离及低漏电流。
接下来请参阅图11,以PVD、CVD、热氧化或其他适合的形成方法形成介电层160于上鳍120A’/120B’、PSG膜130、BSG膜140及STI区150之上。介电层160可包含氧化硅、氮化硅、高介电常数介电材料或其他适合的材料,且可于随后的工艺中用作栅极介电质以形成栅极(未显示)。于一些实施例中,在介电层160形成后,于介于大约1000℃及大约1300℃的温度范围,举例来说大约1045℃,及于介于大约20秒及大约40秒的时间之间进行热退火工艺250。于一些实施例中,用于热退火工艺250中的较高温度(如高于1000℃)驱动PSG膜130中n型掺质(如磷)及BSG膜140中p型掺质(如硼)以扩散的方式分别进入长条半导体121A和121B中。于各种实施例中,如图11所示,因PSG膜130和BSG膜140分别沉积于长条半导体121A和121B的侧壁上,n型掺质(如磷)和p型掺质(如硼)分别扩散进入长条半导体121A和121B中以形成APT区129A和129B。在图11中,仅绘示APT区129A/129B于PMOS区101中的一长条半导体121A及NMOS区103中的一长条半导体121B,应当理解所有的长条半导体121(如121A和121B)都可具有APT区129(如129A和129B)。应注意的是于PMOS区域101中,PSG膜130减少或预防了BSG膜140中的p型掺质扩散进入长条半导体121A中。本领域技术人士容易理解可进行进一步的工艺(未显示)以完成FinFET装置100的制造,且可包含额外的步骤如形成栅极、ILD及接触。
因为上鳍120A’/120B’的侧壁无PSG膜130或BSG膜140,PSG膜130及BSG膜140的掺质通过高温热退火工艺250扩散进入长条半导体121A/121B的中,而对于上鳍120A’/120B’中的掺质浓度仅有少量或无影响。
请暂时参照图20,进行工程用电脑辅助设计(Technology Computer-Aid Design,简称TCAD)模拟,以研究半导体装置100中于APT区129以本公开的方法生成后不同区域的掺质(如APT区129A中的磷及APT区129B中的硼)浓度。模拟结果以曲线2011表示。为了比较,以传统注入工艺生成APT区后的FinFET掺质浓度以曲线2013表示。图20的X轴代表半导体装置100的区域及上鳍120A’/120B’的上表面间的距离(单位为μm),负值代表此区域位于上鳍120A’/120B’的上表面之下。Y轴代表模拟的掺质浓度。因此于图20中,X轴上的点A对应上鳍120A’/120B’的上表面,点B对应上鳍120A’/120B’的底部,点C对应长条半导体121A/121B的底部。如图20中的曲线2011所示,于上鳍120A’/120B’及长条半导体121A/121B间的界面中(如X轴上的点B),从上鳍120A’/120B’至长条半导体121A/121B方向的掺质浓度有一阶梯状增加;于长条半导体121A/121B及基板110间的界面中(如X轴上的点C),从长条半导体121A/121B至基板110的掺质浓度有一大抵上阶梯状减少。曲线2011示意本公开方法的优点,其包含精确控制APT区129的位置。相较于传统以注入形成APT区域的方法(如曲线2013),本公开的方法有效地增加APT区域129中掺质浓度,且仅有少量或无因用于形成APT区129的掺质造成的沟道损伤或沟道迁移率的降低,这可由上鳍120A’/120B’及长条半导体121A/121B界面间掺质浓度的阶梯状增加所证明。
图12-图19示意本公开的另一实施例,其中分别于PMOS区域101及NMOS区域103进行不同的注入工艺270和280(请参阅图16及图17),以配合PMOS区域101及NMOS区域103中STI区域150的不同的蚀刻要求。除非另有说明,于图12-图19中与图1-图11类似元件符号通常被用来代表相似的部分。
请参照图12,其绘示有着自基板110延伸的多个半导体鳍120A/120B的半导体装置100的剖面图。于图12的例子中,半导体装置100有第一区域101和第二区域103。第一区域101可为用于制造p型半导体装置(如PMOSFET)的PMOS区域101,第二区域103可为用于制造n型半导体装置(如NMOSFET)的NMOS区域103。此外,第一区域101可用于形成逻辑装置且可含具第一宽度W1的多个第一鳍120A,且第二区域102可被用于形成输入-输出装置且可含具第二宽度W2的多个第二鳍120B。于图12的例子中,由于例如不同的设计和/或效能需求,第二宽度W2与第一宽度W1不同。于其他实施例中,W2可与W1相同。虽然图12仅显示两区域101和103,半导体装置100可包含其他数量的鳍120A/120B及其他数量的区域,如一个或大于两个区域,半导体装置100的不同区域可为相同或不同类型(如PMOS区或NMOS区)。为了示意,随后的讨论使用PMOS区101及NMOS区103为例子,本技术领域人士阅读本公开后应当可利用本公开的原理于有着其他数量和/或形态区域以及有着任何数量鳍的半导体装置。
如先前参考图1所述,鳍120A/120B可由如利用光刻和蚀刻的相似工艺形成,细节将不予赘述。于鳍120A/10B形成之后,形成沟槽113且其具有由鳍120A/120B的上表面量至基板110的上表面110B的深度H,其值可为大约
接下来请参照图13,PSG膜130使用和叙述于先前图2-图4相似的工艺形成于PMOS区101之上,且BSG膜140形成于PSG膜130及NMOS区103之上。
请参照图14,介电膜150以FCVD工艺形成于鳍120A/120B、PSG膜130、BSG膜140及基板110之上,接着以第一低温退火及平坦化工艺分别暴露垫氮化层124A和124B的上表面124A_t和124B_t,随后步骤与图5-图6中描述相似。相似于图6,可于平坦化工艺后进行第二低温退火。
接着如图15所示,去除垫氮化层124A/124B,进行半导体装置100的阱区工艺,随后步骤与图7-图8中描述相似。如图15所示,于PMOS区域101进行注入工艺260以形成n型阱,于此同时以掩模层171遮盖NMOS区域103以于注入工艺260中遮蔽NMOS区域103。须注意图15可仅表示一系列阱区工艺步骤中的一步。其他工艺步骤不绘示于图15中,如于NMOS区域103中形成P型阱的步骤。
接着请参照图16,于PMOS区域101进行注入工艺270,以修改沉积于区域101上的膜150的性质(如硬度和/或WER),于此同时NMOS区域103被掩模层172覆盖以遮蔽NMOS区域103于注入工艺270。掩模层172可为图案化的光致抗蚀剂层或其他适合作为掩模层的材料。于一些实施例中,注入工艺270利用He为掺质以及约为3eV的注入能量。注入工艺270的其他参数可与图9中的注入工艺240相似且可包含介于1E15cm-2及1E16cm-2之间的掺质浓度,及介于大约200℃及大约500℃之间的温度。于一些实施例中,注入工艺270降低膜150的WER。于其他实施例中,任何适合的掺质,如He、O2、N2、C和其组合可被当作于注入工艺270中的掺质,且注入能量可根据鳍高及其他设计参数而被调整至大于或小于3keV。
如图17所绘示,于图16的工艺后,于NMOS区域103进行另一注入工艺280以修改沉积于区域103的膜150的性质(如硬度和/或WER),于此同时PMOS区域101被掩模层173覆盖以遮蔽PMOS区域101于注入工艺280。掩模层173可为图案化的光致抗蚀剂层,且可包含与掩模层171相同的材料。于一些实施例中,注入工艺280利用He作为掺质及使用和注入工艺270中不同的注入能量。举例来说,可于注入工艺280使用大约2keV的注入能量。其他注入工艺的参数可相似于图9中的注入工艺240且可包含介于1E15cm-2及1E16cm-2之间的掺质浓度,及介于大约200℃及大约500℃之间的温度。于一些实施例中,注入工艺280降低了膜150的WER。于其他实施例中,任何适合的掺质,如He、O2、N2、C和其组合可被用于注入工艺280中的掺质,且注入能量可根据鳍高及其他设计参数而被调整至大于或小于2keV。此外,本领域技术人士将可理解注入技术270/280可被用于修改由FCVD工艺所形成的ILD层的性质。
通过使用不同的注入能量(如3keV和2keV)于沉积于区域101和103之上的膜150,沉积于区域101和103之上的膜150的性质被不同地修改。举例来说,区域101中的膜150因暴露于较高的注入能量下,可有和区域103中的膜150相比较慢的WER(如更耐抗随后的湿蚀刻工艺),而于区域101及区域103中的膜150都有较佳的WER,使得可由随后的去除工艺(如湿蚀刻工艺)去除膜150的上部获得大抵上水平的上表面,以形成STI区150。
请参照图18,类似于图10的工艺,以合适的工艺凹蚀膜150以形成STI区150,如使用合适的蚀刻剂的湿蚀刻工艺。于凹蚀工艺后,延伸于STI区150的上表面150UA/150U之上的鳍120A/120B的部分被称为上鳍120A’/120B’,延伸于STI区150的上表面150UA/150UB之下的部分的鳍120A/120B被称为长条半导体121A/121B。须注意由于沉积于区域101和103上的膜150被修改后的性质(如以注入工艺270/280修改后的WER)不同,区域101之中的上表面150UA不和区域103的上表面150UB等高。举例来说,上表面150UA可高于(进一步延伸自基板110)上表面150UB距离a(也称为偏移a),其值可为大约5nm,虽然也可能为其他尺寸,取决于如设计需求。于一些实施例中,虽然上表面150UA和150UB间有偏移a,因注入工艺270/280提供的改善后的WER,每一上表面150UA和150UB大抵上为水平。此偏移a可被用于有利地容纳半导体装置100不同区域中(如PMOS区域和NMOS区域)的不同鳍高设计需求。举例来说,可用不同鳍高平衡于PMOS及NMOS区域中不同型态装置的效能差异。也可使用偏移a补偿半导体装置100的负载效应,如于须于半导体装置的不同区域(有不同图案化密度的区域)中有同等鳍高。
本领域的技术人士将可理解上述公开方法的各种变化。举例来说,可由修改注入工艺270/280的其他参数达成沉积于区域101和103中的膜150的不同WER。可通过调整沉积于区域101和103的膜150的WER的差异达成其他的偏移a(如不同数值和/或不同正负号)。举例来说,虽然图16和图17示意于NMOS区103进行注入工艺280之前于PMOS区101进行注入工艺270,其工艺顺序可被调整且于工艺270前进行工艺280。此外,结合阱区工艺和注入工艺270/280是可能的,使得同样的掩模层可被用于阱区注入工艺以及随后用于修饰膜150的WER的注入工艺。举例来说,图15中的掩模层171可被用在于区域101的阱区注入工艺260时遮蔽区域103,之后可进行注入工艺270以利用掩模层171改变区域101中膜150的WER,以消除图16中形成掩模层172的步骤。于本公开的范围中,也可做其他变化或修改。
接着请参照图19,介电层160形成于区域101和区域103之上,随后是高温退火工艺250,接着是与图11中示意相似的步骤。与图11相似,于一些实施例中APT区域129A/129B以高温退火工艺250形成于长条半导体121A/121B中。于一些实施例中,半导体装置100的掺质(如PSG膜130中的磷和BSG膜140中的硼)浓度展示出如同图20示意的阶梯状增加与阶梯状减少。本公开的优势包含了精确控制APT区域129的位置,当与一般以注入形成APT区域的方法比较时,本公开的方法有效地增加APT区域129中的掺质浓度且仅有少量或无沟道伤害或沟道迁移率的降低。本领域技术人士可轻易理解,可进行进一步的工艺(未显示)以完成FinFET装置100的制造,及可包括额外的步骤如形成栅极电极、ILDs及接触。
虽然本公开的实施例使用有一PMOS区域及一CMOS区域的半导体装置为例,于本公开的范围中本领域技术人士将理解半导体装置100上区域组合(如区域的型态和数目)的各种变化是可能的。举例来说,半导体装置100可仅有一区域或多于两区域,及每一区域可为PMOS区域或NMOS区域。做为另一个例子,本公开的方法可被用于仅有一个或多个NMOS区域或仅有一个或多个PMOS装置的半导体装置100。
图21依据一些实施例示意制造介电膜方法的流程图。应当理解于图21中示意的实施例方法为许多可能的实施例方法中的一例子。本领域技术人员将可认知许多变化、替代及修改。举例来说,如图21所示意的各种步骤可被增加、减少、取代、重排及重复。
请参照图21,于步骤1010中,包括N型掺质的第一介电层形成于延伸于基板的第一区域之上的多个第一鳍之上。于步骤1020中,包括P型掺质的第二介电层形成于第一鳍及延伸于基板的第二区域上的多个第二鳍之上,第二介电层位于第一介电层之上。于步骤1030中,隔离层形成于接邻的第一鳍及接邻的第二鳍之间。于步骤1040中,注入工艺被以第一掺质进行,布值工艺改善隔离层的蚀刻速率。于步骤1050中,凹蚀隔离层、第一介电层及第二介电层,于凹蚀之后,第一鳍及第二鳍延伸于隔离层的上表面之上。
本公开的实施例可实现一些优点。本公开实施例的方法以低质量掺质(如He)修改以FCVD工艺形成的介电层的物理和/或机械性质(如硬度和/或WER)。因掺质的低质量,于介电层的性质被修改时,对半导体装置的鳍仅有少量或无损害。于一些实施例中可达成两倍的WER改进。改善的介电层性质造成大抵上平坦的以凹蚀介电层上部(如以湿蚀刻工艺)而形成的STI区上表面,进而降低或预防鳍凹槽不均匀。鳍高的均匀性被改善,进而改善半导体装置100的启动电流Ion及改善漏极电流Idrain的均匀性。此外,STI区的大抵上平坦的上表面提供较佳的阱隔离及低漏电流。额外的优点包含以控制注入工艺(如注入工艺270/280)参数而控制介电层性质的能力,以及控制APT区的位置及掺质浓度且对沟道迁移率仅有少量或无负面影响的能力。
依据一些实施例,一种半导体工艺方法包含形成包含N型掺质的第一介电层于第一鳍之上,第一鳍延伸于一基板的第一区域之上,形成包括P型掺质的第二介电层于第一鳍及第二鳍之上,第二鳍延伸于基板的第二区域之上,第二介电层位于第一介电层上,及形成隔离层,介于相邻的第一鳍之间,以及介于相邻的第二鳍之间。此方法更加包括以第一掺质进行第一注入工艺,注入工艺改变隔离层的蚀刻速率,以及凹蚀隔离层、第一介电层及第二介电层,其中在凹蚀之后,第一鳍及第二鳍延伸于隔离层的上表面之上。
依据一些实施例,一种形成FinFET装置的方法,包括形成PSG膜于基板的第一区域中的第一鳍上,形成BSG膜于PSG膜及基板的第二区域中的第二鳍上,形成介电层于基板中的第一区域及第二区域中及接邻第一鳍及第二鳍,及注入掺质于介电层中,其中注入降低介电层的蚀刻速率。
依据其他实施例,一种半导体结构包括第一上鳍,于基板的PMOS区域中的第一长条半导体之上,第二上鳍,于基板的NMOS区域中的第二长条半导体之上,及多个STI区,于每一第一鳍及第二鳍的相反侧,其中第一上鳍延伸于接近第一上鳍的第一STI区域的第一上表面之上,其中第二上鳍延伸于接近第二上鳍的第二STI区域的第二上表面之上。半导体结构也包括第一介电膜,介于第一STI区域及第一长条半导体之间,以及介于第二STI区域及第二长条半导体之间,第一介电膜与第二长条半导体接触,以及一第二介电膜,介于第一长条半导体及第一介电层之间,第二介电层与第一长条半导体接触。
如本公开一些实施例所述的半导体工艺方法,还包括:该第一介电层包括磷硅玻璃(phosphosilicate glass,简称PSG),且该第二介电层包括硅硼玻璃(borosilicateglass,简称BSG)。
如本公开一些实施例所述的半导体工艺方法,还包括:该注入工艺的进行降低该隔离层的该蚀刻速率。
如本公开一些实施例所述的半导体工艺方法,还包括:该隔离层由一可流动式化学气相沉积(flowable chemical vapor deposition,简称FCVD)工艺所形成。
如本公开一些实施例所述的半导体工艺方法,还包括:该隔离层的该形成包括:以该FCVD工艺沉积该隔离层于该些第一鳍及该些第二鳍之上,该隔离层延伸于该些第一鳍及该些第二鳍的上表面之上;于该沉积之后进行一第一热退火工艺;以及于该第一热退火工艺之后去除该隔离层的一上部,以暴露每一该些第一鳍及该些第二鳍的一第一掩模层。
如本公开一些实施例所述的半导体工艺方法,还包括:于该去除该隔离层的一上部之后进行一第二热退火工艺。
如本公开一些实施例所述的半导体工艺方法,还包括:该第一热退火工艺及该第二热退火工艺进行于介于大约300℃及大约700℃的一第一温度。
如本公开一些实施例所述的半导体工艺方法,还包括:于进行该注入工艺之前去除每一该些第一鳍及该些第二鳍的该第一掩模层。
如本公开一些实施例所述的半导体工艺方法,还包括:该注入工艺以一包含氦的掺质进行。
如本公开一些实施例所述的半导体工艺方法,还包括:该注入工艺以介于大约3keV及大约5keV之间的注入能量,介于大约1E15cm-2及大约1E16cm-2之间的剂量,及于介于大约200℃及大约500℃之间的温度进行。
如本公开一些实施例所述的半导体工艺方法,还包括:该注入工艺的进行包括:对于该隔离层的一第一部分以一第一布值能量进行一第一注入工艺,该第一部分置于该基板的该第一区域上,其中该隔离层的一第二部分屏蔽于该第一注入工艺,该第二部分置于该基板的该第二区域之上;以及对于该隔离层的一第二部分以一小于该第一注入能量的第二注入能量进行一第二注入工艺,其中该隔离层的第一部分屏蔽于该第二注入工艺。
如本公开一些实施例所述的半导体工艺方法,还包括:于该凹蚀之后,该些第一鳍的一第一鳍高大于该些第二鳍的一第二鳍高。
如本公开另一些实施例所述的形成鳍式场效晶体管(Fin Field-Effect,简称FinFET)装置的方法,其包括:形成一第一鳍于一基板的一第一区域中;形成一介电层于该基板之上以及于该第一鳍的相反侧;以及注入一掺质于该介电层之中,其中该注入降低该介电层的一蚀刻速率,其中该掺质择自由氦、氮、氧及碳所组成的群组。
如本公开另一些实施例所述的形成鳍式场效晶体管装置的方法,还包括:该介电层由一FCVD工艺形成。
如本公开另一些实施例所述的形成鳍式场效晶体管装置的方法,还包括:该注入于介于大约3keV及大约5keV之间的注入能量,介于大约1E15cm-2及大约1E16cm-2之间的剂量,及介于大约200℃及大约500℃之间的温度进行。
如本公开另一些实施例所述的形成鳍式场效晶体管装置的方法,还包括:形成一第二鳍于该基板的一第二区域之上;其中该介电层注入于该第二鳍的相反侧上;其中该注入包括:进行一第一注入工艺,以一第一注入能量于该基板的一第一区域之中进行,该基板的该第二区域以一第二注入掩模覆盖;以及进行一第二注入工艺,以小于该第一注入能量的一第二注入能量于该基板的该第二区域中进行,该基板的该第一区域以一第一注入掩模覆盖。
如本公开另一些实施例所述的形成鳍式场效晶体管装置的方法,还包括:凹蚀该介电层以暴露该第一鳍及该第二鳍的上部,其中该凹蚀去除一于该第一区域中的该介电层的第一部分,以及一于该第二区域中的该介电层的第二部分,其中该第一部分的一第一厚度较该第二部分的一第二厚度小。
如本公开又一些实施例所述的半导体结构,其包括:一第一上鳍,于一基板的一PMOS区域中的一第一长条半导体之上;一第二上鳍,于该基板的一NMOS区域中的一第二长条半导体之上;多个浅沟槽隔离(shallow trench isolation,简称STI)区,于每一该些第一鳍及该些第二鳍的相反侧,其中该第一上鳍延伸于接近该第一上鳍的一第一STI区域的一第一上表面之上,其中该第二上鳍延伸于接近该第二上鳍的一第二STI区域的一第二上表面之上;一第一介电膜,介于该第一STI区域及该第一长条半导体之间,以及介于该第二STI区域及该第二长条半导体之间,该第一介电膜与该第二长条半导体接触;以及一第二介电膜,介于该第一长条半导体及该第一介电层之间,该第二介电层与该第一长条半导体接触。
如本公开又一些实施例所述的半导体结构,还包括:该第一介电膜包括一P型掺质,且其中该第二介电膜包括一N型掺质。
如本公开又一些实施例所述的半导体结构,还包括:于该第一长条半导体及该第二长条半导体之中有多个抗接面击穿(anti-punch through,简称APT)区,其中该第一STI区的该第一上表面相较于该第二STI区的该第二上表面自基板延伸得更远。
虽然此发明参考示例性实施例进行描述,但此描述并非旨在以限制性的意义来解释。各种示例性实施例及其组合和本公开的其他实施例对于本领域技术人士是显而易见的。因此,所附权利要求旨在包括任何这样的修改或实施例。

Claims (1)

1.一种半导体工艺方法,包括:
形成一包括一N型掺质的第一介电层于多个第一鳍之上,所述多个第一鳍延伸于一基板的一第一区域之上;
形成一包括一P型掺质的第二介电层于所述多个第一鳍及多个第二鳍之上,所述多个第二鳍延伸于该基板的一第二区域之上,该第二介电层位于该第一介电层上;
形成一隔离层,介于相邻的所述多个第一鳍之间,以及介于相邻的所述多个第二鳍之间;
以一第一掺质进行一第一注入工艺,该注入工艺改变该隔离层的一蚀刻速率;以及
凹蚀该隔离层、该第一介电层及该第二介电层,其中在凹蚀之后,所述多个第一鳍及所述多个第二鳍延伸于该隔离层的上表面之上。
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