CN111341847A - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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CN111341847A
CN111341847A CN201811557549.5A CN201811557549A CN111341847A CN 111341847 A CN111341847 A CN 111341847A CN 201811557549 A CN201811557549 A CN 201811557549A CN 111341847 A CN111341847 A CN 111341847A
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fin
groove
doped
recess
semiconductor structure
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CN111341847B (zh
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王智亿
许田昇
邱诚朴
王尧展
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United Microelectronics Corp
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United Microelectronics Corp
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Abstract

本发明公开一种半导体结构及其制作方法，其中该半导体结构包含一基底、多个相互平行的鳍部从该基底凸出且由沟槽所分隔、以及一元件隔离层位于两个该鳍部之间的该沟槽之上，其中该沟槽具有位于中央的第一沟槽以及位于该第一沟槽两侧的两个第二沟槽，该第一沟槽的深度低于该第二沟槽的深度，且该元件隔离层具有一顶面、一第一凹槽以及一第二凹槽，而该鳍部从该顶面凸出，该第二凹槽的底面低与第一凹槽的底面。

Description

半导体结构及其制作方法
技术领域
本发明涉及一种半导体结构有关，更确切地说，其涉及一种具有特殊元件隔离层的半导体结构及其形成方法。
背景技术
现今的金属氧化物半导体场效晶体管(metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET)是一种广泛使用在模拟电路与数字电路的场效晶体管，其不论在使用面积、操作速度、耗损功率、以及制造成本等方面都比以往的双载流子晶体管(Bipolar Junction Transistor,BJT)更具优势，故获得业界广泛应用。互补式金属氧化物半导体(complementary MOS,CMOS)则是在硅质晶片上同时制作出NMOS(n-type MOSFET)和PMOS(p-type MOSFET)的基本元件，由于NMOS与PMOS在物理特性上为互补性，因此被称为CMOS。CMOS制作工艺可用来制作电子产品的静态随机存取存储器、微控制器、微处理器与其他数字逻辑电路系统。此外，由于其技术特性，使它也可以用于光学仪器的制作上，例如互补式金属氧化物半影像感测器(CMOS image sensor,CIS)常见于一些高级数字相机中。
随着MOSFET技术的演进，当栅极长度缩小到20纳米(nm)以下的时候，由于源极和漏极的距离过近，漏电流的问题会变得益加严重，而且栅极长度的缩减也使得其对通道的接触面积变小，使得栅极对通道的影响力变小。为了解决此问题，业界开发出了立体的鳍式场效晶体管(FinFET)结构，其鳍部设计可以增加栅极与通道的接触面积，故能解决上述问题。
发明内容
本发明即为提出一种具有特殊元件隔离层的鳍式场效晶体管(FinFET)结构，其元件隔离层具有特殊的凹槽特征。
本发明的其一目的在于提出一种半导体结构，其结构包含一基底、多个相互平行的鳍部从该基底凸出且由沟槽所分隔、以及一元件隔离层位于两个该鳍部之间的该沟槽之上，其中该沟槽具有位于中央的第一沟槽以及位于该第一沟槽两侧的两个第二沟槽，该第一沟槽的深度低于该第二沟槽的深度，且该元件隔离层具有一顶面、一第一凹槽以及一第二凹槽，该鳍部从该顶面凸出，且该第二凹槽的底面低于第一凹槽的底面。
本发明的另一目的在于提出一种半导体结构的制作方法，其步骤包含：提供一基底，其中该基底上界定有第一区域与第二区域，多个相互平行的鳍部从该基底凸出，且该鳍部之间具有元件隔离层；在该基底的第一区域上覆盖光致抗蚀剂并进行第一蚀刻制作工艺，以在该元件隔离层中形成第一凹槽；以及在该基底的第二区域上覆盖光致抗蚀剂并进行第二蚀刻制作工艺，以在该元件隔离层中形成第二凹槽，其中该第二凹槽的底面低于第一凹槽的底面。
本发明的这类目的与其他目的在阅者读过下文以多种图示与绘图来描述的优选实施例细节说明后必然可变得更为明了显见。
附图说明
本说明书含有附图并于文中构成了本说明书的一部分，使阅者对本发明实施例有进一步的了解。该些图示描绘了本发明一些实施例并连同本文描述一起说明了其原理。在该些图示中：
图1为本发明优选实施例中一半导体结构的示意性顶视图；
图2至图5为本发明优选实施例中该半导体结构的制作流程在鳍部的长度方向的截面示意图；以及
图6为本发明优选实施例中该半导体结构在鳍部的宽度方向的截面示意图。
需注意本说明书中的所有图示都为图例性质，为了清楚与方便图示说明之故，图示中的各部件在尺寸与比例上可能会被夸大或缩小地呈现，一般而言，图中相同的参考符号会用来标示修改后或不同实施例中对应或类似的元件特征。
主要元件符号说明
100 基底
101 第一区域
102 第二区域
104a 鳍部
104b 鳍部
106 栅极
106a n通道型场效晶体管
106b p通道型场效晶体管
107 共形层
108 元件隔离层
108a 顶面
108b 第一凹槽
108c 第二凹槽
109 介电层
110 光致抗蚀剂
112 凹槽
114 外延结构
116 介电层
118 光致抗蚀剂
120 外延结构
122 顶盖层
124 空洞
126 第一沟槽
128 第二沟槽
130 第三沟槽
D1 第一方向
D2 第二方向
E1 蚀刻制作工艺
E2 蚀刻制作工艺
具体实施方式
在下文的本发明细节描述中，元件符号会标示在随附的图示中成为其中的一部分，并且以可实行该实施例的特例描述方式来表示。这类的实施例会说明足够的细节以使该领域的一般技术人士得以具以实施。为了图例清楚之故，图示中可能有部分元件的厚度会加以夸大。阅者需了解到本发明中也可利用其他的实施例或是在不悖离所述实施例的前提下作出结构性、逻辑性、及电性上的改变。因此，下文的细节描述将不欲被视为是一种限定，反之，其中所包含的实施例将由随附的权利要求来加以界定。
一般而言，文中的术语可以至少部分地根据上、下文中的用法来理解。例如，如本文所使用的术语「一或多个」可用于以单数意义描述任何特征、结构或特性，或可用于描述特征、结构或特征的多个组合，至少可部分取决于上、下文。类似地，术语诸如「一」、「一个」或「该」也可以被理解为表达单数用法或传达多个用法，至少可部分取决于上、下文。
应该容易理解的是，本文中的「在...上面」、「在...之上」及「在...上方」的含义应该以最宽泛的方式来解释，使得「在...上面」不仅意味着「直接在某物上」，而且还包括在某物上且两者之间具有中间特征或中间层，并且「在...之上」或「在...上方」不仅意味着在某物之上或在某物上方的含义，而且还可以包括两者之间没有中间特征或中间层(即，直接在某物上)的含义。
在说明优选实施例之前，通篇说明书中会使用特定的词汇来进行描述。例如文中所使用的「蚀刻」一词一般是用来描述图形化一材料的制作工艺，如此制作工艺完成后至少会有部分的该材料余留下来。须了解蚀刻硅材料的制作工艺都会牵涉到在硅材料上图形化一光致抗蚀剂层的步骤，并在之后移除未被光致抗蚀剂层保护的硅区域。如此，被光致抗蚀剂层保护的硅区域会在蚀刻制作工艺完成后保留下来。然而在其他例子中，蚀刻动作也可能指的是不使用光致抗蚀剂层的制作工艺，但其在蚀刻制作工艺完成后仍然会余留下来至少部分的目标材料层。
上述说明的用意在于区别「蚀刻」与「移除」两词。当蚀刻某材料时，制作工艺完成后至少会有部分的该材料于留下来。相较之下，当移除某材料时，基本上所有的该材料在该制作工艺中都会被移除。然而在某些实施例中，「移除」一词也可能会有含括蚀刻意涵的广义解释。
如本文所使用者，术语「基底」是指在其上添加后续材料层的材料。基底本身可以被图案化。添加在基底顶部的材料可以被图案化或可以保持未图案化。文中所说明的「基底」、「半导体基底」或「晶片」等词通常大多为硅基底或是硅晶片。然而，「基底」、或「晶片」等词也可能指的是任何半导体材质，诸如锗、砷化锗、磷化铟等种类的材料。在其他实施例中，「基底」、或「晶片」等词也可能指的是非导体类的玻璃或是蓝宝石基板等材料。
请参照图1，其为根据本发明优选实施例中一半导体结构的示意性顶视图。首先提供一基底100，如一硅基底，作为整个半导体结构的基础。基底100上会预先界定有第一区域101与第二区域102，如n通道型(NMOS)区域与p通道型(PMOS)区域两不同半导体特性的主动(有源)区域，其彼此邻接。在实施例中，第一区域101与第二区域102的界定可以通过在基底100中掺杂离子来形成井区的方式而达成。例如在一p型基底上掺杂磷、砷等n型掺质的方式来界定出不同的半导体区域。
再者，基底100上形成有多个相互平行的鳍部(fin)特征，其从基底表面向上凸出且往一第一方向D1延伸。第一区域101与第二区域102会分别含括多条鳍部，例如分别含括多条p型掺杂的鳍部104a或多条n型掺杂的鳍部104b。鳍部104a,104b可经由对基底进行光刻与蚀刻制作工艺的方式来形成。基底100上还形成有多条栅极106，其往一第二方向D2延伸并横跨多条鳍部104a,104b，第二方向D2较佳与第一方向D1正交。栅极106可经由在基底100与鳍部104a,104b上形成一材料层，如多晶硅层，再进行光刻与蚀刻制作工艺来图案化材料层的方式而形成。栅极106与鳍部104a,104b之间还会形成一栅介电层(未示出)来隔离栅极106与鳍部。
现在请参照图2，其为根据本发明优选实施例中一半导体结构的截面示意图，其描绘出第一区域101与第二区域102上一p型掺杂的鳍部104a或一n型掺杂的鳍部104b在长度方向的截面态样。如图2所示，p型掺杂的鳍部104a与n型掺杂的鳍部104b之间形成有一元件隔离层108，如氧化硅层，其隔绝该两不同的鳍部。元件隔离层108具有一顶面108a，鳍部104a与104b是从该顶面108a凸出。多条栅极设置在鳍部104a与104b的上方，从而构成了场效晶体管结构，如n通道型场效晶体管(NMOS)106a与p通道型场效晶体管(PMOS)106b结构。晶体管106a与106b的上方还形成有一共形层107，如氮化硅层，其可覆盖住栅极结构的侧壁并在后续形成间隔壁(spacer)。
接下来请参照图3。为了在栅极结构的两旁形成源极与漏极，如图3所示，先进行一光刻制作工艺在基底的第二区域102(如PMOS区域)上覆盖一层图案化光致抗蚀剂110，之后以光致抗蚀剂110以及栅极106为蚀刻掩模进行一蚀刻制作工艺E1，如一各向异性制作工艺，来蚀刻裸露出的鳍部，如此即能在第一区域101(如NMOS区域)栅极106两侧的鳍部104a上形成凹槽112。此蚀刻制作工艺E1也会使得栅极106上的共形层107变为栅极两侧的间隔壁。为了提供平坦的涂覆面，在形成图案化光致抗蚀剂110之前可以先在第二区域102的栅极106上形成一平坦化的介电层109。需注意在本发明实施例中，除了鳍部以外，此蚀刻制作工艺E1同时也会蚀刻两区域交界处裸露出的元件隔离层108部位，在其上形成了一第一凹槽108b。第一凹槽108b的一侧由于以栅极106为部分蚀刻掩模之故，而会具有该顶面108a。
接下来请参照图4。在鳍部104a上形成凹槽112后，接下来可进行一外延制作工艺在第一区域101的凹槽112中生长外延结构114作为晶体管的源极与漏极。以n通道型场效晶体管(NMOS)为例，外延结构114的材料可为碳化硅(SiC)或磷化硅(SiP)，其可提供邻近的n通道应力来产生应变硅效果，改善通道的载流子移动率。在形成外延结构114后，同样在栅极106与外延结构114上形成一介电层116，以提供平坦的涂覆面。之后，为了在栅极结构的两旁形成源极与漏极，如图4所示，先进行一光刻制作工艺在基底第一区域101(如NMOS区域)的介电层116上形成另一图案化光致抗蚀剂118，之后以光致抗蚀剂118以及栅极106为蚀刻掩模进行另一蚀刻制作工艺E2，如一各向异性制作工艺，来蚀刻裸露出的鳍部，如此即能在第二区域102(如PMOS区域)栅极106两侧的鳍部104b上形成凹槽112。此蚀刻制作工艺E2也会使得栅极106上的共形层107变为栅极两侧的间隔壁。
需注意在本发明实施例中，除了鳍部以外，此蚀刻制作工艺E2同时也会蚀刻两区域交界处裸露出的元件隔离层108部位，在其上形成了一第二凹槽108c。第二凹槽108c的一侧由于以栅极106为部分蚀刻掩模之故，而会具有该顶面108a。第二凹槽108c与第一凹槽108b邻接，且由于蚀刻制作工艺E2要在第二区域102的鳍部104b上形成较大的凹槽112之故，其所形成的第二凹槽108c的底面也会较蚀刻制作工艺E1所形成的第一凹槽108b的底面来的深。
接下来请参照图5。在第二区域102的鳍部104b上形成凹槽112后，接下来可进行另一外延制作工艺在第二区域102的凹槽中生长外延结构120作为晶体管的源极与漏极。以p通道型场效晶体管(PMOS)为例，外延结构120的材料可为硅锗(SiGe)，其可提供邻近的p通道应力来产生应变硅效果，改善通道的载流子移动率。之后可以将第一区域101上的介电层116与图案化光致抗蚀剂118都移除，如此即形成了图5所示的半导体结构，其包含n通道型场效晶体管(NMOS)106a与p通道型场效晶体管(PMOS)106b结构分别形成在第一区域101的p型掺杂鳍部104a上与第二区域102的n型掺杂鳍部104b上，该p型掺杂鳍部104a与该n型掺杂鳍部104b之间设有元件隔离层108，其具有相邻的一第一凹槽108b与一第二凹槽108c，第一凹槽108b与一第二凹槽108c的两侧分别具有平坦的顶面108a，其中鳍部104a与104b是从该顶面108a凸出，且该第二凹槽108c的底面低于第一凹槽108b的底面。
接下来请参照图6，其为根据本发明优选实施例中一半导体结构的截面示意图，其描绘出第一区域101与第二区域102上多个p型掺杂鳍部104a与n型掺杂鳍部104b在宽度方向的截面态样。如图6所示，p型掺杂鳍部104a与n型掺杂鳍部104b上分别形成有外延结构(如SiP)114与外延结构(如SiGe)120，其中，位于两种不同外延结构114与120之间的元件隔离层108也具有前述特征，即一第一凹槽108b以及一第二凹槽108c，其中该第二凹槽108c的底面低于第一凹槽108b的底面。相同外延结构114或120之间的元件隔离层108则不具备如此的双凹槽特征。
此外要注意的是，在本发明实施例中，形成外延结构114与120后会在整个基底表面形成一共形的顶盖层(capping layer)122，其会覆盖第一区域101上的外延结构114以及元件隔离层108。其中顶盖层122会封住部分较为相邻的p型掺杂鳍部104a之间的开口，而在两者间形成一空洞124。在此实施例中，第二区域102以及其上的外延结构120则不会被顶盖层122所覆盖。
另一方面，如图6所示，在本发明实施例中，基底100上除了突出的主动鳍部104a,104b以外，还会形成有第一沟槽126、第二沟槽128、以及第三沟槽130等部位。第一沟槽126与第二沟槽128是在使基底100产生凹陷来形成主动鳍部104a,104b时形成的，两者深度相同，其侧面可为鳍部104a或104b的侧壁，其中第一沟槽126位于该两较为相邻的p型掺杂鳍部104a之间。第三沟槽130可在形成第二沟槽128后再次使第二沟槽128产生凹陷而形成在两第二沟槽128之间，故其深度低于第二沟槽128与第一沟槽126。第三沟槽130可用于区隔不同的主动区块，不同主动区块可能会有不同的掺质类型或是掺杂浓度。例如如图中所示位于两第三沟槽130之间的一对主动鳍部104a或是单一主动鳍部104b。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (20)

1.一种半导体结构，其特征在于，包含：
基底；
多个相互平行的鳍部，从该基底凸出且由沟槽所分隔；以及
元件隔离层，位于两个该鳍部之间的该沟槽之上，其中该沟槽具有位于中央的第一沟槽以及位于该第一沟槽两侧的两个第二沟槽，该第一沟槽的深度低于该第二沟槽的深度，且该元件隔离层具有顶面、第一凹槽以及第二凹槽，其中该鳍部从该顶面凸出，该第二凹槽的底面低于该第一凹槽的底面。
2.如权利要求1所述的半导体结构，其中该第一凹槽与该第二凹槽相接。
3.如权利要求2所述的半导体结构，其中两个该鳍部之间依序包含该顶面、该第一凹槽、该第二凹槽、以及该顶面。
4.如权利要求1所述的半导体结构，其中该基底上界定有相邻的n通道型区域与p通道型区域，该n型通道区域包含多个p型掺杂的该鳍部，该p型通道区域包含n型掺杂的该鳍部。
5.如权利要求4所述的半导体结构，其中该元件隔离层位于相邻的一该p型掺杂的鳍部与一该n型掺杂的鳍部之间。
6.如权利要求5所述的半导体结构，其中相邻的该n型掺杂的鳍部之间的该沟槽为第三沟槽，该第三沟槽的深度与该第二沟槽的深度相同。
7.如权利要求5所述的半导体结构，还包含外延结构分别形成在该n型掺杂的鳍部与该p型掺杂的鳍部上。
8.如权利要求7所述的半导体结构，其中形成在该n型掺杂的鳍部上的外延结构的材质为磷化硅(SiP)或碳化硅(SiC)，形成在该p型掺杂的鳍部上的外延结构的材质为硅锗(SiGe)。
9.如权利要求7所述的半导体结构，其中该元件隔离层位于相邻的一形成在该n型掺杂的鳍部上的外延结构与一形成在该p型掺杂的鳍部上的外延结构之间。
10.如权利要求7所述的半导体结构，还包含顶盖层(capping layer)，形成在该n型掺杂的鳍部上的外延结构上，其中该顶盖层封住相邻的该n型掺杂的鳍部上的外延结构之间的开口。
11.一种半导体结构的制作方法，包含：
提供基底，其中该基底上界定有第一区域与第二区域，多个相互平行的鳍部从该基底凸出，且该鳍部之间具有元件隔离层；
在该基底的该第一区域上覆盖光致抗蚀剂并进行第一蚀刻制作工艺，以在该元件隔离层中形成第一凹槽；以及
在该基底的该第二区域上覆盖光致抗蚀剂并进行第二蚀刻制作工艺，以在该元件隔离层中形成第二凹槽，其中该第二凹槽的底面低与第一凹槽的底面。
12.如权利要求11所述的半导体结构的制作方法，其中该第一凹槽与该第二凹槽相接。
13.如权利要求12所述的半导体结构的制作方法，其中两个该鳍部之间依序包含该顶面、该第一凹槽、该第二凹槽、以及该顶面。
14.如权利要求11所述的半导体结构的制作方法，其中该第一区域与该第二区域分别为n通道型区域与p通道型区域，该n通道型区域包含多个p型掺杂的该鳍部，该p通道型区域包含多个n型掺杂的该鳍部。
15.如权利要求14所述的半导体结构的制作方法，其中该元件隔离层位于相邻的一该p型掺杂的鳍部与一该n型掺杂的鳍部之间。
16.如权利要求14所述的半导体结构的制作方法，其中该第一蚀刻制作工艺与该第二蚀刻制作工艺也分别在该p型掺杂的鳍部与该n型掺杂的鳍部上形成凹槽。
17.如权利要求16所述的半导体结构的制作方法，还包含在该n型掺杂的鳍部的该凹槽中与该p型掺杂的鳍部的该凹槽中分别形成外延结构。
18.如权利要求17所述的半导体结构的制作方法，其中该元件隔离层位于相邻的一形成在该n型掺杂的鳍部上的外延结构与一形成在该p型掺杂的鳍部上的外延结构之间。
19.如权利要求17所述的半导体结构的制作方法，其中形成在该n型掺杂的鳍部上的外延结构的材质为磷化硅(SiP)，形成在该p型掺杂的鳍部上的外延结构的材质为硅锗(SiGe)。
20.如权利要求17所述的半导体结构的制作方法，还包含顶盖层(capping layer)，形成在该n型掺杂的鳍部上的外延结构上，其中该顶盖层封住相邻的该n型掺杂的鳍部上的外延结构之间的开口。
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