CN107768439B - 非对称闭锁双向氮化镓开关 - Google Patents
非对称闭锁双向氮化镓开关 Download PDFInfo
- Publication number
- CN107768439B CN107768439B CN201710672810.5A CN201710672810A CN107768439B CN 107768439 B CN107768439 B CN 107768439B CN 201710672810 A CN201710672810 A CN 201710672810A CN 107768439 B CN107768439 B CN 107768439B
- Authority
- CN
- China
- Prior art keywords
- layer
- gan
- source
- gate
- drain electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 88
- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 72
- 230000002457 bidirectional effect Effects 0.000 title claims abstract description 36
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- 230000000903 blocking effect Effects 0.000 claims abstract description 17
- 230000005533 two-dimensional electron gas Effects 0.000 claims abstract description 5
- 229910002704 AlGaN Inorganic materials 0.000 claims description 31
- 239000000758 substrate Substances 0.000 claims description 24
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- 229910052759 nickel Inorganic materials 0.000 claims description 7
- 229910052594 sapphire Inorganic materials 0.000 claims description 7
- 239000010980 sapphire Substances 0.000 claims description 7
- 229910052719 titanium Inorganic materials 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims 1
- 238000000034 method Methods 0.000 description 43
- 238000002161 passivation Methods 0.000 description 32
- 230000004888 barrier function Effects 0.000 description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 18
- 229910052681 coesite Inorganic materials 0.000 description 9
- 229910052906 cristobalite Inorganic materials 0.000 description 9
- 239000000377 silicon dioxide Substances 0.000 description 9
- 235000012239 silicon dioxide Nutrition 0.000 description 9
- 229910052682 stishovite Inorganic materials 0.000 description 9
- 229910052905 tridymite Inorganic materials 0.000 description 9
- 238000013461 design Methods 0.000 description 8
- 239000012212 insulator Substances 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- 229910004298 SiO 2 Inorganic materials 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 230000009977 dual effect Effects 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 238000005530 etching Methods 0.000 description 6
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- MLLWPVVMXGUOHD-QNUMDXCLSA-N levuglandin D2 Chemical compound CCCCC[C@H](O)\C=C\[C@@H](C(C)=O)[C@H](C=O)C\C=C/CCCC(O)=O MLLWPVVMXGUOHD-QNUMDXCLSA-N 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
- H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1066—Gate region of field-effect devices with PN junction gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Materials Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
一种高电子迁移率晶体管(HEMT)氮化镓(GaN)双向闭锁器件包括一个异质结结构,包括两个不同带隙的第一半导体层和第二半导体层相交接,从而将交界面层制成一个二维电子气(2DEG)层。HEMT GaN双向闭锁器件还包括一个第一源极/漏极电极和一个第二源极/漏极电极,位于所述的异质结结构上方的栅极电极的两个对边上,用于控制2DEG层中第一和第二源极/漏极电极之间的电流,其中栅极电极与第一源极/漏极电极相距第一距离,与第二源极/漏极电极相距第二距离,第一距离不同于第二距离。
Description
技术领域
本发明主要关于半导体功率器件的制备工艺及结构。更确切地说,本发明是关于非对称闭锁氮化镓(GaN)开关。
背景技术
配置和制备氮化镓(GaN)基场效应晶体管(FET)的传统方法,仍然面临提供双向非对称闭锁性能用作双向开关的技术困难。经常需要提供横向GaN基非对称闭锁功能,用于直流高压降压转换器和双升压无桥PFC等器件。
然而,由于闭锁开关传统应用的局限性,无法实现非对称闭锁的优势。确切地说,对于双向开关应用来说,通常配置RB-IGBT器件和对称双向闭锁GaN开关。硅基双向闭锁器件为垂直器件,从本质上说是对称的。如图1A、1B、1C、1D和1E所示的GaN器件通常优化对称闭锁性能,对称闭锁性能由Rds,on设置,反之由对称场镀电容显示。
因此,有必要提出带有非对称闭锁性能的双向GaN闭锁开关的新型改良器件结构和制备方法,从而克服上述困难与局限。
发明内容
因此,本发明的一个方面在于,提出了提供高电子迁移率晶体管(HEMT)功率器件的新型改良器件结构和制备方法,具有非对称双向闭锁开关的功能,从而解决上述难题与局限。
确切地说,本发明的一个方面在于提出了半导体GaN基HEMT功率器件的改良器件结构和制备方法,具有非对称双向闭锁功能,用于切换不对称电压应力,使得Rds-on和电容损耗最低,从而降低常用于传统设计的对称闭锁开关中不必要的损耗。
本发明的另一方面在于提出了GaN基高电子迁移率晶体管(HEMT)功率器件改良的器件结构和制备方法,该功率器件具有优化的横向结构,用于设计和制备非对称闭锁开关,使得具有不同寄生电感的常用布局限制,使得更好地理解和控制非对称闭锁和非对称电压过冲,作为设计和制备工艺的一部分。
本发明的另一方面在于提出了具有非对称闭锁性能的半导体GaN基HEMT功率器件改良的器件结构和制备方法,通过配置单独的或双栅极结构,使得开关器件的切换功能和性能可以更加灵活、方便地控制。
本发明的较佳实施例主要提出了一种高电子迁移率晶体管(HEMT)氮化镓(GaN)双向闭锁器件,包括一个异质结结构,由一个第一半导体层交界两个不同带隙的第二半导体层,从而生成一个交界面层,作为二维电子气(2DEG)层。HEMT GaN双向闭锁器件还包括一个第一源极/漏极电极和一个第二源极/漏极,位于异质结结构上方的栅极电极两个不同的边上,用于控制2DEG层中第一和第二个源极/漏极电极之间的电流流动,其中栅极电极位于与第一源极/漏极电极相距第一距离处,以及与第二源极/漏极电极相距第二距离处,第一距离与第二距离不同。
阅读以下详细说明并参照附图之后,本发明的这些和其他的特点和优势,对于本领域的技术人员而言,无疑将显而易见。
附图说明
图1A至1E表示传统的GaN基HEMT对称闭锁开关器件的剖面图和电路图。
图2至5表示作为本发明不同的较佳实施例,非对称闭锁开关器件的剖面图。
图6A至6G表示本发明制备器件的工艺步骤的一系列剖面图。
图7A至7H表示本发明制备器件的工艺步骤的一系列剖面图。
图8A至8I表示本发明制备器件的工艺步骤的一系列剖面图。
图9A至9G表示本发明制备器件的工艺步骤的一系列剖面图。
图10A至10H表示本发明制备器件的工艺步骤的一系列剖面图。
图11A至11I表示本发明制备器件的工艺步骤的一系列剖面图。
具体实施方式
参见图2,对于双向GaN开关的剖面图,作为本发明的高电子迁移率晶体管(HEMT)半导体功率器件100。双向GaN开关器件100包括一个AlGaN层120,外延生长在氮化镓(GaN)层115上方,从而在交界面处构成一个AlGaN/GaN异质结。AlGaN/GaN异质结结构位于衬底105上的缓冲层110上。第一电极140-1和第二电极140-2位于栅极电极135的两个对边上,以控制流经AlGaN和GaN层交界面之间的异质结的双向电流。栅极电极135与AlGaN层120绝缘。为了将双向GaN开关配置成非对称闭锁开关,第一电极140-1和栅极135之间的距离(即LGS1/D2)不同于第二电极140-2和栅极135之间的距离(即LGS2/D1)。因此,在如图2所示的该双向GaN HEMT单栅极器件中,之所以设计非对称闭锁是因为栅极到各自的源极/漏极区的距离不同,即LGD1≠LGD2。此外,栅极135上的场板135-FP1和135-FP2也是非对称的,以获得非对称闭锁。
图2A表示本发明与图2所示的器件类似的非对称双向GaN开关的另一个示例。唯一的不同在于本实施例的栅极135P作为p-型AlGaN栅极。
参见图3所示的双向非对称闭锁开关的剖面图,作为本发明的GaN高电子迁移率晶体管(HEMT)半导体功率器件200。双向GaN开关器件200包括一个AlGaN层120,外延生长在氮化镓(GaN)层115上方,从而在交界面处构成一个AlGaN/GaN异质结。AlGaN/GaN异质结结构位于衬底105上的缓冲层110上。第一电极140-1和第二电极140-2位于AlGaN层120顶面的两个对边上。非对称闭锁开关还包括双栅极135-1和135-2,分别位于场板140-1-FP和140-2-FP下方。
为了将双向闭锁开关配置成非对称闭锁开关,第一和第二个漏极/源极电极的场板,即所形成的第一场板LSD-FP1具有与第二场板LSD-FP2不同的长度。栅极和电极之间的距离,即LGS1和LGS2也可以具有非对称结构。
参见图4对于双向非对称闭锁开关的剖面图,作为本发明所述的单独栅极金属绝缘物半导体场效应晶体管(MISFET)半导体功率器件300。双向GaN开关器件300包括一个AlGaN层120外延生长在氮化镓(GaN)层115上方,从而在交界面处构成一个AlGaN/GaN异质结。AlGaN/GaN异质结结构位于衬底105上的缓冲层110上。双向非对称闭锁开关300还包括一个盖帽/钝化层125,作为高电阻层,例如GaN/SiN/SiO2层,盖帽/钝化层125为2至200纳米的薄层。盖帽/钝化层125可以用作含有SiN或SiO2的钝化层或栅极电介质层。
第一电极140-1和第二电极140-2位于栅极电极135的两个对边上,以控制流经AlGaN和GaN层交界面之间异质结的双向电流。为了将双向GaN开关配置成非对称闭锁开关,第一电极140-1和栅极135之间的距离(即LGS1/D2)不同于第二电极140-2和栅极135之间的距离(即LGS2/D1)。因此,在如图4所示的该双向GaN HEMT单栅极器件中,之所以设计非对称闭锁是因为栅极到各自的源极/漏极区的距离不同,即LGD1≠LGD2。此外,栅极135上的场板135-FP1和135-FP2也是非对称的,以获得非对称闭锁。
参见图5,本发明的一个可选实施例的剖面图。双向开关用作双向GaN高电子迁移率晶体管(HEMT)半导体功率器件400。双向GaN开关器件400包括一个AlGaN层120外延生长在氮化镓(GaN)层115上方,从而在交界面处构成一个AlGaN/GaN异质结。AlGaN/GaN异质结结构位于衬底105上的缓冲层110上。第一电极140-1和第二电极140-2位于栅极电极的两个对边上,以控制流经AlGaN和GaN层交界面之间的异质结的双向电流。栅极电极135T作为带沟槽的栅极,通过绝缘层125T与AlGaN层120绝缘。为了将双向GaN开关配置成非对称闭锁开关,第一电极140-1和栅极135T(即LGS1/D2)不同于第二电极140-2和栅极135T之间的距离(即LGS2/D1)。因此,在如图5所示的该双向GaN HEMT单栅极器件中,之所以设计非对称闭锁是因为栅极到各自的源极/漏极区的距离不同,即LGD1≠LGD2。此外,栅极135上的场板135-FP1和135-FP2也是非对称的,以获得非对称闭锁。
图6A至6G所示一系列的剖面图,表示制备本发明所述的双向非对称中心MIS栅极闭锁GaN开关的工艺步骤。在图6A中,工艺流程从衬底105开始。衬底105可以是硅(Si)、碳化硅(SiC)、氮化镓(GaN)或蓝宝石衬底。在图6B中,生长外延层110作为缓冲层。可以通过不同的方法生长缓冲层,并且缓冲层可以是含有GaN、ALN、AlGaN等层的组合层。缓冲层110可以作为外延层生长,根据实际应用的电压,缓冲层110的厚度范围为0.25μm至7μm。缓冲层110可以掺杂Fe、C,或者也可以是无意掺杂。在图6C中,生长一个含有GaN外延层115的通道层。通道层的厚度范围为100至400纳米(nm)。在图6D中,生长一个势垒层120。势垒外延层120可以由AlxGa1-xN(例如0.18<x<28)制成,厚度范围为10至30nm,或者由AlN制成,厚度范围为2至10nm。势垒外延层120由带隙大于GaN的材料制成。在图6E中,沉积一个盖帽/钝化层125。盖帽或钝化层可以是一个高阻层,例如一层GaN/SiN/SiO2,并且作为一个薄层,范围为2至200纳米。盖帽/钝化层125可以作为一层绝缘物,起钝化的作用或由SiN或SiO2制成的栅极电介质层的作用。在图6F中,利用标准工艺制备源极/漏极欧姆接触,以制备由Ti、Al、Ni或Au金属制成的金属接头130-1和130-2。在图6G中,利用工艺制备栅极/场板135和源极/漏极场板140-1和140-2。栅极135和源极/漏极场板140-1和140-2的结构,取决于器件电压以及上述非对称闭锁开关的外延设计。
图7A至7H所示一系列剖面图,表示制备本发明所述的带有非对称中心栅极的双向非对称中心P-型栅极闭锁GaN开关的工艺步骤。在图7A中,工艺流程从衬底105开始。衬底105可以是硅(Si)、碳化硅(SiC)、氮化镓(GaN)或蓝宝石衬底。在图7B中,生长一个外延层110,作为缓冲层。可以通过不同的方法生长缓冲层,并且缓冲层可以是含有GaN、ALN、AlGaN等层的组合层。缓冲层110可以作为外延层生长,根据实际应用的电压,缓冲层110的厚度范围为0.25μm至7μm。缓冲层110可以掺杂Fe、C,或者也可以是无意掺杂。在图7C中,生长一个含有GaN外延层115的通道层。通道层的厚度范围为100至400纳米(nm)。在图7D中,生长一个势垒层120。势垒外延层120可以由AlxGa1-xN(例如0.18<x<28)制成,厚度范围为10至30nm,或者由AlN制成,厚度范围为2至10nm。势垒外延层120由带隙大于GaN的材料制成。在图7E中,沉积一个P-型外延层150。P-型外延层可以是GaN或AlGaN等类似材料,并掺杂Mg等P-型掺杂物,作为一个薄层,范围为2至200纳米。盖帽/钝化层125可以作为一层绝缘物,起钝化的作用或由SiN或SiO2制成的栅极电介质层的作用。在图7F中,通过刻蚀工艺,形成P-外延层150的图案,用于限定栅极区域。在图7G中,利用标准工艺制备源极/漏极欧姆接触,以制备由Ti、Al、Ni或Au金属制成的金属接头130-1和130-2。在图7H中,沉积一个盖帽/钝化层125。盖帽或钝化层可以是一个高阻层,例如一层GaN/SiN/SiO2,作为一个薄层,范围为2至200纳米。盖帽/钝化层125可以作为一层绝缘物,起钝化作用,或由SiN或SiO2构成的栅极电介质层。然后,利用工艺制备栅极/场板135和源极/漏极场板140-1和140-2。栅极135和源极/漏极场板140-1和140-2的结构,取决于器件电压以及上述非对称闭锁开关的外延设计。
图8A至8I所示的一系列剖面图,表示制备本发明所述的双向非对称中心沟槽MIS-栅极闭锁GaN开关的工艺步骤。在图8A中,工艺流程从衬底105开始。衬底105可以是硅(Si)、碳化硅(SiC)、氮化镓(GaN)或蓝宝石衬底。在图8B中,生长一个外延层110,作为缓冲层。可以通过不同的方法生长缓冲层,并且缓冲层可以是含有GaN、ALN、AlGaN等层的组合层。缓冲层110可以作为外延层生长,根据实际应用的电压,缓冲层110的厚度范围为0.25μm至7μm。缓冲层110可以掺杂Fe、C,或者也可以是无意掺杂。在图8C中,生长一个含有GaN外延层115的通道层。通道层的厚度范围为100至400纳米(nm)。在图8D中,生长一个势垒层120。势垒外延层120可以由AlxGa1-xN(例如0.18<x<28)制成,厚度范围为10至30nm,或者由AlN制成,厚度范围为2至10nm。势垒外延层120由带隙大于GaN的材料制成。在图8E中,沉积一个盖帽/钝化层125。盖帽或钝化层可以是一个高阻层,例如一层GaN/SiN/SiO2,并且作为一个薄层,范围为2至200纳米。盖帽/钝化层125可以作为一层绝缘物,起钝化的作用或由SiN或SiO2制成的栅极电介质层的作用。在图8F中,利用标准工艺制备源极/漏极欧姆接触,以制备由Ti、Al、Ni或Au金属制成的金属接头130-1和130-2。在图8G中,利用刻蚀工艺,通过钝化层125和势垒层120刻蚀,在势垒层120中打开栅极沟槽132,以减少二维电子气(2DEG)中的电子。在图8H中,沉积栅极电介质层128。栅极电介质层可以由Si3N4、SiO2或其他高电阻率的材料构成。在图8I中,利用工艺,制备栅极/场板135’和源极/漏极场板140-1和140-2。栅极135’和源极/漏极场板140-1和140-2的结构,取决于器件电压以及上述非对称闭锁开关的外延设计。
图9A至9G所示的一系列剖面图,表示制备本发明所述的双向非对称中心沟槽MIS-栅极闭锁GaN开关的工艺步骤。在图9A中,工艺流程从衬底105开始。衬底105可以是硅(Si)、碳化硅(SiC)、氮化镓(GaN)或蓝宝石衬底。在图9B中,生长一个外延层110,作为缓冲层。可以通过不同的方法生长缓冲层,并且缓冲层可以是含有GaN、ALN、AlGaN等层的组合层。缓冲层110可以作为外延层生长,根据实际应用的电压,缓冲层110的厚度范围为0.25μm至7μm。缓冲层110可以掺杂Fe、C,或者也可以是无意掺杂。在图9C中,生长一个含有GaN外延层115的通道层。通道层的厚度范围为100至400纳米(nm)。在图9D中,生长一个势垒层120。势垒外延层120可以由AlxGa1-xN(例如0.18<x<28)制成,厚度范围为10至30nm,或者由AlN制成,厚度范围为2至10nm。势垒外延层120由带隙大于GaN的材料制成。在图9E中,沉积一个盖帽/钝化层125。盖帽或钝化层可以是一个高阻层,例如一层GaN/SiN/SiO2,并且作为一个薄层,范围为2至200纳米。盖帽/钝化层125可以作为一层绝缘物,起钝化的作用或由SiN或SiO2制成的栅极电介质层的作用。在图9F中,利用标准工艺制备源极/漏极欧姆接触,以制备由Ti、Al、Ni或Au金属制成的金属接头130-1和130-2。在图9G中,利用工艺,制备由双栅极/场板135-1、135-2和源极/漏极场板140-1和140-2。双栅极135-1和135-2的结构,以及源极/漏极场板140-1和140-2的长度,取决于器件电压和上述非对称闭锁开关的外延设计。
图10A至10H所示的一系列剖面图,表示制备带有本发明所述的非对称中心栅极的双向非对称双P-型栅极闭锁GaN开关的工艺步骤。在图10A中,工艺流程从衬底105开始。衬底105可以是硅(Si)、碳化硅(SiC)、氮化镓(GaN)或蓝宝石衬底。在图10B中,生长一个外延层110,作为缓冲层。可以通过不同的方法生长缓冲层,并且缓冲层可以是含有GaN、ALN、AlGaN等层的组合层。缓冲层110可以作为外延层生长,根据实际应用的电压,缓冲层110的厚度范围为0.25μm至7μm。缓冲层110可以掺杂Fe、C,或者也可以是无意掺杂。在图10C中,生长一个含有GaN外延层115的通道层。通道层的厚度范围为100至400纳米(nm)。在图10D中,生长一个势垒层120。势垒外延层120可以由AlxGa1-xN(例如0.18<x<28)制成,厚度范围为10至30nm,或者由AlN制成,厚度范围为2至10nm。势垒外延层120由带隙大于GaN的材料制成。在图10E中,沉积一个P-型外延层150。P-型外延层可以是一个掺杂AlGaN的层,并且作为一个薄层,范围为2至200纳米。在图10F中,通过刻蚀工艺,形成P-外延层150的图案,用于限定双栅极的区域150-1和150-2。在图10G中,利用标准工艺制备源极/漏极欧姆接触,以制备由Ti、Al、Ni或Au金属制成的金属接头130-1和130-2。在图10H中,沉积一个盖帽/钝化层125。盖帽或钝化层可以是一个高阻层,例如一层GaN/SiN/SiO2,作为一个薄层,范围为2至200纳米。盖帽/钝化层125可以作为一层绝缘物,起钝化作用,或由SiN或SiO2构成的栅极电介质层。然后,利用工艺制备栅极/场板135和源极/漏极场板140-1和140-2。栅极135-1、135-2和源极/漏极场板140-1和140-2的结构,取决于器件电压以及上述非对称闭锁开关的外延设计。
图11A至11I所示的一系列剖面图,表示制备本发明所述的双向非对称双沟槽MIS-栅极闭锁GaN开关的工艺步骤。在图11A中,工艺流程从衬底105开始。衬底105可以是硅(Si)、碳化硅(SiC)、氮化镓(GaN)或蓝宝石衬底。在图11B中,生长一个外延层110,作为缓冲层。可以通过不同的方法生长缓冲层,并且缓冲层可以是含有GaN、ALN、AlGaN等层的组合层。缓冲层110可以作为外延层生长,根据实际应用的电压,缓冲层110的厚度范围为0.25μm至7μm。缓冲层110可以掺杂Fe、C,或者也可以是无意掺杂。在图11C中,生长一个含有GaN外延层115的通道层。通道层的厚度范围为100至400纳米(nm)。在图11D中,生长一个势垒层120。势垒外延层120可以由AlxGa1-xN(例如0.18<x<28)制成,厚度范围为10至30nm,或者由AlN制成,厚度范围为2至10nm。势垒外延层120由带隙大于GaN的材料制成。在图11E中,沉积一个盖帽/钝化层125。盖帽或钝化层可以是一个高阻层,例如一层GaN/SiN/SiO2,并且作为一个薄层,范围为2至200纳米。盖帽/钝化层125可以作为一层绝缘物,起钝化的作用或由SiN或SiO2制成的栅极电介质层的作用。在图11F中,利用标准工艺制备源极/漏极欧姆接触,以制备由Ti、Al、Ni或Au金属制成的金属接头130-1和130-2。在图11G中,利用刻蚀工艺,通过钝化层125和势垒层120刻蚀,在势垒层120中打开栅极沟槽132,以减少二维电子气(2DEG)中的电子。在图11H中,在双栅极沟槽132-1和132-2中,沉积栅极电介质层128。栅极电介质层可以由Si3N4、SiO2或其他高电阻率的材料构成。在图11I中,利用工艺,制备双栅极/场板135’-1、135’-2和源极/漏极场板140-1和140-2。双栅极/场板135’-1、135’-2和源极/漏极场板140-1和140-2的结构,取决于器件电压以及上述非对称闭锁开关的外延设计。
尽管本发明已经详细说明了现有的较佳实施例,但应理解这些说明不应作为本发明的局限。对于这些实施例,也有可能使用各种可选、修正和等效方案。因此,本发明的范围不应局限于以上说明,而应由所附的权利要求书及其全部等效内容决定。
Claims (8)
1.一种高电子迁移率晶体管(HEMT)氮化镓(GaN)双向闭锁器件,包括:
一个异质结结构,包括两个不同带隙的第一半导体层与第二半导体层相交接,从而形成一个交界面层,作为二维电子气(2DEG)层;以及
一个第一源极/第二漏极电极和一个第二源极/第一漏极电极,位于所述的异质结结构顶面的两个对边上;
第一源极/第二漏极电极还包括一个第一场板,向第二源极/第一漏极电极横向延伸,第一栅极位于第一场板下方;以及
第二源极/第一漏极电极还包括一个第二场板,向第一源极/第二漏极电极横向延伸,第二栅极位于第二场板下方,其中将第一场板和第二场板成非对称配置;
所述第一源极/第二漏极电极和所述第一栅极之间的距离不同于所述第二源极/第一漏极电极和所述第二栅极之间的距离。
2.如权利要求1所述的高电子迁移率晶体管氮化镓双向闭锁器件,其中:
第一场板的长度用LSD-FP1表示,第二场板的长度用LSD-FP2表示,其中LSD-FP1不同于LSD-FP2。
3.如权利要求1所述的高电子迁移率晶体管氮化镓双向闭锁器件,还包括:
一个蓝宝石衬底,用于支撑上面的异质结结构。
4.如权利要求1所述的高电子迁移率晶体管氮化镓双向闭锁器件,其中:
异质结结构含有氮化镓(GaN),作为第一半导体层,与作为第二半导体层的AlGaN层相交接。
5.如权利要求1所述的高电子迁移率晶体管氮化镓双向闭锁器件,其中:
第一半导体层为N-型氮化镓层,第二半导体层为N-型AlGaN层,位于氮化镓层上方。
6.如权利要求1所述的高电子迁移率晶体管氮化镓双向闭锁器件,还包括:
一个GaN缓冲层,位于底部衬底上方,用于支撑上面的异质结结构。
7.如权利要求1所述的高电子迁移率晶体管氮化镓双向闭锁器件,其中:
第一栅极包括一个第一P-型AlGaN栅极,和第二栅极包括一个第二P-型AlGaN栅极。
8.如权利要求1所述的高电子迁移率晶体管氮化镓双向闭锁器件,其中:
第一源极/第二漏极电极和第二源极/第一漏极电极由一种金属制成,金属可以从Ti、Al、Ni和Au中选取。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/244,819 US20180076310A1 (en) | 2016-08-23 | 2016-08-23 | Asymmetrical blocking bidirectional gallium nitride switch |
US15/244,819 | 2016-08-23 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN107768439A CN107768439A (zh) | 2018-03-06 |
CN107768439B true CN107768439B (zh) | 2021-06-15 |
Family
ID=61265173
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201710672810.5A Active CN107768439B (zh) | 2016-08-23 | 2017-08-08 | 非对称闭锁双向氮化镓开关 |
Country Status (3)
Country | Link |
---|---|
US (2) | US20180076310A1 (zh) |
CN (1) | CN107768439B (zh) |
TW (1) | TWI644429B (zh) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10680090B2 (en) * | 2017-07-20 | 2020-06-09 | Delta Electronics, Inc. | Enclosed gate runner for eliminating miller turn-on |
US10483356B2 (en) * | 2018-02-27 | 2019-11-19 | Siliconix Incorporated | Power semiconductor device with optimized field-plate design |
JP7021038B2 (ja) * | 2018-09-18 | 2022-02-16 | 株式会社東芝 | 半導体装置 |
US11522060B2 (en) * | 2018-09-26 | 2022-12-06 | Intel Corporation | Epitaxial layers on contact electrodes for thin- film transistors |
US11522079B2 (en) * | 2019-10-16 | 2022-12-06 | Tower Semiconductor Ltd. | Electrostatically controlled gallium nitride based sensor and method of operating same |
CN111863961B (zh) * | 2020-07-28 | 2021-11-09 | 西安电子科技大学 | 异质结场效应晶体管 |
US11901445B2 (en) * | 2020-11-13 | 2024-02-13 | Globalfoundries Singapore Pte. Ltd. | Transistor and methods of fabricating a transistor |
CN112466928B (zh) * | 2020-12-15 | 2021-11-30 | 南京工业职业技术大学 | 一种同时优化击穿特性和反向特性的GaN HEMT器件及其制作工艺 |
US11923424B2 (en) * | 2020-12-31 | 2024-03-05 | Nxp B.V. | Semiconductor device with conductive elements formed over dielectric layers and method of fabrication therefor |
CN113454790B (zh) * | 2021-02-25 | 2023-03-31 | 英诺赛科(苏州)科技有限公司 | 半导体器件及其制造方法 |
EP4115449A4 (en) | 2021-05-25 | 2023-08-02 | Innoscience (Suzhou) Semiconductor Co., Ltd. | BIDIRECTIONAL NITRIDE-BASED SEMICONDUCTOR SWITCHING DEVICE AND METHOD OF MANUFACTURE THEREOF |
WO2023272674A1 (en) * | 2021-07-01 | 2023-01-05 | Innoscience (Suzhou) Technology Co., Ltd. | Nitride-based multi-channel switching semiconductor device and method for manufacturing the same |
CN113594247B (zh) * | 2021-07-30 | 2024-01-26 | 电子科技大学 | 一种逆阻型氮化镓高电子迁移率晶体管 |
WO2023015494A1 (en) * | 2021-08-11 | 2023-02-16 | Innoscience (Suzhou) Technology Co., Ltd. | Semiconductor device and method for manufacturing the same |
CN115911108A (zh) * | 2021-09-30 | 2023-04-04 | 华为数字能源技术有限公司 | 一种半导体器件及其制造方法 |
CN116913954A (zh) * | 2021-09-30 | 2023-10-20 | 湖南三安半导体有限责任公司 | 氮化镓双向开关器件 |
US20240047568A1 (en) * | 2021-12-31 | 2024-02-08 | Innoscience (suzhou) Semiconductor Co., Ltd. | Nitride-based bidirectional switching device and method for manufacturing the same |
CN115763558A (zh) * | 2022-11-11 | 2023-03-07 | 英诺赛科(苏州)半导体有限公司 | 一种半导体装置及其形成方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102822982A (zh) * | 2010-03-26 | 2012-12-12 | 松下电器产业株式会社 | 双向开关元件及使用该双向开关元件的双向开关电路 |
WO2014129245A1 (ja) * | 2013-02-21 | 2014-08-28 | シャープ株式会社 | 窒化物半導体装置 |
CN104934476A (zh) * | 2014-03-19 | 2015-09-23 | 株式会社东芝 | 半导体装置及其制造方法 |
CN105428409A (zh) * | 2014-09-16 | 2016-03-23 | 株式会社东芝 | 半导体装置及其制造方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7126426B2 (en) * | 2003-09-09 | 2006-10-24 | Cree, Inc. | Cascode amplifier structures including wide bandgap field effect transistor with field plates |
JP2006310769A (ja) * | 2005-02-02 | 2006-11-09 | Internatl Rectifier Corp | Iii族窒化物一体化ショットキおよび電力素子 |
US8946778B2 (en) * | 2007-01-10 | 2015-02-03 | International Rectifier Corporation | Active area shaping of III-nitride devices utilizing steps of source-side and drain-side field plates |
US8168486B2 (en) * | 2009-06-24 | 2012-05-01 | Intersil Americas Inc. | Methods for manufacturing enhancement-mode HEMTs with self-aligned field plate |
KR20120120828A (ko) * | 2011-04-25 | 2012-11-02 | 삼성전기주식회사 | 질화물 반도체 소자 및 그 제조방법 |
WO2013036593A1 (en) * | 2011-09-06 | 2013-03-14 | Sensor Electronic Technology, Inc. | Semiconductor device with low-conducting field-controlling element |
US8633094B2 (en) * | 2011-12-01 | 2014-01-21 | Power Integrations, Inc. | GaN high voltage HFET with passivation plus gate dielectric multilayer structure |
US20140159116A1 (en) * | 2012-12-07 | 2014-06-12 | International Rectifier Corporation | III-Nitride Device Having an Enhanced Field Plate |
JP6534791B2 (ja) * | 2013-12-16 | 2019-06-26 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US20160079233A1 (en) * | 2014-09-15 | 2016-03-17 | Infineon Technologies Austria Ag | Iii-v semiconductor material based ac switch |
-
2016
- 2016-08-23 US US15/244,819 patent/US20180076310A1/en not_active Abandoned
-
2017
- 2017-08-08 CN CN201710672810.5A patent/CN107768439B/zh active Active
- 2017-08-17 TW TW106127982A patent/TWI644429B/zh active
-
2019
- 2019-05-31 US US16/428,746 patent/US10777673B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102822982A (zh) * | 2010-03-26 | 2012-12-12 | 松下电器产业株式会社 | 双向开关元件及使用该双向开关元件的双向开关电路 |
WO2014129245A1 (ja) * | 2013-02-21 | 2014-08-28 | シャープ株式会社 | 窒化物半導体装置 |
CN104934476A (zh) * | 2014-03-19 | 2015-09-23 | 株式会社东芝 | 半导体装置及其制造方法 |
CN105428409A (zh) * | 2014-09-16 | 2016-03-23 | 株式会社东芝 | 半导体装置及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20190355844A1 (en) | 2019-11-21 |
US10777673B2 (en) | 2020-09-15 |
US20180076310A1 (en) | 2018-03-15 |
TW201826534A (zh) | 2018-07-16 |
CN107768439A (zh) | 2018-03-06 |
TWI644429B (zh) | 2018-12-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN107768439B (zh) | 非对称闭锁双向氮化镓开关 | |
KR100841472B1 (ko) | Ⅲ-질화물 양방향 스위치 | |
JP6362248B2 (ja) | Mishfetおよびショットキーデバイスの統合 | |
JP6522521B2 (ja) | 半導体デバイスの電極及びその製造方法 | |
CN105283958B (zh) | GaN HEMT的共源共栅结构 | |
TWI609488B (zh) | 具有場板的半導體元件 | |
US11075196B2 (en) | Integrated resistor for semiconductor device | |
EP3326208A1 (en) | Field-plate structures for semiconductor devices | |
US20110309372A1 (en) | Enhancement-mode hfet circuit arrangement having high power and a high threshold voltage | |
US9502549B2 (en) | Nitride semiconductor device | |
CN102694019B (zh) | 氮化物半导体器件及其制造方法 | |
US10134850B2 (en) | Semiconductor device | |
EP3008759A1 (en) | Cascode structures with gan cap layers | |
US9209255B2 (en) | Semiconductor device including an electrode structure formed on nitride semiconductor layers | |
CN103972284A (zh) | 半导体器件 | |
KR100770132B1 (ko) | 질화물계 반도체 소자 | |
US20220384424A1 (en) | Nitride-based semiconductor bidirectional switching device and method for manufacturing the same | |
CN216250739U (zh) | 一种具有高导通能力的氮化镓晶体管 | |
CN104037211B (zh) | 半导体器件和电子装置 | |
CN113224155A (zh) | 一种具有高导通能力的氮化镓晶体管及其制备方法 | |
JP2006114795A (ja) | 半導体装置 | |
CN116344586A (zh) | 折叠沟道氮化镓基场效应晶体管及其制备方法 | |
JP5666992B2 (ja) | 電界効果型トランジスタおよびその製造方法 | |
CN106558601B (zh) | 半导体装置及其制造方法 | |
JP2023503944A (ja) | Iii族窒化物半導体集積回路構造、その製造方法および使用 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |