CN107731753B - 半导体结构的形成方法 - Google Patents

半导体结构的形成方法 Download PDF

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CN107731753B
CN107731753B CN201610664338.6A CN201610664338A CN107731753B CN 107731753 B CN107731753 B CN 107731753B CN 201610664338 A CN201610664338 A CN 201610664338A CN 107731753 B CN107731753 B CN 107731753B
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CN107731753A (zh
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谢欣云
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to US15/666,865 priority patent/US20180047623A1/en
Priority to EP17185488.8A priority patent/EP3288065A1/en
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Abstract

本发明提供一种半导体结构的形成方法，包括：形成基底，所述基底包括：衬底，位于衬底上的栅极结构，位于所述栅极结构两侧衬底中的源漏掺杂区，位于所述衬底和栅极结构顶部上的介质层；形成贯穿所述介质层的接触孔，所述接触孔底部延伸至所述源漏掺杂区中；形成所述接触孔之后，通过掺杂工艺在所述源漏掺杂区中掺入掺杂离子，在所述接触孔底部和侧壁暴露出的源漏掺杂区中形成掺杂层；在形成所述掺杂层之后，在所述接触孔中形成插塞。所述形成方法能够使掺杂离子在所述源漏掺杂区中分布均匀，从而能够使插塞与源漏掺杂区之间的电阻率分布较均匀，进而能够改善所形成半导体结构性能。

Description

半导体结构的形成方法
技术领域
本发明涉及半导体制造技术领域，尤其涉及一种半导体结构的形成方法。
背景技术
随着半导体技术的不断进步，半导体器件的特征尺寸逐渐变小。关键尺寸的缩小意味着在芯片上可布置更多数量的晶体管，同时给半导体工艺提出了更高的要求。
源漏掺杂区和栅极结构是晶体管的重要组成部分。晶体管通过在源漏掺杂区上形成插塞实现与外部电路的电连接。源漏掺杂区掺杂离子的浓度对插塞与源漏掺杂区之间的接触电阻具有很大影响，源漏掺杂区掺杂离子浓度越高，所述接触电阻越小。因此，在形成所述硅化物之前，往往通过对源漏掺杂区进行掺杂来降低所述接触电阻。
然而，现有技术形成的半导体结构的源漏掺杂区与插塞之间的接触电阻率分布不均匀，半导体结构性能不稳定。
发明内容
本发明解决的问题是提供一种半导体结构的形成方法，能够改善所形成半导体结构性能。
为解决上述问题，本发明提供一种半导体结构的形成方法，包括：形成基底，所述基底包括：衬底，位于衬底上的栅极结构，位于所述栅极结构两侧衬底中的源漏掺杂区，位于所述衬底和栅极结构顶部上的介质层；形成贯穿所述介质层的接触孔，所述接触孔底部延伸至所述源漏掺杂区中；形成所述接触孔之后，通过掺杂工艺在所述源漏掺杂区中掺入掺杂离子，在所述接触孔底部和侧壁暴露出的源漏掺杂区中形成掺杂层；在形成所述掺杂层之后，在所述接触孔中形成插塞。
可选的，所述掺杂工艺具有各向同性；所述掺杂工艺为等离子体掺杂工艺。
可选的，所述源漏掺杂区用于形成NMOS晶体管，所述掺杂离子为磷离子、砷离子或锑离子。
可选的，所述源漏掺杂区用于形成PMOS晶体管，所述掺杂离子为硼离子或铟离子。
可选的，所述掺杂层中掺杂的离子浓度大于5E14atoms/cm2；所述掺杂工艺的工艺参数包括：掺杂剂量为1E15atoms/cm2～5E15atoms/cm2，掺杂能量为：10eV～20KeV，气压为1mtorr～1000mtorr温度为25℃～800℃。
可选的，在所述接触孔中形成插塞之前，还包括：对所述掺杂层进行防扩散处理。
可选的，通过离子注入对所述掺杂层进行防扩散处理，在所述掺杂层中注入重离子。
可选的，所述重离子的原子量大于所述掺杂离子的原子量。
可选的，通过等离子体掺杂进行所述防扩散处理，在所述掺杂层中掺入重离子，所述重离子的原子量大于所述掺杂离子的原子量。
可选的，所述源漏掺杂区用于形成NMOS晶体管，所述掺杂离子为磷离子；所述重离子为砷离子或锑离子。
可选的，所述源漏掺杂区用于形成PMOS晶体管，所述掺杂离子为硼离子；对所述掺杂层进行离子注入的注入离子为铟离子。
可选的，所述离子注入的工艺参数包括：注入能量为200eV～20KeV；注入剂量小于1E14atoms/cm2；注入角度为0度～20度。
可选的，形成所述插塞的之前，形成所述掺杂层之后，还包括：在所述接触孔底部和侧壁形成金属层，与所述掺杂层接触的金属层与所述掺杂层反应形成金属化物。
可选的，所述基底包括：第一晶体管区和第二晶体管区；所述栅极结构包括：位于第一晶体管区衬底上的第一栅极结构；位于第二晶体管区衬底上的第二栅极结构；所述源漏掺杂区包括：位于第一栅极结构两侧衬底中的第一源漏掺杂区；位于第二栅极结构两侧衬底中的第二源漏掺杂区；所述掺杂层包括：位于所述第一源漏掺杂区表面的第一掺杂层和位于所述第二源漏掺杂区表面的第二掺杂层。
可选的，通过掺杂工艺对所述源漏掺杂区进行掺杂的步骤包括：在所述第一晶体管区介质层上和接触孔中形成第一光刻胶；以所述第一光刻胶为掩膜，通过第二掺杂工艺对所述第二源漏掺杂区进行掺杂，在所述第二晶体管区接触孔底部和侧壁暴露出的第二源漏掺杂区中形成第二掺杂层；去除所述第一光刻胶；在所述第二晶体管区介质层上和接触孔中形成第二光刻胶；以所述第二光刻胶为掩膜，通过第一掺杂工艺对所述第一源漏掺杂区进行掺杂，在所述第一晶体管区接触孔底部和侧壁暴露出的第一源漏掺杂区中形成第一掺杂层；去除所述第二光刻胶。
可选的，在所述接触孔中形成插塞之前，还包括：对所述掺杂层进行防扩散处理；所述扩散处理的步骤包括：通过第二掺杂工艺对所述第二源漏掺杂区进行掺杂之后，以所述第一光刻胶为掩膜对所述第二掺杂层进行第二防扩散处理；通过第一掺杂工艺对所述第一源漏掺杂区进行掺杂之后，以所述第二光刻胶为掩膜对所述第一掺杂层进行第一防扩散处理。
与现有技术相比，本发明的技术方案具有以下优点：
本发明的半导体结构的形成方法中，通过掺杂工艺对所述源漏掺杂区进行掺杂，在所述接触孔底部和侧壁暴露出的源漏掺杂区中形成掺杂层，所述掺杂层能够降低源漏掺杂区与插塞之间的电阻。在对所述源漏掺杂区进行掺杂之后，所述掺杂离子能够分布于接触孔底部和侧壁的所述源漏掺杂区中，且能够使掺杂离子在所述源漏掺杂区中分布均匀。因此，所述形成方法能够使插塞与源漏掺杂区之间的电阻率分布较均匀，从而能够改善所形成半导体结构性能。
进一步，形成所述插塞之前，对所述掺杂层进行防扩散处理。所述防扩散处理能够减小所述掺杂层中掺杂离子向掺杂层表面的扩散，从而能够增加所述掺杂中掺杂离子浓度，进而减小所述插塞与源漏掺杂区之间的电阻。因此，所述形成方法能够进一步改善半导体结构性能。
附图说明
图1至图3是一种半导体结构的形成方法各步骤的结构示意图；
图4至图11是本发明半导体结构的形成方法一实施例各步骤的结构示意图。
具体实施方式
半导体结构的形成方法存在诸多问题，例如：所形成的半导体结构性能较差。
现结合一种半导体结构的形成方法，分析所述形成方法形成的半导体结构性能较差的原因：
图1至图3是一种半导体结构的形成方法各步骤的结构示意图。
请参考图1，提供基底，所述基底包括：衬底100，位于所述衬底100上的栅极结构110；位于所述栅极结构110两侧衬底100中的源漏掺杂区120，位于所述衬底100和所述源漏掺杂区120上的底层介质层102。
继续参考图1，在所述基底上形成介质层101。
请参考图2，形成贯穿所述介质层101的接触孔111，所述接触孔111底部延伸至所述源漏掺杂区120中。
继续参考图2，形成所述接触孔111之后，对所述源漏掺杂区120进行离子注入，在所述接触孔底部暴露出的源漏掺杂区120中形成掺杂层121。
请参考图3，在所述接触孔111(如图2所示)中形成插塞130。
其中，所述离子注入具有方向性。在对所述源漏掺杂区120进行离子注入的过程中，在所述接触孔111下方的源漏掺杂区120中注入的离子浓度较高，因此，所述插塞130与插塞130下方源漏掺杂区120之间的接触电阻率较小。然而，所述接触孔111侧壁的源漏掺杂区120中注入的离子浓度较小，因此，所述接触孔111侧壁暴露出的源漏掺杂区120与所述插塞130之前的电阻率较大。也就是说，所述形成方法形成的源漏掺杂区120与插塞130之间的接触电阻率分布不均匀，因此，所形成的半导体结构性能较差。
为解决所述技术问题，本发明提供了一种半导体结构的形成方法，包括：形成基底，所述基底包括：衬底，位于衬底上的栅极结构，位于所述栅极结构两侧衬底中的源漏掺杂区，位于所述衬底和栅极结构顶部上的介质层；形成贯穿所述介质层的接触孔，所述接触孔底部延伸至所述源漏掺杂区中；形成所述接触孔之后，通过掺杂工艺在所述源漏掺杂区中掺入掺杂离子，在所述接触孔底部和侧壁暴露出的源漏掺杂区中形成掺杂层；在形成所述掺杂层之后，在所述接触孔中形成插塞。
其中，通过掺杂工艺对所述源漏掺杂区进行掺杂，在所述接触孔底部和侧壁暴露出的源漏掺杂区中形成掺杂层，所述掺杂层能够降低源漏掺杂区与插塞之间的电阻。在对所述源漏掺杂区进行掺杂之后，所述掺杂离子能够分布于接触孔底部和侧壁暴露出的所述源漏掺杂区中，且能够使掺杂离子在所述源漏掺杂区中分布均匀。因此，所述形成方法能够使插塞与源漏掺杂区之间的电阻率分别较均匀，从而能够改善所形成半导体结构性能。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图4至图11是本发明半导体结构的形成方法一实施例各步骤的结构示意图。
请参考图4和图5，提供基底，所述基底包括：衬底，位于衬底上的栅极结构，位于所述栅极结构两侧衬底中的源漏掺杂区，位于所述衬底和栅极结构顶部上的介质层。
本实施例中，所述基底包括：第一晶体管区I和第二晶体管区II。
所述第一晶体管区I用于形成NMOS晶体管；所述第二晶体管区II用于形成PMOS。在其他实施例中，所述第一晶体管区还可以用于形成PMOS晶体管；所述第二晶体管区用于形成NMOS。
本实施例中，所述介质层包括：位于所述衬底上的底层介质层203；位于所述底层介质层203和所述栅极结构顶部上的顶层介质层230。
形成所述基底的步骤如图4和图5所示。
请参考图4，提供衬底；在所述衬底上形成栅极结构；在栅极结构两侧的衬底内形成源漏掺杂区；在衬底和源漏掺杂区上形成底层介质层203，所述底层介质层203暴露出所述栅极结构顶部。
本实施例中，形成所述衬底的步骤包括：提供初始衬底；对所述初始衬底进行图形化，形成所述底层衬底200和位于所述底层衬底200上的鳍部201。
本实施例中，所述底层衬底200为硅衬底。在其他实施例中，所述底层衬底还可以为锗衬底、硅锗衬底、绝缘体上硅衬底或绝缘体上锗衬底等半导体衬底。
本实施例中，所述鳍部201的材料为硅。在其他实施例中，所述鳍部的材料还可以为锗或硅锗。
本实施例中，所述基底还包括：位于所述鳍部201之间底层衬底200上的隔离结构201，所述隔离结构201表面低于所述鳍部201顶部表面。
本实施例中，所述栅极结构包括：位于第一晶体管区I鳍部201上的第一栅极结构221；位于第二晶体管区II鳍部201上的第二栅极结构222。
本实施例中，所述第一栅极结构221包括：位于第一晶体管区I鳍部201表面的第一栅介质层；位于所述第一栅介质层上的第一功函数层；位于所述第一功函数层上的第一覆盖层；位于所述第一覆盖层表面的第一栅极。
所述第二栅极结构222包括：位于所述第二晶体管区II鳍部201上的第二栅介质层；位于所述第二栅介质层上的第一功函数层；位于所述第一功函数层上的第二功函数层；位于所述第二功函数层上的第二覆盖层；位于所述第二覆盖层表面的第二栅极。
本实施例中，所述第一栅极和第二栅极为金属栅极。具体的，所述第一栅极和第二栅极的材料为钨。
需要说明的是，本实施例中，所述第一栅极结构221和第二栅极结构222是通过后栅工艺形成的。
本实施例中，所述基底还包括：位于所述底层介质层203上的阻挡层231。
具体的，形成所述第一栅极结构221和第二栅极结构222的步骤包括：在所述第一晶体管区I鳍部201上形成第一伪栅结构；在所述第二晶体管区II鳍部201上形成第二伪栅结构；在所述鳍部201和隔离结构202上依次形成底层介质层203和阻挡层231；去除第一伪栅结构，形成第一开口；去除所述第二伪栅结构，形成第二开口；在所述第一开口中形成第一栅极结构221；在所述第二开口中形成第二栅极结构222。
所述底层介质层203用于实现第一栅极结构221、第二栅极结构222与外部电路的隔离；所述阻挡层231用于保护所述底层介质层203。
需要说明的是，本实施例是以后栅工艺形成所述基底为例进行说明的。在其他实施例中，所述第一栅极和第二栅极还可以为多晶硅栅极。可以通过前栅工艺形成所述基底，所述基底还可以不包括所述底层介质层和阻挡层。
本实施例中，所述源漏掺杂区包括：位于第一栅极结构221两侧鳍部201中的第一源漏掺杂区211；位于所述第二栅极结构221两侧鳍部201中的第二源漏掺杂区212。
本实施例中，形成所述第一伪栅结构和第二伪栅结构之后，且在形成底层介质层203之前，形成所述基底的步骤还包括：在所述第一伪栅结构两侧的鳍部201中形成第一源漏掺杂区211；在所述第二伪栅结构两侧的鳍部201中形成第二源漏掺杂区212。
本实施例中，通过外延生长工艺形成所述第一源漏掺杂区211和第二源漏掺杂区212。并在所述外延生长的工艺中对所述第一源漏掺杂区211和第二源漏掺杂区212进行掺杂。
本实施例中，所述第一晶体管区I用于形成NMOS晶体管，所述第一源漏掺杂区211的材料为碳硅，所述第一源漏掺杂区211中的掺杂的离子为磷离子。
本实施例中，所述第二晶体管区II用于形成PMOS晶体管，所述第二源漏掺杂区212的材料为硅锗，所述第二源漏掺杂区212中的掺杂的离子为硼离子。所述基底还包括：位于所述栅极结构和所述底层介质层203之间的侧墙。
请参考图5，形成所述第一栅极结构221和第二栅极结构222之后，形成所述基底的步骤还包括：在所述底层介质层和所述栅极结构上形成顶层介质层230。
所述顶层介质层230用于实现所述基底与外部电路之间的隔离。
所述顶层介质层230的材料为氧化硅。在其他实施例中，所述顶层介质层的材料还可以为氮氧化硅。
本实施例中，通过化学气相沉积工艺、物理气相沉积工艺或原子层沉积工艺形成所述顶层介质层230。
请参考图6，形成贯穿所述介质层的接触孔240，所述接触孔240底部延伸至所述源漏掺杂区中。
所述接触孔240后续用于容纳插塞，从而实现源漏掺杂区与外部电路的电连接。
形成所述接触孔240的步骤包括：对所述介质层进行刻蚀，形成所述接触孔240。
本实施例中，对所述介质层进行刻蚀的工艺包括干法刻蚀。干法刻蚀在横向的刻蚀速率较小，形成的接触孔240侧壁的垂直性好。
本实施例中，形成所述接触孔240的步骤还包括：对所述阻挡层231进行刻蚀。
后续形成所述接触孔240之后，通过掺杂工艺对所述源漏掺杂区进行掺杂，在所述源漏掺杂区中掺入的离子为掺杂离子，形成掺杂层，在所述接触孔240底部和侧壁暴露出的源漏掺杂区中形成掺杂层。
本实施例中，所述掺杂层包括：位于所述第一源漏掺杂区211中的第一掺杂层；位于所述第二源漏掺杂区212中的第二掺杂层。所述掺杂离子包括位于第一掺杂层中的第一掺杂离子和位于第二掺杂层中的第二掺杂离子。
本实施例中，通过掺杂工艺对所述源漏掺杂区进行掺杂的步骤包括：通过第一掺杂工艺对所述第一源漏掺杂区211进行掺杂，在所述第一晶体管区I接触孔240底部和侧壁的第一源漏掺杂区211中形成第一掺杂层；通过第二掺杂工艺对所述第二源漏掺杂区212进行掺杂，在所述第二晶体管区II接触孔240底部和侧壁的第二源漏掺杂区212中形成第二掺杂层。
所述形成方法还包括：对所述掺杂层进行防扩散处理。
本实例中，对所述掺杂层进行防扩散处理的步骤包括：对所述第一掺杂层进行第一防扩散处理；对所述第二掺杂层进行第二防扩散处理。
请参考图7，通过第二掺杂工艺对所述第二源漏掺杂区212进行掺杂，在所述第二源漏掺杂区212掺入第二掺杂离子，在所述第一晶体管区I接触孔240底部和侧壁暴露出的第二源漏掺杂区212中形成第二掺杂层252。
所述第二掺杂层252用于降低所述第二源漏掺杂层252与后续形成的插塞之间的电阻。
所述第二掺杂工艺具有各向同性，所述第二掺杂工艺的各向同性为所述第二掺杂工艺能够在各个方向上对所述第二源漏掺杂区212进行掺杂，且各方向上的掺杂浓度较均匀。
因此，所述第二掺杂工艺能够使所述第二晶体管区II接触孔240的侧壁和底部都掺入第二掺杂离子，从而使所述第二掺杂层252位于所述第二晶体管区II接触孔240侧壁和顶部暴露出的第二源漏掺杂区212中。第二掺杂工艺具有各向同性，能够使所述第二掺杂层252中第二掺杂离子的浓度较均匀，从而使后续形成的插塞与第二源漏掺杂区212之间的电阻率较均匀。因此，所述形成方法能够改善所形成半导体结构的性能。
本实施例中，通过第二掺杂工艺对所述第二源漏掺杂区212进行掺杂的步骤包括：在所述第一晶体管区I介质层230上和接触孔240中形成第一光刻胶210；以所述第一光刻胶210为掩膜，通过第二掺杂工艺对所述第二源漏掺杂区212进行掺杂，在所述接触孔240底部和侧壁暴露出的第二源漏掺杂区212中形成第二掺杂层252；去除所述第一光刻胶210。
本实施例中，形成第一光刻胶210的工艺包括旋涂工艺。
本实施例中，所述第二晶体管区II用于形成PMOS晶体管，所述第二掺杂离子为硼离子。在其他实施例中，所述第二掺杂离子还可以为铟离子。
本实施例中，所述第二掺杂工艺为等离子掺杂工艺。
等离子体掺杂工艺主要依靠等离子体向第二源漏掺杂区212的扩散对第二源漏掺杂区212进行掺杂，等离子体的扩散不具有方向性，且等离子之间的散射也能够增加掺杂浓度的均匀性。因此，等离子体掺杂工艺能够实现各向同性掺杂。
如果所述第二掺杂层252中第二掺杂离子的浓度过小，不利于后续形成的插塞与第二源漏掺杂区211之间电阻的减小。本实施例中，所述第二掺杂层252中第二掺杂离子的浓度大于5E14atoms/cm2。
掺杂剂量与掺杂浓度有关。参杂剂量过高，容易使掺杂浓度过低，容易使掺杂浓度过低，掺杂剂量过大容易产生材料浪费。具体的，本实施例中，所述掺杂剂量为1E15atoms/cm2～5E15atoms/cm2。
本实施例中，所述第二掺杂工艺的掺杂能量较小，能够降低第二掺杂工艺的方向性。然而如果掺杂能量过低，容易影响掺杂效率，因此，所述掺杂能量为：10eV～20KeV。
本实施例中，掺杂温度越高，等离子在所述第二源漏掺杂区212中的扩散速率越大，生产效率越高；然而温度过高容易使半导体结构的性能降低。具体的，本实施例中，所述掺杂温度为25℃～800℃。
本实施例中，气压越小，真空度越高，对等离子扩散的影响越小；真空度过高容易增加对设备的要求。因此，本实施例中，真空度为1mtorr～1000mtorr。
请参考图8，通过所述第二掺杂工艺对所述第二源漏掺杂区212掺杂之后，还包括：对所述第二掺杂层252进行第二防扩散处理。
所述第二防扩散处理用于减小所述第二掺杂层252中第二掺杂离子向第二掺杂层252表面的扩散，从而降低所述第二掺杂离子的损耗。
本实施例中，所述第二防扩散处理的步骤包括：对所述第二掺杂层252进行第二离子注入，所述第二离子注入的注入离子为第二防扩散离子。
在进行所述第二离子注入的过程中，所述第二防扩散离子具有一定的动能，能够与所述第二掺杂离子发生碰撞，使所述第二掺杂离子向所述第二源漏掺杂区212内部移动。
本实施例中，所述第二防扩散离子的原子量大于所述第二掺杂离子的原子量。在其他实施例中，所述第二防扩散离子的原子量也可以等于或小于所述第二掺杂离子的原子量。
所述第二防扩散离子的原子量大于所述第二掺杂离子的原子量，在第二离子注入的过程中，能够较容易地使所述第二掺杂离子向所述第二源漏掺杂区252内部移动，从而减小第二掺杂离子的损耗。
本实施例中，所述第二掺杂离子为硼离子，所述第二防扩散离子为铟离子。
本实施例中，通过第二离子注入对所述第二掺杂层252进行第二防扩散处理的工艺参数包括：注入能量为200eV～20KeV；注入剂量小于1E14atoms/cm2；注入角度为0度～20度。
在其他实施例中，还可以通过等离子体掺杂工艺对所述第二掺杂层进行第二防扩散处理，在所述掺杂层中掺入重离子，所述重离子的原子量大于所述掺杂离子的原子量。
请参考图9，第二防扩散处理之后，通过第一掺杂工艺对所述第一源漏掺杂区211进行掺杂，在所述第一源漏掺杂区211掺入第一掺杂离子，在所述第一晶体管区I接触孔240底部和侧壁暴露出的第一源漏掺杂区211中形成第一掺杂层251，所述第一掺杂工艺具有各向同性。
所述第一掺杂层251用于降低所述第一源漏掺杂层211与后续形成的插塞之间的电阻。
所述第一掺杂工艺具有各向同性，所述第一掺杂工艺的各向同性为所述第一掺杂工艺能够在各个方向上对所述第一源漏掺杂区211进行掺杂，且各方向上的掺杂浓度较均匀。
因此，所述第一掺杂工艺能够使所述第一晶体管区I接触孔240的侧壁和底部都掺入第一掺杂离子，从而使所述第一掺杂层251位于所述第一晶体管区I接触孔240侧壁和顶部的第一源漏掺杂区211中。第一掺杂工艺具有各向同性，能够使所述第一掺杂层251中第一掺杂离子的浓度较均匀，从而使后续形成的插塞与第一源漏掺杂区211之间的电阻率较均匀。因此，所述形成方法能够改善所形成半导体结构的性能。
本实施例中，通过第一掺杂工艺对所述第一源漏掺杂区211进行掺杂的步骤包括：在所述第二晶体管区II介质层230上和接触孔240中形成第二光刻胶220；以所述第二光刻胶220为掩膜，通过第一掺杂工艺对所述第一源漏掺杂区211进行掺杂，在所述接触孔240底部和侧壁暴露出的第一源漏掺杂区211中形成第一掺杂层251；去除所述第二光刻胶220。
本实施例中，形成第二光刻胶220的工艺包括旋涂工艺。
本实施例中，所述第一晶体管区I用于形成NMOS，所述第一掺杂离子为磷离子。在其他实施例中，所述第一掺杂离子也可以为砷离子或锑离子。
本实施例中，所述第一掺杂工艺包括等离子体掺杂工艺。
等离子体掺杂工艺主要依靠等离子体向第一源漏掺杂区211的扩散对基第一源漏掺杂区211进行掺杂，等离子体的扩散不具有方向性，且等离子之间的散射也能够增加掺杂浓度的均匀性。因此，等离子参杂工艺能够实现各向同性掺杂。
如果所述第一掺杂层251中第一掺杂离子的浓度过小，不利于后续形成的插塞与第一源漏掺杂区211之间电阻的减小。本实施例中，所述第一掺杂层251中第二掺杂离子的浓度大于5E14atoms/cm2。
掺杂剂量与掺杂浓度有关。参杂剂量过高，容易使掺杂浓度过低，容易使掺杂浓度过低，掺杂剂量过大容易产生材料浪费。具体的，本实施例中，所述掺杂剂量为1E15atoms/cm2～5E15atoms/cm2
所述第一掺杂工艺的掺杂能量较小，能够降低第一掺杂工艺的方向性。然而如果掺杂能量过低，容易影响掺杂效率。因此，本实施例中，所述掺杂能量为：10eV～20KeV。
掺杂温度越高，等离子在所述第一源漏掺杂区211中的扩散速率越大，生产效率越高；然而温度过高容易使半导体结构的性能降低。具体的，本实施例中，所述掺杂温度为25℃～800℃。
气压越小，真空度越高，对等离子扩散的影响越小；真空度过高容易增加对设备的要求。因此，本实施例中，真空度为1mtorr～1000mtorr。
请参考图10，形成第一掺杂层251之后，所述形成方法还包括：对所述第一掺杂层251进行第一防扩散处理。
所述第一防扩散处理用于减小所述第一掺杂层251第一掺杂离子向第一掺杂层251表面的扩散，从而降低所述第一掺杂离子的损耗。
本实施例中，对所述第一掺杂层251进行第一防扩散处理的步骤包括：对所述第一掺杂层251进行第一离子注入，所述第一离子注入的注入离子为第一防扩散离子。
在进行所述第一离子注入的过程中，所述第一防扩散离子具有一定的动能，能够与所述第一掺杂离子发生碰撞，使所述第一掺杂离子向所述第一源漏掺杂区251内部移动。
本实施例中，所述第一防扩散离子的原子量大于所述第一掺杂离子的原子量。在其他实施例中，所述第一防扩散离子的原子量还可以等于或小于所述第一掺杂离子的原子量。
所述第一防扩散离子的原子量大于所述第一掺杂离子的原子量，在离子注入的过程中，能够使所述第一掺杂离子向所述第一源漏掺杂区211内部移动，从而减小第一掺杂离子的损耗。
本实施例中，所述第一掺杂离子为磷离子，所述第一防扩散离子为砷离子或锑离子。
本实施例中，通过第一离子注入对所述第一掺杂层251进行第一防扩散处理的工艺参数包括：注入能量为200eV～20KeV；注入剂量小于1E14atoms/cm2；注入角度为0度～20度。
在其他实施例中，还可以通过等离子体掺杂工艺对所述第一掺杂层进行第一防扩散处理，在所述掺杂层中掺入重离子，所述重离子的原子量大于所述掺杂离子的原子量。
请参考图11，在所述接触孔240中形成插塞241。
所述插塞241用于实现所述源漏掺杂区与外部电路的电连接。
本实施例中，所述插塞241的材料为钨。在其他实施例中，所述插塞的材料还可以为铜。
本实施例中，通过化学气相沉积工艺形成所述插塞241。通过化学气相沉积工艺形成的插塞241的阶梯覆盖性好。
本实施例中，在形成所述插塞241之前，所述形成方法还包括：在所述掺杂层表面形成金属化物。
综上，本实施例中，通过掺杂工艺对所述源漏掺杂区进行掺杂，在所述接触孔底部和侧壁暴露出的源漏掺杂区中形成掺杂层，所述掺杂层能够降低源漏掺杂区与插塞之间的电阻。在对所述源漏掺杂区进行掺杂之后，所述掺杂离子能够分布于接触孔底部和侧壁暴露出的所述源漏掺杂区中，且能够使掺杂离子在所述源漏掺杂区中分布均匀。因此，所述形成方法能够使插塞与源漏掺杂区之间的电阻率分别较均匀，从而能够改善所形成半导体结构性能。
进一步，形成所述插塞之前，对所述掺杂层进行防扩散处理。所述防扩散处理能够减小所述掺杂层中掺杂离子向掺杂层表面的扩散，从而能够增加所述掺杂中掺杂离子浓度，进而减小所述插塞与源漏掺杂区之间的电阻。因此，所述形成方法能够进一步改善半导体结构性能。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (15)

1.一种半导体结构的形成方法，其特征在于，包括：
形成基底，所述基底包括：衬底，位于衬底上的栅极结构，位于所述栅极结构两侧衬底中的源漏掺杂区，位于所述衬底和栅极结构顶部上的介质层；
形成贯穿所述介质层的接触孔，所述接触孔底部延伸至所述源漏掺杂区中；
形成所述接触孔之后，通过掺杂工艺在所述源漏掺杂区中掺入掺杂离子，在所述接触孔底部和侧壁暴露出的源漏掺杂区中形成掺杂层；
在形成所述掺杂层之后，在所述接触孔中形成插塞，在所述接触孔中形成插塞之前，对所述掺杂层进行防扩散处理。
2.如权利要求1所述的半导体结构的形成方法，其特征在于，所述掺杂工艺具有各向同性；所述掺杂工艺为等离子体掺杂工艺。
3.如权利要求1所述的半导体结构的形成方法，其特征在于，所述源漏掺杂区用于形成NMOS晶体管，所述掺杂离子为磷离子、砷离子或锑离子。
4.如权利要求1所述的半导体结构的形成方法，其特征在于，所述源漏掺杂区用于形成PMOS晶体管，所述掺杂离子为硼离子或铟离子。
5.如权利要求1所述的半导体结构的形成方法，其特征在于，所述掺杂层中掺杂的离子浓度大于5E14 atoms/cm2；
所述掺杂工艺的工艺参数包括：掺杂剂量为1E15atoms/cm2～5E15atoms/cm2，掺杂能量为：10eV～20KeV，气压为1mtorr～1000mtorr，掺杂温度为25℃～800℃。
6.如权利要求1所述的半导体结构的形成方法，其特征在于，通过离子注入对所述掺杂层进行防扩散处理，在所述掺杂层中注入重离子。
7.如权利要求6所述的半导体结构的形成方法，其特征在于，所述重离子的原子量大于所述掺杂离子的原子量。
8.如权利要求1所述的半导体结构的形成方法，其特征在于，通过等离子体掺杂工艺对所述掺杂层进行所述防扩散处理，在所述掺杂层中掺入重离子，所述重离子的原子量大于所述掺杂离子的原子量。
9.如权利要求7或8所述的半导体结构的形成方法，其特征在于，所述源漏掺杂区用于形成NMOS晶体管，所述掺杂离子为磷离子；
所述重离子为砷离子或锑离子。
10.如权利要求7或8所述的半导体结构的形成方法，其特征在于，所述源漏掺杂区用于形成PMOS晶体管，所述掺杂离子为硼离子；
所述重离子为铟离子。
11.如权利要求6所述的半导体结构的形成方法，其特征在于，所述离子注入的工艺参数包括：注入能量为200eV～20KeV；注入剂量小于1E14atoms/cm2；注入角度为0度～20度。
12.如权利要求1所述的半导体结构的形成方法，其特征在于，形成所述插塞之前，形成所述掺杂层之后，还包括：在所述接触孔底部和侧壁表面形成金属层，与所述掺杂层接触的金属层与所述掺杂层反应形成金属化物。
13.如权利要求1所述的半导体结构的形成方法，其特征在于，所述基底包括：第一晶体管区和第二晶体管区；
所述栅极结构包括：位于第一晶体管区衬底上的第一栅极结构；位于第二晶体管区衬底上的第二栅极结构；
所述源漏掺杂区包括：位于第一栅极结构两侧衬底中的第一源漏掺杂区；
位于第二栅极结构两侧衬底中的第二源漏掺杂区；
所述掺杂层包括：位于所述第一源漏掺杂区表面的第一掺杂层和位于所述第二源漏掺杂区表面的第二掺杂层。
14.如权利要求13所述的半导体结构的形成方法，其特征在于，通过掺杂工艺对所述源漏掺杂区进行掺杂的步骤包括：
在所述第一晶体管区介质层上和接触孔中形成第一光刻胶；
以所述第一光刻胶为掩膜，通过第二掺杂工艺对所述第二源漏掺杂区进行掺杂，在所述第二晶体管区接触孔底部和侧壁暴露出的第二源漏掺杂区中形成第二掺杂层；
去除所述第一光刻胶；
在所述第二晶体管区介质层上和接触孔中形成第二光刻胶；
以所述第二光刻胶为掩膜，通过第一掺杂工艺对所述第一源漏掺杂区进行掺杂，在所述第一晶体管区接触孔底部和侧壁暴露出的第一源漏掺杂区中形成第一掺杂层；
去除所述第二光刻胶。
15.如权利要求14所述的半导体结构的形成方法，其特征在于，在所述接触孔中形成插塞之前，还包括：对所述掺杂层进行防扩散处理；
所述防扩散处理的步骤包括：通过第二掺杂工艺对所述第二源漏掺杂区进行掺杂之后，以所述第一光刻胶为掩膜对所述第二掺杂层进行第二防扩散处理；
通过第一掺杂工艺对所述第一源漏掺杂区进行掺杂之后，以所述第二光刻胶为掩膜对所述第一掺杂层进行第一防扩散处理。
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