CN107579049A - 半导体封装及其制造方法 - Google Patents

半导体封装及其制造方法 Download PDF

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Publication number
CN107579049A
CN107579049A CN201610867673.6A CN201610867673A CN107579049A CN 107579049 A CN107579049 A CN 107579049A CN 201610867673 A CN201610867673 A CN 201610867673A CN 107579049 A CN107579049 A CN 107579049A
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CN
China
Prior art keywords
tube core
wiring layer
die
certain embodiments
layer
Prior art date
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Pending
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CN201610867673.6A
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English (en)
Inventor
余振华
余俊辉
余国宠
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN107579049A publication Critical patent/CN107579049A/zh
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
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    • G06V40/12—Fingerprints or palmprints
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
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    • G06V40/13—Sensors therefor
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Abstract

本发明实施例提供一种半导体封装及其制造方法。半导体封装包括第一布线层、位于第一布线层之上的第一管芯、包覆位于第一布线层上的至少一第二管芯与至少一第三管芯的封装模塑体以及连接至第一布线层的至少一第四管芯与导电部件。第一管芯的导通孔电性连接至穿透封装模塑体的贯穿介层孔且电性连接至第一布线层。半导体封装更可包括第二布线层，其位于封装模塑体上且位于第一管芯、第二管芯与第三管芯之间。

Description

半导体封装及其制造方法
技术领域
本发明实施例是有关于一种半导体封装及其制造方法。
背景技术
通常可以在整片半导体芯片上制造半导体组件和集成电路。在芯片层级工艺中，针对芯片中的管芯进行加工处理，并且可以将管芯与其他的半导体组件一起封装。目前各方正努力开发适用于芯片级封装的不同技术。
发明内容
本发明实施例提供半导体封装结构，能有效地改善半导体封装电性性能。
根据本发明的一些实施例，半导体封装包括第一布线层、第一管芯、至少一第二管芯、至少一第三管芯、封装模塑体、贯穿介层孔、导电部件以及至少一第四管芯。第一管芯位于第一布线层之上且具有至少一导通孔。第一管芯包括至少一个传感器。第二管芯与第三管芯设置于第一布线层上且位于第一布线层与第一管芯之间。封装模塑体设置于第一布线层上且位于第一布线层与第一管芯之间，并且封装模塑体包覆第二管芯与第三管芯。穿透封装模塑体的贯穿介层孔位于第一布线层与第一管芯之间且位于所述至少一第二管芯与所述至少一第三管芯旁边。贯穿介层孔电性连接至第一管芯的至少一导通孔且电性连接至第一布线层。导电部件电性连接至第一布线层。第四管芯电性连接至第一布线层且设置于导电部件旁边。
根据本发明的一些实施例，一种半导体封装包括第一布线层、第一管芯、至少一第二管芯、至少一第三管芯、贯穿介层孔以及封装模塑体。第一管芯包括至少一个传感器和导通孔于其中，第一布线层设置在第一管芯之下。第二管芯与第三管芯设置在第一布线层上且位于第一布线层和第一管芯之间。贯穿介层孔设置在第一布线层上、位于第一布线层和第一管芯之间并且设置于至少一第二管芯与至少一第三管芯旁边。导通孔的位置与贯穿介层孔的位置实质上大致对齐。第一管芯的导通孔与贯穿介层孔电性连接，并且导通孔和贯穿介层孔电性连接至第一布线层。封装模塑体设置于第一布线层上且位于第一布线层和第一管芯之间，而且封装模塑体包覆密封至少一第二管芯、至少一第三管芯以及贯穿介层孔。
根据本发明的一些实施例，半导体封装的制造方法包括提供具有第一管芯的芯片于载体上，其中第一管芯包括至少一个传感器和多个导通孔于其中。形成多个贯穿介层孔于第一管芯之上以及导通孔之上，其中导通孔的位置与贯穿介层孔的位置实质上大致对齐。第一管芯的导通孔与贯穿介层孔电性连接。设置至少一第二管芯与至少一第三管芯于第一管芯之上并且设置于贯穿介层孔旁边。形成封装模塑体于芯片的第一管芯之上并且封装模塑体包覆密封至少一第二管芯、至少一第三管芯以及贯穿介层孔。形成第一布线层于封装模塑体上。贯穿介层孔电性连接至第一布线层。设置至少一第四管芯于第一布线层上。第四管芯电性连接至第一布线层。设置导电部件在第一布线层上。从芯片移除载体并对芯片进行切割工艺而切割穿透至少芯片与封装模塑体，分离得到多个半导体封装。
基于上述，本发明实施例提供半导体封装结构及其制造方法，其中贯穿介层孔与导通孔的位置相对齐，贯穿介层孔直接接触导通孔或贯穿介层孔位置至少与导通孔位置重叠，可为位于封装模塑体不同层的多个管芯提供较短的电性连接路径，进而降低了封装结构厚度并改善提高封装结构的电性性能。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
图1A到图1J为依据本发明的一些实施例的半导体封装制造方法的各种阶段所形成的半导体封装的剖面示意图。
图2A为依据本发明的一些实施例的半导体封装的剖面示意图。
图2B为依据本发明的一些实施例的半导体封装的剖面示意图。
图3A到图3I为依据本发明的一些实施例的半导体封装制造方法的各种阶段所形成的半导体封装的剖面示意图。
图4A为依据本发明的一些实施例的半导体封装的剖面示意图。
图4B为依据本发明的一些实施例的半导体封装的剖面示意图。
附图标记说明：
10：半导体封装
100：芯片
102：载体
110：第一管芯
111：覆盖层
112：影像传感器
113：透镜阵列
114a：接触垫
114b：传感器图案
115：框架结构
116：导电接合结构
118：信号处理单元
120：导通孔
122：图案化的介电材料层
126：第二布线层
130：贯穿介层孔(TIVs)
140：第二管芯
141、151：接点
150：第三管芯
145：管芯附着膜
160：封装模塑体
170：第一布线层
170a：上表面
170b：下表面
172、128：顶金属图案层
174、124：底金属图案层
180：导电部件
190：连接器
200：第四管芯
S110：前表面
S140、S150：有源表面
250：保护层。
具体实施方式
以下揭露内容提供用于实施所提供的目标的不同特征的许多不同实施例或实例。以下所描述的构件及设置的具体实例是为了以简化的方式传达本发明为目的。当然，这些仅仅为实例而非用以限制。举例来说，于以下描述中，在第一特征上方或在第一特征上形成第二特征可包括第二特征与第一特征形成为直接接触的实施例，且亦可包括第二特征与第一特征之间可形成有额外特征使得第二特征与第一特征可不直接接触的实施例。此外，本发明在各种实例中可使用相同的组件符号及/或字母来指代相同或类似的部件。组件符号的重复使用是为了简单及清楚起见，且并不表示所欲讨论的各个实施例及/或设置本身之间的关系。
另外，为了易于描述附图中所绘示的一个构件或特征与另一组件或特征的关系，本文中可使用例如“在...下”、“在...下方”、“下部”、“在…上”、“在…上方”、“上部”及类似术语的空间相对术语。除了附图中所绘示的定向之外，所述空间相对术语意欲涵盖组件在使用或操作时的不同定向。设备可被另外定向(旋转90度或在其他定向)，而本文所用的空间相对术语相应地作出解释。
此外，文中所述用语诸如“第一”、“第二”、“第三”、“第四”等，其在文中的使用主要是便于描述图中所示相似或不同的组件或特征，并且可以根据叙述出现的顺序或上下文的描述而相互调换使用。
图1A到图1J为依据本发明的一些实施例的半导体封装制造方法的各种阶段所形成的半导体封装的剖面示意图。在实施例中所描述半导体的制造方法为芯片级封装工艺的一部分。在一些实施例中，图示绘出两个管芯以代表所述芯片的多个管芯，并且绘示出一或多个封装10来代表依照所述半导体封装制造方法而获得的多个半导体封装。参照图1A，提供一载体102，而载体102可以是玻璃载体或可适用于半导体封装制造方法的任何合适的载体。在一些实施例中，载体102其上设置涂覆有一个脱黏层(未图示)，脱黏层(debondlayer)的材料可以是能够使载体102与位于其上的各层或芯片轻易脱离的任意材料。参照图1A，在一些实施例中，首先提供包括第一管芯110的芯片100，并放置在载体102上，将包括第一管芯110的芯片100贴合到载体102上。在实施例中，如图1A所示，第一管芯110是传感器芯片(sensor chip)，其包括一或多个传感器(sensors)112。
在实施例中，第一管芯110包括至少一个指纹传感器例如光学指纹传感器或电容指纹传感器(capacitance fingerprint sensor)。在实施例中，第一管芯110设有形成于其中的导通孔120。在一实施例中，导通孔120是穿硅通孔(through silicon vias)或通过半导体通孔(through semiconductor vias)。在一些实施例中，导通孔120连接到传感器112的接点或接触垫114a，且电性连接到第一管芯110的传感器112。在一实施例中，接触垫114a设置在传感器112旁边的传感器图案114b，而传感器112的传感器图案114b是指传感器112用于检测光或信号的部分。在某些实施例中，导通孔120可以通过激光钻孔、机械钻孔或甚至光刻蚀刻等工艺(例如波希蚀刻工艺；Bosch etching process)来形成贯通第一管芯110的通孔开口，然后以电镀或沉积法形成金属材料例如铜或铜合金来填充所述开口而形成。在一实施例中，所提供的第一管芯110黏合到载体102，使第一管芯110的前表面S110朝向载体102(亦即在图1A面朝下)，而暴露出第一管芯110背面的导通孔120。在其他实施例中，第一管芯110包括一或多种类型的传感器，可包括例如电荷耦合组件(CCD)、主动像素传感器(APS)和接触式影像传感器(CIS)。在一些实施例中，第一管芯110还更包括信号处理电路、MEMS组件和/或光学装置例如透镜、偏光器或光谱仪等等。
在不同实施例中，如图1A'所示，第一管芯110是传感器芯片，其包括一或多个CMOS影像传感器112、导电接合结构116、信号处理单元118和导通孔120。依照一实施例，提供第一管芯110且连结至载体102，而所述管芯的前表面S110乃朝向载体102(亦即在图1A'中面朝下)，而在第一管芯110背侧的导通孔120被暴露出来。依照一实施例，进一步设置透镜阵列113、框架结构115和覆盖层111于第一管芯110的传感器112上，来配合影像传感器的背侧照明(backside illumination；BSI)模式。在一些实施例中，第一管芯110的导通孔120通过导电接合结构116电性连接到传感器112。依照一实施例，导电接合结构116包括混合连接结构(hybrid bonding structure)。依照一实施例，第一管芯110的传感器112可包括多种类型的传感器合并使用，不同类型的传感器用于检测不同波长的光。
参照图1B，在一些实施例中，形成图案化的介电材料层122在芯片100(包括第一管芯110)之上而露出导通孔120。在某些实施例中，形成介电材料层(未图示)于第一管芯110背面之上覆盖背面所露出的导通孔120，然后图案化介电材料层以形成图案化的介电材料层122并暴露出导通孔120。在一些实施例中，贯穿介层孔(TIVs)130形成在露出的导通孔之上，且TIVs130是直接连接到导通孔120。在一些实施例中，TIVs 130例如是贯穿整合扇出通孔(through InFO vias)。在某些实施例中，导通孔120的位置乃实质上大致对齐TIVs 130的位置(两者位置至少部分地重叠，例如从垂直方向看来投影式地重叠设置)。依照一实施例，导通孔120的一端连接到传感器112的接触垫114a，而导通孔120的另一端连接到TIV130。在一些实施例中，TIVs130与导通孔120的位置相对齐，且TIVs 130直接接触导通孔120或TIVs 130位置至少与导通孔120位置重叠。在一些实施例中，当TIVs 130是直接连接到导通孔120，为位于封装模塑体不同层的多个管芯提供较短的电性连接路径，进而降低了封装结构10的高度(厚度)并改善提高封装结构10的电性性能。在一些实施例中，形成TIVs 130可通过先形成掩模图案(未图标)来覆盖第一管芯110且图案开口露出导通孔120，接着以电镀或沉积法形成金属材料填充前述开口来形成TIVs，然后除去掩模图案。在一些实施例中，如图1B所示，其中虚线表示芯片100上的切割线，导通孔120和TIVs 130设置成靠近切割线但非直接位于切割在线，并且沿着第一管芯110的切割线设置。在某些实施例中，导通孔120沿着第一管芯110周边设置，其设置可使第一管芯的感测区域变大。然而，亦可根据产品的设计，将导通孔120设置在其他位置而非限定于第一管芯110周边，或设置在传感器112之间位置，而TIVs130的位置可以相应调整设置。
如图1C所示，在一些实施例中，提供第二管芯140和第三管芯150于图案化的介电材料层122上并位于第一管芯110之上。在某些实施例中，管芯附着膜145设置在第二管芯140、第三管芯150和图案化的介电材料层122之间，可以更好地粘合第二管芯140与第三管芯150至图案化介电材料层122上。在某些实施例中，如图1C所示，第二管芯140、第三管芯150和第一管芯110是背对背式连接。在一些实施例中，第二管芯140与第三管芯150设置在第一管芯110之上，且设置于TIVs 130旁边(位于TIVs所环绕的区域内)。在其他实施例中，取决于产品设计，TIVs 130设置于第二管芯140与第三管芯150之间。在一些实施例中，第二管芯140和第三管芯150是不同类型或相同类型的管芯，可以选自于应用专用集成电路(application-specific integrated circuit；ASIC)芯片、模拟芯片、传感器芯片、无线射频芯片、电压调节器芯片或存储器芯片。在一些实施例中，第二管芯140例如是ASIC芯片而第三管芯150例如是电压调节器芯片。在某些实施例中，既然第一管芯110内形成有导通孔120，则第二管芯140和第三管芯150可堆叠在第一管芯110上，而非彼此并排设置，而包含堆叠在不同层管芯的封装结构具有较小的外形尺寸(form factor)和更好的电性性能。虽然例示性实施例显示在芯片的第一管芯上堆叠两个管芯，但实际上，堆叠在芯片任一管芯上的管芯数量可以视产品的设计调整，并且芯片的类型不限于实施例所述。
参照图1D，在一些实施例中，形成封装模塑体160将位于第一管芯110上的第二管芯140、第三管芯150和TIVs 130包覆且密封于其内。依照一实施例，封装模塑体160填充于第二管芯140、第三管芯150以及TIVs 130之间的空间，并覆盖图案化介电材料层122。依照一实施例，封装模塑体160的材料包括例如环氧树脂、酚醛树脂或含硅树脂。
如图1D所示，在一些实施例中，对封装模塑体160进行平坦化工艺以露出TIVs 130的顶部。在某些实施例中，可以平坦化封装模塑体160直到暴露出TIVs 130、第二管芯140的有源表面S140和第三管芯150的有源表面S150。在一些实施例中，对于过塑模(over-molded)封装模塑体160和TIVs 130进行抛光，直到第二管芯140和第三管芯150的接点141、151露出来。依照一实施例，在平坦化之后，TIVs 130、封装模塑体160、第二管芯140和第三管芯150成为大致等高(亦即这四个部件的顶表面共平面)。在一些实施例中，封装模塑体160和TIVs 130的平坦化是利用研磨工艺或化学机械抛光(CMP)工艺。
参照图1E，在一些实施例中，在封装模塑体160、第二管芯140和第三管芯150之上以及在TIVs 130之上形成第一布线层(redistribution layer)170。在一些实施例中，第一布线层170电性连接至TIVs 130以及第二管芯140和第三管芯150。第一布线层170的形成包括依序地且交替地形成多层聚合物介电材料层以及多层金属图案层。在某些实施例中，金属图案层可以夹在聚合物介电材料层之间，但是顶金属图案层172的顶表面会露出来，而底金属图案层174连接到第二管芯140和第三管芯150的接点141、151以及TIVs130。在一些实施例中，金属图案层的材料包括例如铝、钛、铜、镍、钨和/或其合金。在一些实施例中，聚合物电介质材料层的材料包括例如聚酰亚胺、环氧树脂、丙烯酸树脂、酚醛树脂、苯并环丁烯(BCB)、聚苯并恶唑(PBO)或任何其他合适的聚合物类介电材料。在一些实施例中，第一布线层170电性连接到第二管芯140和第三管芯150，且通过TIVs 130和导通孔120而电性连接到第一管芯110。
参照图1F，在一些实施例中，将导电部件180设置于第一布线层170上。在一些实施例中，设置导电部件180之前，先将焊膏或焊剂施加于顶金属图案层172上，便于导电部件180能够更好地固定在顶金属图案层172上，而连接于导电部件180的顶金属图案层172的特定部分可视为导电部件180的UBM层或垫。在一些实施例中，设置于第一布线层170的顶金属图案层172上的导电部件180例如是焊球(solder balls)或球栅阵列球(BGA balls)，而位于导电部件180下面的顶金属图案层172的部分乃作为UBM层。在一些实施例中，部分的导电部件180通过第一布线层170、TIVs 130和导通孔120而电性连接至第一管芯110。
参照图1G，在一些实施例中，将第四管芯200设置于第一布线层170之上。在一些实施例中，在设置第四管芯200到第一布线层170的顶金属图案层172上之前，先将连接器190接到第四管芯200再利用覆晶连接(flip chip bonding)方式将第四管芯200连接到第一布线层170的顶金属图案层172上。在一些实施例中在设置连接器190之前，先施加焊膏或焊剂以便于固定与连结。在一些实施例中，连接器190例如是凸块(bumps)，而连接器190之下的顶金属图案层172部分可视为凸块垫。在一些实施例中，第四管芯200包括至少一个无源组件，例如电容、电阻、电感、转换器(transducers)和天线。在其他实施例中，第四管芯200可以是与第二管芯140或第三管芯150为相同类型或不同类型的芯片，可以选自于应用专用集成电路(ASIC)芯片、模拟芯片、传感器芯片、无线射频芯片、电压调节器芯片或存储器芯片。
在一些实施例中，导电部件180和第四管芯200电性连接到第一布线层170，而第四管芯200可通过连接器190和第一布线层170电性连接到第二管芯140和第三管芯150。在一些实施例中，第四管芯200可利用连接器190、第一布线层170、TIVs 130和导通孔120而电性连接到第一管芯110。
参照图1H，在一些实施例中，将载体102与芯片100的第一管芯脱胶分离开来。由于载体102的脱黏层，芯片100可轻易与载体102分离开来。在一些实施例中，芯片100从载体102脱胶开来后，第一管芯110的前表面S110暴露出来。
参照图1I，在一些实施例中，进行切割工艺沿着切割线(图中虚线)切割封装结构整体(至少切透穿过第一布线层170、封装模塑体160和芯片100)而得到个别且分离的半导体封装10。依照一实施例，切割工艺步骤包含机械式切锯工艺或激光切割芯片工艺。
参照图1J，在一些实施例中，形成保护层250于第一管芯110的前表面S110上。在一些实施例中，设置在第一管芯110前表面S110上的保护层250覆盖第一管芯110的传感器图案114b并保护第一管芯110的前表面S110。在一些实施例中，保护层250包括例如玻璃盖、盖板、硬涂层或任何其它合适的保护膜。在一些实施例中，保护层250更包括额外的功能层，例如偏光膜、彩色膜、防反射层或防眩光层。在某些实施例中，保护层250至少允许特定信号或某些波长的光通过。在一些实施例中，施加粘合剂(未示)到前表面S110上或到保护层250上，然后，粘接保护层250到半导体封装10的第一管芯110上。在其他实施例中，在进行切割工艺之前，可将保护层黏着至第一管芯上，本文所包括的范围涵盖对于制造过程的步骤或某些可选择的程序所进行的调整或修改。在例示性实施例中，前述制造方法是芯片级封装工艺的一部分，并在芯片切割过程之后获得多个半导体封装10。在后续的工艺中，半导体封装结构10可被翻转(上下颠倒)，便于进一步的处理，利用导电部件180连接到电路板或系统板上，而使半导体封装结构10安装至电路板或系统板上。以此种结构设置来看，保护层250正面朝上而第一管芯110是用来检测或感测光或信号。
在其他实施例中，半导体封装10更可包括额外的管芯设置在第一管芯110之上，或设置在第二管芯140和第三管芯150的旁边或上面，而可通过调整布线层以电性连接其他的管芯。本发明的结构和/或制造过程并非仅限于例示性实施例。
图2A为依据本发明的一些实施例的半导体封装的剖面示意图。图2A的半导体封装10可按照图1A及图1B-1J所描述的制造流程来制造。参照图2A，在一些实施例中，半导体封装10包括保护层250、第一管芯110、第二管芯140、第三管芯150、封装模塑体160、第一布线层170、第四管芯200和导电部件180。在一些实施例中，第一管芯110、第二管芯140、第三管芯150和封装模塑体160夹在保护层250和第一布线层170之间。在一些实施例中，保护层250覆盖第一管芯110的前表面S110。在一些实施例中，第二管芯140和第三管芯150被密封在封装模塑体160之中，而贯穿封装模塑体160的TIVs130设置在第二管芯140和第三管芯150旁边。除了电性连接功能之外，TIVs130也可用作散热途径或作为用于射频应用的屏蔽结构。
在例示性的实施例中，如图2A所示，第一管芯110是例如传感器芯片，其包括一或多个传感器112。在某些实施例中，第一管芯110包括至少一个指纹传感器，例如光学指纹传感器或电容指纹传感器等。在某些实施例中，如图2A所示，第一管芯110包括一个或多个导通孔120，并且导通孔120的两相对端分别连接到第一管芯110的接触垫114a和TIVs 130。在一些实施例中，TIVs 130的两相对端分别连接到导通孔120和第一布线层170。依照一实施例，导通孔120与TIVs 130直接接触。在一些实施例中，介电材料层122设置于第一管芯110和封装模塑体160之间，介电材料层122和第一布线层170分位于封装模塑体160两相对侧。如图2A所示设置看来，在某些实施例中，第二管芯140和第三管芯150设置在第一布线层170的上表面170a上，第二管芯140和第三管芯150的接点141、151连接到第一布线层170，而导电部件180设置在第一布线层170的下表面170b上并连接至第一布线层170。在某些实施例中，第四管芯200通过设置在第一布线层170下表面上的连接器190而连接至第一布线层170。
在一些实施例中，第二管芯140和第三管芯150为相同类型或不同类型的芯片，可以选自于应用专用集成电路(ASIC)芯片、模拟芯片、传感器芯片、无线射频芯片、电压调节器芯片或存储器芯片。在一些实施例中，第二管芯140是ASIC芯片而第三管芯150是电压调节器芯片。在一些实施例中，第四管芯200包括至少一个无源组件，例如电容、电阻、电感、转换器(transducers)和天线。在某些实施例中，保护层250允许特定波长的光(可见光、红外线或紫外线或各种颜色的光)通过或者特定的信号通过。在一些实施例中，保护层250包括例如玻璃盖、盖板、硬涂层或任何其它合适的保护膜。在一些实施例中，保护层250更包括额外的功能层，例如偏光膜、彩色膜、防反射层或防眩光层。
图2B为依据本发明的一些实施例的半导体封装的剖面示意图。图2B的半导体封装10可按照图1A’(而非图1A的步骤)及图1B-1I所描述的制造流程来制造。如图2B所示，在一些实施例中，类似于图2A所示的半导体封装10，图2B中的半导体封装10包括第一管芯110、第二管芯140、第三管芯150、封装模塑体160、第一布线层170、第四管芯200和导电部件180。如图2B所示，第一管芯110是传感器芯片，其包括至少一CMOS影像传感器112、导电接合结构116、信号处理单元118和导通孔120。在一些实施例中，透镜阵列113设置位于传感器112的传感器图案114b上方。依照一实施例，第一管芯110设置在介电材料层122上，而其前表面S110朝向封装模塑体160外侧(亦即图2B中面朝上)，第一管芯110的导通孔120连接到TIVs130。在一些实施例中，第一管芯110内的导通孔120利用导电接合结构116电性连接到传感器112。依照一实施例，传感器112和信号处理元件118通过导电接合结构116电性连接，并且第一管芯110利用导电接合结构116、导通孔120和TIVs 130电性连接至第一布线层170。依照一实施例，导电接合结构116包括混合连接结构。
在某些实施例中，如图2B所示，第一管芯110的导通孔120的两端分别连接到第一管芯110的导电接合结构116和TIVs 130。在一些实施例中，TIVs130的两端分别连接到导通孔120和第一布线层170。依照一实施例，导通孔120是与TIVs 130直接接触。与图2A类似或基本上相同的部件会使用相同的数字标示，并且此处将不再重复相同部件的某些细节或描述。
图3A到图3I为依据本发明的一些实施例的半导体封装制造方法的各种阶段所形成的半导体封装的剖面示意图。在其他实施例中，如图3A所示，于黏在载体102上芯片100的第一管芯110上形成第二布线层126，如图1A'中所描述的工艺步骤。类似于或基本上相同于图1A'所描述的部件将使用相同的数字标示，并且此处将不再重复相同部件的某些细节或描述。第二布线层126覆盖住第一管芯110的导通孔120和信号处理元件118，并且与第一管芯110的信号处理元件118和导通孔120连接。在一些实施例中，第二布线层126利用第一管芯110的导通孔120和导电接合结构116而电性连接至第一管芯110中的传感器112和信号处理元件118。第二布线层126的形成包括依序地且交替地形成多层聚合物介电材料层以及多层金属图案层。在某些实施例中，金属图案层可以夹在聚合物介电材料层之间，但是顶金属图案层128的顶表面会露出来，而底金属图案层124连接到第一管芯110的导通孔120。此处的布线层与前面的实施例描述的布线层可具有相似的设置，并且所使用的金属图案层和/或聚合物介电材料层采用类似的材料，故在此将不再复述。
在一些实施例中，如图3B所示，贯穿介层孔(TIVs)130形成于第二布线层126上，并连接到第二布线层126露出的顶金属图案层128。导通孔120通过第二布线层126电性连接到TIVs 130，使得TIVs 130和/或导通孔120的布局设计更加灵活。依照一实施例，导通孔120的一端连接到导电接合结构116的部分，而导通孔120另一端连接到第二布线层126的底金属图案层124。在一些实施例中，TIVs 130可以利用形成掩模图案覆盖第二布线层126，而其开口暴露部分第二布线层126，利用电镀或沉积形成金属材料填充开口以形成TIVs，然后除去掩模图案。在一些实施例中，如图3B所示，其中虚线表示芯片100的切割线，导通孔120和TIVs 130的设置靠近切割线(但是不能直接位在切割在线)，且设置相邻于第一管芯110的周边。
参照图3C，在一些实施例中，提供第二管芯140和第三管芯150并设置在第二布线层126上以及第一管芯110之上。在某些实施例中，第二管芯140和第三管芯150接合到第二布线层126，且第二管芯140的有源表面S140和第三管芯150的有源表面S150面对第二布线层126且连接到第二布线层126。在一些实施例中，第二管芯140和第三管芯150的接点141、151经由覆晶接合技术连接到第二布线层126所露出的顶金属图案层128。在某些实施例中，如图3C所示，第二管芯140和第三管芯150的前侧连接到第一管芯110的背侧，亦即采面对背式连接。在一些实施例中，第二管芯140与第三管芯150设置在第一管芯110之上且位于TIVs130旁边。在一些实施例中，取决于产品设计，一些TIVs 130设置于第二管芯140和第三管芯150之间或设置于第二管芯140和第三管芯150周围。在一些实施例中，第二管芯140和第三管芯150为相同类型或不同类型的芯片，可以选自于应用专用集成电路(ASIC)芯片、模拟芯片、传感器芯片、无线射频芯片、电压调节器芯片或存储器芯片。在一些实施例中，第二管芯140例如是射频芯片而第三管芯150例如是存储器芯片。堆叠在芯片上的管芯数量和/或类型可以视产品的设计调整或修改。在一些实施例中，第二管芯140和第三管芯150可以通过第二布线层126和导通孔120电性连接至第一管芯110。于第一管芯110内形成导通孔120，则第二管芯140和第三管芯150可堆叠在第一管芯110上面而非彼此并排设置，而包含堆叠在不同层管芯的封装结构具有较小的外形尺寸和更好的电性性能。
参照图3D，在一些实施例中，形成封装模塑体160将位于第一管芯110上的第二管芯140、第三管芯150和TIVs 130包覆且密封于其内。如图3D，在一些实施例中，对封装模塑体160进行平坦化工艺，直到TIVs 130的顶部露出来。在某些实施例中，可以平坦化封装模塑体160直至TIVs 130和第二管芯140和第三管芯150的背面暴露出来。
如图3E所示，在一些实施例中，在封装模塑体160和TIVs 130上形成第一布线层170。在一些实施例中，第一布线层170电性连接到TIVs 130，且可以电性连接到第二管芯140和第三管芯150。第一布线层170的形成及所使用材料等细节可如前述段落所述，故在此不再重复。在某些实施例中，第一布线层170的顶金属图案层172的顶面暴露出来，而底金属图案层174连接到TIVs 130。在一些实施例中，第一布线层170通过TIVs 130和第二布线层126可以电性连接到第二管芯140和/或第三管芯150，并且通过TIVs130、第二布线层126和导通孔120而电性连接到第一管芯110。
如图3F所示，将导电部件180设置于第一布线层170的顶金属图案层172上。在一些实施例中，设置导电部件180之前，先将焊膏或焊剂施加于顶金属图案层172上，便于导电部件180能够更好地固定在顶金属图案层172上，而连接于导电部件180的顶金属图案层172的特定部分可视为导电部件180的UBM层或垫。在一些实施例中，设置于第一布线层170的顶金属图案层172上的导电部件180例如是焊球(solder balls)或球栅阵列球(BGA balls)，而位于导电部件180下面的顶金属图案层172的部分乃作为UBM层。在一些实施例中，部分的导电部件180通过第一布线层170、TIVs 130、第二布线层126和导通孔120而电性连接至第一管芯110。
参照图3G，在一些实施例中，将第四管芯200设置于第一布线层170的表面170b上。在一些实施例中，在设置第四管芯200到第一布线层170的顶金属图案层172上之前，先将连接器190接到第四管芯200再利用覆晶连接(flip chip bonding)方式将第四管芯200连接到第一布线层170的顶金属图案层172上。在一些实施例中在设置连接器190之前，先施加焊膏或焊剂以便于固定与连结。在一些实施例中，连接器190例如是凸块(bumps)，而连接器190之下的顶金属图案层172部分可视为凸块垫。在一些实施例中，第四管芯200包括至少一个无源组件，例如电容、电阻、电感、转换器(transducers)和天线。在其他实施例中，第四管芯200可以是与第二管芯140或第三管芯150为相同类型或不同类型的芯片，可以选自于应用专用集成电路(ASIC)芯片、模拟芯片、传感器芯片、无线射频芯片、电压调节器芯片或存储器芯片。
在一些实施例中，第四管芯200通过连接器190、第一和第二布线层170、126与TIVs130而电性连接到第二管芯140和/或第三管芯150。在一些实施例中，第四管芯200可通过连接器190、第一和第二布线层170、126、TIVs 130和导通孔120而电性连接到第一管芯110。
参照图3H，在一些实施例中，将载体102与芯片100脱胶分离开来。在一些实施例中，芯片100从载体102脱胶开来后，第一管芯110的前表面S110(覆盖层111)暴露出来。
参照图3I，在一些实施例中，进行切割工艺沿着切割线(图中虚线)切割封装结构整体(至少切透穿过第一布线层170、封装模塑体160、第二布线层126和芯片100)而得到个别且分离的半导体封装10。
图4A为依据本发明的一些实施例的半导体封装的剖面示意图。图4A的半导体封装10可按照图1A’及图3A-3I所描述的制造流程来制造。参照图4A，在一些实施例中，半导体封装10包括第一管芯110、第二布线层126、第二管芯140、第三管芯150、封装模塑体160、第一布线层170、第四管芯200和导电部件180。在一些实施例中，第一管芯110设置在第二布线层126上，而第二管芯140、第三管芯150和封装模塑体160夹在第二布线层126和第一布线层170之间。在一些实施例中，如图4A的结构设置所示，第一管芯110是传感器芯片，其包括至少一CMOS影像传感器112、导电接合结构116、信号处理单元118和导通孔120。依照一实施例，第一管芯110设置在第二布线层126上，而第一管芯110的前表面S110中朝向封装模塑体160外侧(亦即在图4A中面朝上)，第一管芯110的导通孔120连接至第二布线层126。在一些实施例中，在第一管芯110内的导通孔120是通过导电接合结构116电性连接到传感器112。依照一实施例，第一管芯110通过导电接合结构116、导通孔120、第二布线层126和TIVs 130则可以电性连接到第一布线层170、导电部件180或第四管芯200。在一些实施例中，第二管芯140和第三管芯150被封装在封装模塑体160内，而贯穿封装模塑体160的TIVs 130则设置在第二管芯140和第三管芯150的旁边且环绕第二管芯140和第三管芯150。
图4B为依据本发明的一些实施例的半导体封装的剖面示意图。图4B的半导体封装10可按照图1A、图3A-3I以及图1J所描述的制造流程来制造。如图4B所示，在一些实施例中，半导体封装10包括保护层250、第一管芯110、第二布线层126、第二管芯140、第三管芯150、封装模塑体160、第一布线层170、第四管芯200和导电部件180。在一些实施例中，第一管芯110设置在第二布线层126上，而第二管芯140、第三管芯150和封装模塑体160夹在第二布线层126和第一布线层170之间。在一些实施例中，如图4B的结构设置所示，第一管芯110是传感器芯片，其包括一或多个传感器112。在某些实施例中，第一管芯110包括至少一个指纹传感器例如光学指纹传感器或电容指纹传感器。在某些实施例中，如图4B所示，导通孔120的两相对端分别连接到第一管芯110的接触垫114a和第二布线层126。在一些实施例中，TIVs130的两相对端分别连接到第二布线层126和第一布线层170。在一些实施例中，第二布线层126设置在第一管芯110和封装模塑体160之间，第二布线层126和第一布线层170分位于封装模塑体160的两相对侧。从图4B中所示的设置看来，在某些实施例中，第二管芯140和第三管芯150设置在第一布线层170的上表面170a上，第二管芯140和第三管芯150的接点141、151连接到第二布线层126。导电部件180设置在第一布线层170的下表面170b上且连接至第一布线层170。在某些实施例中，第四管芯200通过设置在第一布线层170的下表面170b上的连接器190而连接至第一布线层170。
本发明实施例提供一种半导体封装，包括第一布线层、第一管芯、至少一第二管芯、至少一第三管芯、封装模塑体、贯穿介层孔、导电部件以及至少一第四管芯。第一管芯位于第一布线层之上且具有至少一导通孔。第一管芯包括至少一个传感器。第二管芯与第三管芯设置于第一布线层上且位于第一布线层与第一管芯之间。封装模塑体设置于第一布线层上且位于第一布线层与第一管芯之间，并且封装模塑体包覆第二管芯与第三管芯。穿透封装模塑体的贯穿介层孔位于第一布线层与第一管芯之间且位于所述至少一第二管芯与所述至少一第三管芯旁边。贯穿介层孔电性连接至第一管芯的至少一导通孔且电性连接至第一布线层。导电部件电性连接至第一布线层。第四管芯电性连接至第一布线层且设置于导电部件旁边。
在本发明一些实施例中，半导体封装更包括设置在封装模塑体上和介于封装模塑体、至少一第二管芯、至少一第三管芯和第一管芯之间的介电材料层，其中介电材料层暴露半导体封装的至少一导通孔和贯穿介层孔。在本发明一些实施例中，其中第一管芯的至少一导通孔与封装模塑体中的贯穿介层孔直接接触。在本发明一些实施例中，还包括设置在封装模塑体上介于第一管芯和至少一第二管芯和至少一第三管芯之间的第二布线层，其中至少一导通孔和贯穿介层孔连接至第二布线层，并且第一管芯是通过至少一导通孔电连接至第二布线层。在本发明一些实施例中，其中至少一个传感器包括至少一个指纹传感器、至少一个CMOS传感器或它们的组合。在本发明一些实施例中，第四管芯包括至少一个无源组件，连接器配置在第四管芯与第一布线层之间而电性连接第四管芯与第一布线层。
本发明实施例提供一种半导体封装，包括第一布线层、第一管芯、至少一第二管芯、至少一第三管芯、贯穿介层孔以及封装模塑体。第一管芯包括至少一个传感器和导通孔于其中，第一布线层设置在第一管芯之下。第二管芯与第三管芯设置在第一布线层上且位于第一布线层和第一管芯之间。贯穿介层孔设置在第一布线层上、位于第一布线层和第一管芯之间并且设置于至少一第二管芯与至少一第三管芯旁边。导通孔的位置与贯穿介层孔的位置实质上大致对齐。第一管芯的导通孔与贯穿介层孔电性连接，并且导通孔和贯穿介层孔电性连接至第一布线层。封装模塑体设置于第一布线层上且位于第一布线层和第一管芯之间，而且封装模塑体包覆密封至少一第二管芯、至少一第三管芯以及贯穿介层孔。
本发明实施例提供一种半导体封装的制造方法。提供具有第一管芯的芯片于载体上，其中第一管芯包括至少一个传感器和多个导通孔于其中。形成多个贯穿介层孔于第一管芯之上以及导通孔之上，其中导通孔的位置与贯穿介层孔的位置实质上大致对齐。第一管芯的导通孔与贯穿介层孔电性连接。设置至少一第二管芯与至少一第三管芯于第一管芯之上并且设置于贯穿介层孔旁边。形成封装模塑体于芯片的第一管芯之上并且封装模塑体包覆密封至少一第二管芯、至少一第三管芯以及贯穿介层孔。形成第一布线层于封装模塑体上。贯穿介层孔电性连接至第一布线层。设置至少一第四管芯于第一布线层上。第四管芯电性连接至第一布线层。设置导电部件在第一布线层上。从芯片移除载体并对芯片进行切割工艺而切割穿透至少芯片与封装模塑体，分离得到多个半导体封装。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (1)

1.一种半导体封装，包括：
第一布线层；
第一管芯，设置于所述第一布线层之上且具有至少一导通孔于其内，其中所述第一管芯包括至少一传感器；
至少一第二管芯与至少一第三管芯，设置于所述第一布线层上且位于所述第一布线层与所述第一管芯之间；
封装模塑体，设置于第一布线层上且位于第一布线层与第一管芯之间，而且所述封装模塑体包覆所述至少一第二管芯与所述至少一第三管芯；
多个贯穿介层孔，设置为穿透所述封装模塑体、位于所述至少一第二管芯与所述至少一第三管芯旁边并且位于所述第一布线层与所述第一管芯之间，其中所述多个贯穿介层孔电性连接至所述第一布线层以及所述第一管芯的所述至少一导通孔；
多个导电部件，电性连接至所述第一布线层；以及
至少一第四管芯，电性连接至所述第一布线层且设置于所述多个导电部件旁边。
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