CN107564823B - 一种用于制造半导体结构的方法 - Google Patents

一种用于制造半导体结构的方法 Download PDF

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CN107564823B
CN107564823B CN201710454238.5A CN201710454238A CN107564823B CN 107564823 B CN107564823 B CN 107564823B CN 201710454238 A CN201710454238 A CN 201710454238A CN 107564823 B CN107564823 B CN 107564823B
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semiconductor substrate
semiconductor structure
die
adhesive
sheet
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CN107564823A (zh
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陈衿良
游济阳
何冠霖
梁裕民
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明的一些实施例揭露一种用于制造半导体结构的方法。所述方法包含：提供上面具有多个裸片的半导体衬底；分注底胶材料及模塑料以填充在所述裸片之下与在所述裸片之间的空间；设置暂时载体在所述裸片上方；薄化所述半导体衬底的厚度；在所述经薄化半导体衬底上执行背侧金属化；移除所述暂时载体；以及附接板材在所述裸片上方。本发明的一些实施例也揭露一种相关的半导体结构。

Description

一种用于制造半导体结构的方法
技术领域
本发明的一些实施例揭露一种用于制造半导体结构的方法。
背景技术
在电子封装的领域中，在晶片上芯片(chip-on-wafer，CoW)组装之后需要成型过程及晶片薄化过程。一些因素，例如大小、芯片高度均匀性、芯片分布均匀性、硬度、刚性、热膨胀系数及模塑料与芯片的玻璃转移温度、晶片的翘曲及翘曲均匀性影响产品产率。
已发现在回焊过程期间，严重的翘曲容易发生于成型封装件，于是造成CoW与衬底之间的非接触或分离。因此，如何克服上述缺点变得关键。
发明内容
本发明的一些实施例揭露一种用于制造半导体结构的方法，其包括：提供上面具有多个裸片的半导体衬底；分注底胶材料及模塑料以填充在所述裸片之下与在所述裸片之间的空间；设置暂时载体在所述裸片上方；薄化所述半导体衬底的厚度；在所述经薄化半导体衬底上执行背侧金属化；移除所述暂时载体；以及附接板材在所述裸片上方。
附图说明
本揭露的方面将在与随附图式一同阅读下列详细说明下被最佳理解。请注意，根据业界标准作法，各种特征未依比例绘制。事实上，为了使讨论内容清楚，各种特征的尺寸可刻意放大或缩小。
图1到9是根据本揭露的示范性实施例在制造半导体结构中的中间阶段的剖面图。
具体实施方式
下列揭露提供许多用于实施所提供目标的不同特征的不同实施例、或实例。为了简化本揭露，于下描述组件及配置的具体实例。当然这些仅为实例而非意图为限制性。例如，在下面说明中，形成第一特征在第二特征上方或上可包含其中第一及第二特征形成为直接接触的实施例，以及也可包含其中额外特征可形成在第一与第二特征之间而使得第一及第二特征不可直接接触的实施例。此外，本揭露可在各种实例中重复参考编号及/或字母。此重复是为了简单与清楚的目的且其本身并不决定所讨论的各种实施例及/或构形之间的关系。
再者，空间相关词汇，例如“在…之下”、“下面”、“下”、“上面”、“上”和类似词汇，可为了使说明书便于描述如图式绘示的一个组件或特征与另一个(或多个)组件或特征的相对关系而使用于本文中。除了图式中所画的方位外，这些空间相对词汇也意图用来涵盖装置在使用中或操作时的不同方位。所述设备可以其它方式定向(旋转90度或处于其它方位)，据此在本文中所使用的这些空间相关说明符可以类似方式加以解释。
尽管用以阐述本揭露宽广范围的数值范围和参数是近似值，但是是尽可能精确地报告在具体实例中所提出的数值。然而，任何数值固有地含有某些必然从相应测试测量中发现的标准偏差所导致的误差。而且，如本文中所使用，词汇“约”一般意指在距给定值或范围的10％、5％、1％、或0.5％内。替代地，词汇“约”意指在本技术领域具有通常知识者所认知的平均值的可接受标准误差内。除操作/工作实例外，或除非有另行具体指明，否则在所有情况下，所有的数值范围、量、值、及百分比，例如本文中所揭露的用于材料数量、时间持续期间、温度、操作条件、量的比、及类似者的那些，应理解成以词汇“约”所修饰者。据此，除非有相反指示，否则本揭露及所附权利要求书中所提出的数值参数是可依所欲变化的近似值。最少，各数值参数应至少按照所报告的有效位数的数目且通过施加常规四舍五入技术而解释。本文中，范围可表示成从一个端点到另一个端点或在两个端点之间。除非有另行指明，否则本文揭露的所有范围包括端点。
现将描述根据本揭露的用于形成半导体结构100的示范性方法。图1到8绘示在依序的制造步骤期间半导体结构100的截面。在一个实施例中，半导体衬底可以是硅插置件，其可形成三维集成电路(three dimensional integrated circuit，3D IC)芯片封装件的部件。
参考图1，用于形成半导体结构的过程从提供具有多个芯片或裸片110已在先前安装于其上的半导体衬底120开始(也称作CoW或晶片上芯片)。据此，在一些实施例中，裸片110可视为顶部裸片。衬底120可以是插置件，其可由任何合适的材料形成，例如硅、玻璃-硅、或用于半导体技术领域的其它衬底材料，但不限于此。在一个实施例中，衬底120是硅插置件且所述插置件可以是硅晶片。在制造过程中的此时点，衬底120尚未变薄。在薄化之前，衬底120可具有大于约100微米的总厚度。然而，此不是本揭露的限制。在一些实施例中，衬底120可具有约25微米厚的总厚度。为简洁起见，请注意关于衬底120的细节可能被省略且未绘示在图1中。
参考图1，衬底120包含以面对裸片110的顶部(前)侧或表面121为界的上部122。衬底120进一步包含以相对底部(背)侧或表面123为界的下部124。上部122靠近裸片110且下部124远离裸片110。衬底120的上部122可包含前侧金属化，所述前侧金属化包含本技术领域已知的导电重布线层(redistribution layer，RDL)互连结构130，且上部122可包含各种经配置的导电垫、引线、通路及沟槽的组合，所述导电垫、引线、通路及沟槽用于形成导电地连接图1所显示的裸片110的群的电路且也形成垂直通过上部122的导电路径。在一些实施例中，衬底120可包含耦合到RDL互连结构130的贯穿硅通路(through silicon via，TSV)(为简洁起见，未显示在图1中)。
如图1所显示，裸片110是通过形成在裸片110与衬底120之间的多个微凸块134导电地耦合到衬底120。微凸块134可以是任何合适的导电材料制，包含铜或铜-锡。在一个示范性实施例中，但不限于此，微凸块134可以是焊料凸块，具有与3D IC芯片封装件架构一致的约20微米的直径及约50微米或较小的节距间隔。微凸块134可通过任何合适的过程连到衬底120的上部122，例如但不限于焊料回焊。
在一些实施例中，除了包含前侧RDL互连结构130之外，衬底120的上部122可进一步包含集成无源装置(integrated passive device，IPD)。IPD可包含组件例如电阻、电容器、谐振器、滤波器、或通常见于射频(radio frequency，RF)电路中的其它组件。
在一些实施例中，但不限于此，在衬底120的上部122中的RDL互连结构130可通过在本技术领域中通常用于形成互连件的后端过程(back-end-of-line，BEOL)程序形成，包含使用光刻(使用图案化光阻)、蚀刻及导电材料或金属沉积的组合及电镀操作的镶嵌或双镶嵌过程。在衬底120的上部122中的前侧RDL互连结构的形成先于安装裸片110在衬底上。
继续参照图1，在制造过程中在衬底薄化之前的此时点，衬底120的下部124可以是固体单石材料片，尚未有任何金属化，例如内部导电结构或贯穿硅通路(TSV)形成。
在图2中，半导体结构制造过程接着为底胶填充及包覆成型过程，其中底胶材料140及模塑料142被分注或注射以填充在裸片110之下且在相邻裸片之间的空隙空间(显示于图1中)。模塑料142接着被固化，例如通过施加热或紫外光(ultraviolet，UV)照射一段时间以硬化化合物。模塑料142可被稍稍地包覆成型而如所示般延伸在裸片110上面，以确保裸片110被完全囊封。模塑料142及底胶材料140保护并结构上支撑裸片110及微凸块134。可使用用于半导体制造的任何合适种类的商业上可购得环氧化物或聚合物系模塑料或囊封剂。
在示范性实施例中，可使用两步骤成型过程，其中底胶材料140是先注射在裸片110之下(即，在裸片与衬底120之间)，接着用第二模塑料包覆成型，以囊封并填充裸片之间的空间以便形成模塑料142。底胶材料可以是任何合适的液体环氧化物、可变形凝胶、硅橡胶、或用于底胶填充化合物的其它材料。
在图3中，在模塑料142被固化与硬化之后，半导体结构的制造接着为平坦化过程，其用于移除过多或过量模塑料142以如所示般暴露裸片110的顶部。平坦化可通过本技术领域所用的任何合适机械及/或化学机械手段执行，以移除过量模塑料142。在一些实施例中，模塑料142可通过化学机械平坦化(chemical mechanical planarization，CMP)、以砂轮研磨、或其它技术移除。此平坦化过程也可回返研磨裸片110中的一些，因为裸片110可能不是全部具有均匀的厚度或高度。所得的裸片110与模塑料142的顶部表面是意图为相对平坦，如图3所显示。
现参照图4A，接下来暂时载体150(在本技术领域中也称作“把手”)附接并接合到裸片110的顶部，以在进一步加工步骤期间，促进半导体结构100的处理并支撑衬底120。在一些实施例中，载体150可以是玻璃、氧化硅、氧化铝、或其它合适的材料制。在一个实施例中，载体150可以是玻璃。载体150可具备可释离粘着剂152，可释离粘着剂152用于在加工期间暂时接合载体150到CoW结构且接着促进从半导体结构容易移除载体150。可使用任何合适种类的商业上可购得可释离粘着剂。在一些实施例中，热介接材料(thermal interfacematerial，TIM)可用于暂时接合载体到CoW结构。
在图5A所显示的下一步骤中，现执行薄化操作以减少衬底120的厚度，在此非限制性实施例中，衬底120可以是硅。图4A的半导体结构可如所示般先被倒置，以供硅薄化步骤。
继续参照图5A，硅薄化操作可通过本技术领域所用的任何合适的机械或化学机械过程执行。在一些实施例中，薄化可通过使用具有滚动板或轮的研磨机的研磨执行，所述滚动板或轮具有黏附到轮的适当尺寸的研磨剂或砂粒。在一些实施例中，砂粒可以是钻石制。
在一个实施例中，可使用两阶段研磨过程以减少硅衬底120的厚度。使用大的粗砂材料，例如40到60微米大小研磨剂，可先在衬底120上执行第一粗研磨步骤。使用细砂材料，例如10到30微米大小研磨剂材料，后续可在衬底120上执行第二最终研磨步骤。第二最终研磨步骤产生相对平滑或经抛光且平坦底部表面123(倒置示于图5A中)。替代地，化学机械平面化(chemical mechanical planning，CMP)可视需要用于第二最终研磨步骤或额外于第二最终研磨步骤之后，以抛光衬底120的底部表面123。在薄化操作之后，硅衬底120的第二厚度小于图1中所示的第一厚度。在一些示范性实施例中，但不限于此，在薄化之后，衬底120可具有约0.8到1mm的厚度。衬底厚度的减少有利地允许形成较薄裸片封装件，其消耗较少垂直高度，进而为裸片封装件产生较小形状因子。
应注意衬底薄化操作从衬底120的下部124移除硅材料且不干扰或损害存在于上部122中的RDL互连结构130。在一个实施例中，执行薄化操作直到已形成在衬底120的上部122中的导电前侧RDL接触垫、通路、TSV或其它导电结构显露出或暴露出。在一些实施例中，衬底120的下部124可主要含有TSV(为简洁起见，未显示在图5A中)。TSV的上端可导电地耦合或连接到任何种类的下述者或下述者的组合：形成前侧金属化及RDL互连件130的部件且在衬底120的上部122中的导电接点，包含但不限于TSV到部份贯穿通路及/或TSV到导电垫或水平引线。
参照图6，接下来可执行背侧金属化以建构RDL互连件170，以此完成最终可安装在系统板例如印刷电路板(printed circuit board，PCB)上的C4(即，控制塌陷高度芯片连接)或“覆晶”裸片封装件。背侧金属化包含形成导电重布线层(RDL)互连件170，如本技术领域具有通常知识者通常已知者其可包含导电垫、引线、通路、沟槽及凸块的组合。此最终金属化阶段可包含先沉积第一介电钝化层171在半导体衬底120的底部表面123上。接下来钝化层171使用光刻图案化，且接着后续被蚀刻以产生暴露出TSV的端的开口，以允许背侧RDL金属化而制作电连接到TSV。第二介电层172可被沉积在钝化层171上。接下来背侧RDL互连件170形成在包含有在凸块下金属化(under bump metallization，UBM)垫173上的C4凸块阵列174的介电层172中。凸块174可以是通常用于C4凸块的任何合适材料制且可通过在本技术领域中已知用于制造覆晶互连的任何合适过程形成。在一些实施例中，凸块174可以是Cu制。凸块174可具有较宽于微凸块134且在一些实施例中在约150到200微米等级的节距间隔。
在如图6所显示般形成背侧RDL互连件170及C4凸块阵列174之后，暂时载体150是通过任何合适的方式从裸片110释离并移除，如图7所示。可使用合适的清洁过程将任何残留粘着剂从裸片110的顶部表面及填充在裸片之间的空隙空间的模塑料142的顶部表面移除。现参照图8，接下来板材160(在本技术领域中也称作“盖”)附接并接合到包含裸片110及模塑料142的CoW结构的顶部。一般来说，板材160具有大于CoW结构所具者的刚性以便减少CoW结构的翘曲。在一些实施例中，板材160可包含材料，例如金属。在一些实施例中，板材160可包含具有从约130到约118GPa模数的Cu。在一些实施例中，板材160可包含具有从约190到约203GPa模数的不锈钢。在一些实施例中，板材160可包含具有从约100到约175GPa模数的陶瓷材料。然而，此不是本揭露的限制。在一些实施例中，板材160可具有约0.5mm到约2mm的厚度。
请注意，板材160可作为散热器使用，以置换传统在晶片上执行裸片切锯之后形成的盖。板材160可具备均匀施加的粘着剂162，粘着剂162用于接合板材160到CoW结构。可使用任何合适种类的商业上可购得粘着剂。在一些实施例中，TIM可用于接合载体到半导体裸片结构。在一些实施例中，粘着剂162可具有约50微米到约150微米的厚度。
在图9所显示的下一步骤中，图8的CoW结构与所附接的板材160被切锯并安装在衬底182例如电路板上。底胶材料180是分注到在经切锯CoW结构与衬底182之间的间隙中。由于在切锯之前板材160被接合到CoW结构，板材160及粘着剂162的边缘能够与CoW结构的边缘齐平而没有挤出。在示范性实施例中，底胶材料180可覆盖板材160的至少一部分。然而，此不是本揭露的限制。在示范性实施例中，底胶材料180可最多覆盖到粘着剂162或CoW结构。
在另一示范性实施例中，将附接板材的过程移动到较早的阶段。尤其，板材是采用来置换在图4A过程期间的暂时载体150。如图4B所显示，板材160是通过粘着剂162附接并接合到裸片110的顶部，以在进一步制造步骤期间支撑衬底120并减轻CoW结构的翘曲。在图5B所显示的下一步骤中，执行薄化操作以减少衬底120的厚度，在此非限制性实施例中，衬底120可以是硅。之后，可执行背侧金属化以此完成C4或“覆晶”裸片封装件及如图8到9所显示的后操作系统(post operating system，post-OS)操作。
本揭露的一些实施例提供一种用于制造半导体结构的方法，其包含：提供上面具有多个裸片的半导体衬底；分注底胶材料及模塑料以填充在所述裸片之下与在所述裸片之间的空间；设置暂时载体在所述裸片上方；薄化所述半导体衬底的厚度；在所述经薄化半导体衬底上执行背侧金属化；移除所述暂时载体；以及附接板材在所述裸片上方。
前面列述了数个实施例的特征以便本技术领域具有通常知识者可更佳地理解本揭露的方面。本技术领域具有通常知识者应了解他们可轻易地使用本揭露作为用以设计或修改其它操作及结构的基础以实现本文中所介绍实施例的相同目的及/或达成本文中所介绍实施例的相同优点。本技术领域具有通常知识者也应体认到这些均等构造不会悖离本揭露的精神及范围，以及它们可在不悖离本揭露的精神及范围下做出各种改变、取代、或替代。
再者，不意图将本申请案的范围限制于说明书中所描述的过程、机器、制造、物质的组成物、手段、方法、及步骤的具体实施例。从本发明实施例的揭露，本技术领域中具有通常知识者将轻易地了解到，可根据本揭露利用目前存在或待于日后开发出的实施如本文中所述的相应实施例实质上相同功能或达成如本文中所述的相应实施例实质上相同结果的过程、机器、制造、物质的组成物、手段、方法、或步骤。据此，随附的权利要求书是意图在它们的范围中包含这些过程、机器、制造、物质的组成物、手段、方法、或步骤。
符号说明
100 半导体结构
110 裸片
120 衬底
121 表面
122 上部
123 表面
124 下部
130 RDL互连结构
134 微凸块
140 底胶材料
142 模塑料
150 暂时载体
152 可释离粘着剂
160 板材
162 粘着剂
170 RDL互连件
171 钝化层
172 介电层
173 垫
174 凸块
180 底胶材料
182 衬底。

Claims (58)

1.一种用于制造半导体结构的方法，其包括：
提供上面具有多个裸片的半导体衬底；
分注第一底胶材料及模塑料以填充在所述裸片之下与在所述裸片之间的空间；
将暂时载体设置在所述裸片上方；
薄化所述半导体衬底的厚度；
在所述经薄化半导体衬底上执行背侧金属化；
移除所述暂时载体后将板材通过粘着剂附接在所述裸片上方；
锯割所述半导体衬底及所述板材以获得单粒化半导体结构；
将所述单粒化半导体结构安装在载体上；及
在所述单粒化半导体结构与所述载体之间分注第二底胶材料，所述第二底胶材料覆盖所述粘着剂与所述板材的至少一部分。
2.根据权利要求1所述的方法，其进一步包括薄化所述模塑料以暴露所述裸片。
3.根据权利要求1所述的方法，其中所述将所述板材附接在所述裸片上方包括将金属板材附接在所述裸片上方。
4.根据权利要求3所述的方法，其中所述将所述金属板材附接在所述裸片上方包括将Cu板材附接在所述裸片上方。
5.根据权利要求3所述的方法，其中所述将所述金属板材附接在所述裸片上方包括将不锈钢板材附接在所述裸片上方。
6.根据权利要求1所述的方法，其中所述将所述板材附接在所述裸片上方包括将陶瓷板材附接在所述裸片上方。
7.根据权利要求1所述的方法，其中所述将所述板材附接在所述裸片上方包括通过使用热界面材料TIM将所述板材附接在所述裸片上方。
8.一种用于制造半导体结构的方法，其包括：
提供上面具有多个裸片的半导体衬底；
分注第一底胶材料及模塑料以填充在所述裸片之下与在所述裸片之间的空间；
施加粘着剂于板材上；
在分注所述第一底胶材料及所述模塑料之后将板材附接在所述裸片上方；
在附接所述板材之后薄化所述半导体衬底的厚度；
在薄化所述半导体衬底之后在所述经薄化半导体衬底上执行背侧金属化；
锯割包含所述板材的所述半导体衬底；及
形成第二底胶材料覆盖所述粘着剂与所述板材的至少一部分。
9.根据权利要求8所述的方法，其进一步包括薄化所述模塑料以暴露所述裸片。
10.根据权利要求8所述的方法，其中所述将所述板材附接在所述裸片上方包括将金属板材附接在所述裸片上方。
11.根据权利要求10所述的方法，其中所述将所述金属板材附接在所述裸片上方包括将Cu板材附接在所述裸片上方。
12.根据权利要求10所述的方法，其中所述将所述金属板材附接在所述裸片上方包括将不锈钢板材附接在所述裸片上方。
13.根据权利要求8所述的方法，其中所述将所述板材附接在所述裸片上方包括将陶瓷板材附接在所述裸片上方。
14.根据权利要求8所述的方法，其中所述将所述板材附接在所述裸片上方包括通过使用热界面材料TIM将所述板材附接在所述裸片上方。
15.根据权利要求8所述的方法，其进一步包括将所述经锯割半导体衬底安装在另一半导体衬底上。
16.一种用于制造半导体结构的方法，其包括：
提供其前侧处具有互连结构的半导体衬底；
提供具有导电凸块的裸片；
将所述裸片设置在所述半导体衬底上方以将所述导电凸块耦合到所述互连结构；
将第一载体设置在所述裸片上方；
在所述半导体衬底的背侧上执行金属化；
移除所述第一载体后将板材通过粘着剂附接在所述裸片上方；
锯割所述半导体衬底及所述板材以获得单粒化半导体结构；
将所述单粒化半导体结构安装在第二载体上；及
在所述单粒化半导体结构与所述第二载体之间分注底胶材料，所述底胶材料覆盖所述粘着剂与所述板材的至少一部分。
17.根据权利要求16所述的方法，其中所述将所述板材附接在所述裸片上方包括通过使用热界面材料TIM将所述板材附接在所述裸片上方。
18.根据权利要求16所述的方法，其进一步包括：
在于所述半导体衬底的所述背侧上执行所述金属化之前薄化所述半导体衬底的厚度。
19.一种半导体结构，其包括：
半导体衬底，其具有前侧及与所述前侧相对的背侧；
多个裸片，其在所述半导体衬底的所述前侧上；
板材，其附接在所述多个裸片上方，其中所述多个裸片在所述板材与所述半导体衬底之间；
粘着剂，其用于接合所述板材与所述多个裸片，其中所述粘着剂的边缘与所述板材的边缘齐平；及
第一底胶材料，其覆盖所述粘着剂的边缘与所述板材的边缘。
20.根据权利要求19所述的半导体结构，其进一步包括填充所述多个裸片与所述半导体衬底之间的空间的第二底胶材料。
21.根据权利要求20所述的半导体结构，其进一步包括在所述半导体衬底的所述背侧上的金属化层。
22.根据权利要求21所述的半导体结构，其进一步包括填充所述金属化层与所述粘着剂之间的空间的模塑料。
23.根据权利要求22所述的半导体结构，其中所述粘着剂的所述边缘与所述模塑料的边缘齐平。
24.根据权利要求19所述的半导体结构，其中所述板材包含Cu板材。
25.根据权利要求19所述的半导体结构，其中所述板材包含不锈钢板材。
26.根据权利要求19所述的半导体结构，其中所述板材包含陶瓷板材。
27.根据权利要求19所述的半导体结构，其中所述粘着剂具有50微米到150微米的厚度。
28.一种半导体结构，其包括：
第一半导体衬底，其具有前侧及与所述前侧相对的背侧；
多个裸片，其在所述第一半导体衬底的所述前侧上；
板材，其附接在所述多个裸片上方，其中所述多个裸片在所述板材与所述第一半导体衬底之间；
粘着剂，其用于接合所述板材与所述多个裸片；
模塑料，其填充所述第一半导体衬底与所述板材之间的空间，其中所述板材的边缘与所述模塑料的边缘齐平；
第二半导体衬底，其中所述第一半导体衬底的所述背侧接合到所述第二半导体衬底；及
底胶材料，其覆盖所述模塑料的边缘、所述粘着剂的边缘与所述板材的边缘。
29.根据权利要求28所述的半导体结构，其进一步包括用于将所述板材附接到所述多个裸片及所述模塑料的粘着剂。
30.根据权利要求28所述的半导体结构，其中所述板材包含金属。
31.根据权利要求30所述的半导体结构，其中所述板材包含Cu。
32.根据权利要求30所述的半导体结构，其中所述板材包含不锈钢。
33.根据权利要求28所述的半导体结构，其中所述板材包含陶瓷。
34.根据权利要求29所述的半导体结构，其中所述粘着剂包含热界面材料TIM。
35.一种半导体结构，其包括：
晶片上覆芯片CoW组合件，其包含半导体衬底及在所述半导体衬底上的多个裸片；
板材，其附接在所述CoW组合件的第一侧上方；
粘着剂，其用于接合所述板材与所述CoW组合件，其中所述粘着剂的边缘与所述CoW组合件的边缘齐平；
另一半导体衬底，其接合到所述CoW组合件的第二侧；及
底胶材料，其设置于所述CoW组合件与所述另一半导体衬底之间且覆盖所述粘着剂的边缘与所述板材的边缘。
36.根据权利要求35所述的半导体结构，其中所述板材包含金属。
37.根据权利要求35所述的半导体结构，其中所述板材包含陶瓷。
38.根据权利要求35所述的半导体结构，其中所述底胶材料进一步覆盖所述板材的至少一部分。
39.一种半导体结构，其包括：
半导体衬底，其具有前侧及与所述前侧相对的背侧；
多个裸片，其在所述半导体衬底的所述前侧上；
板材，其附接在所述多个裸片上方，其中所述多个裸片在所述板材与所述半导体衬底之间；
粘着剂，其用于接合所述板材与所述多个裸片；及
底胶材料，其覆盖所述粘着剂与所述板材的侧壁的至少一部分。
40.根据权利要求39所述的半导体结构，其中所述板材的边缘与所述半导体衬底的边缘齐平。
41.根据权利要求40所述的半导体结构，其进一步包括在所述半导体衬底的所述背侧上的金属化层。
42.根据权利要求41所述的半导体结构，其进一步包括填充所述金属化层与所述粘着剂之间的空间的模塑料。
43.根据权利要求42所述的半导体结构，其中所述粘着剂的边缘与所述模塑料的边缘齐平。
44.根据权利要求39所述的半导体结构，其中所述板材包含具有从118到130GPa的模数的Cu板材。
45.根据权利要求39所述的半导体结构，其中所述板材包含具有从190到203GPa的模数的不锈钢板材。
46.根据权利要求39所述的半导体结构，其中所述板材包含具有从100到175GPa的模数的陶瓷板材。
47.根据权利要求39所述的半导体结构，其中所述粘着剂具有50微米到150微米的厚度。
48.一种半导体结构，其包括：
第一半导体衬底，其具有前侧及与所述前侧相对的背侧；
多个裸片，其在所述第一半导体衬底的所述前侧上；
板材，其附接在所述多个裸片上方，其中所述多个裸片在所述板材与所述第一半导体衬底之间；
粘着剂，其用于接合所述板材与所述多个裸片；
模塑料，其填充所述第一半导体衬底与所述板材之间的空间；
第二半导体衬底，其中所述第一半导体衬底的所述背侧接合到所述第二半导体衬底；及
底胶材料，其填充所述第一半导体衬底与所述第二半导体衬底之间的空间，并且覆盖所述粘着剂与所述板材的至少一部分。
49.根据权利要求48所述的半导体结构，其进一步包括用于将所述板材附接到所述多个裸片及所述模塑料的粘着剂。
50.根据权利要求48所述的半导体结构，其中所述板材包含金属。
51.根据权利要求50所述的半导体结构，其中所述板材包含具有从118到130GPa的模数的Cu。
52.根据权利要求50所述的半导体结构，其中所述板材包含具有从190到203GPa的模数的不锈钢。
53.根据权利要求48所述的半导体结构，其中所述板材包含具有从100到175GPa的模数的陶瓷。
54.根据权利要求49所述的半导体结构，其中所述粘着剂包含热界面材料TIM。
55.一种半导体结构，其包括：
晶片上覆芯片CoW组合件，其包含半导体衬底及在所述半导体衬底上的多个裸片；
板材，其附接在所述CoW组合件的第一侧上方，所述板材包含金属及陶瓷中的至少一个；
粘着剂，其用于接合所述板材与所述CoW组合件；
另一半导体衬底，其接合到所述CoW组合件的第二侧；及
底胶材料，其设置于所述CoW组合件与所述另一半导体衬底之间且覆盖所述粘着剂与所述板材的至少一部分。
56.根据权利要求55所述的半导体结构，其中所述板材包含Cu。
57.根据权利要求55所述的半导体结构，其中所述板材包含不锈钢。
58.根据权利要求55所述的半导体结构，其中所述板材的边缘与所述CoW组合件的边缘齐平。
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Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10600748B2 (en) * 2016-06-20 2020-03-24 Samsung Electronics Co., Ltd. Fan-out semiconductor package
US10553548B2 (en) * 2017-06-28 2020-02-04 Intel Corporation Methods of forming multi-chip package structures
US10515889B2 (en) * 2017-10-13 2019-12-24 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
US10504824B1 (en) 2018-09-21 2019-12-10 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11024616B2 (en) * 2019-05-16 2021-06-01 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
WO2021016547A1 (en) * 2019-07-25 2021-01-28 Samtec, Inc. Wirebondable interposer for flip chip packaged integrated circuit die
US11948855B1 (en) 2019-09-27 2024-04-02 Rockwell Collins, Inc. Integrated circuit (IC) package with cantilever multi-chip module (MCM) heat spreader
TWI756094B (zh) * 2021-03-31 2022-02-21 力成科技股份有限公司 封裝結構及其製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102623441A (zh) * 2011-01-28 2012-08-01 三星电子株式会社 半导体装置及其制造方法
US20130210198A1 (en) * 2012-02-10 2013-08-15 Taiwan Semiconductor Manufacturing Co., Ltd. Process for forming semiconductor structure
US20130217188A1 (en) * 2012-02-16 2013-08-22 Taiwan Semiconductor Manufacturing Company, Ltd. Structures and Formation Methods of Packages with Heat Sinks

Family Cites Families (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5891753A (en) * 1997-01-24 1999-04-06 Micron Technology, Inc. Method and apparatus for packaging flip chip bare die on printed circuit boards
US6104093A (en) * 1997-04-24 2000-08-15 International Business Machines Corporation Thermally enhanced and mechanically balanced flip chip package and method of forming
US6784541B2 (en) * 2000-01-27 2004-08-31 Hitachi, Ltd. Semiconductor module and mounting method for same
US6541847B1 (en) * 2002-02-04 2003-04-01 International Business Machines Corporation Packaging for multi-processor shared-memory system
US7129422B2 (en) * 2003-06-19 2006-10-31 Wavezero, Inc. EMI absorbing shielding for a printed circuit board
US7271479B2 (en) * 2004-11-03 2007-09-18 Broadcom Corporation Flip chip package including a non-planar heat spreader and method of making the same
JP4553765B2 (ja) * 2005-03-25 2010-09-29 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法
JP2007103772A (ja) 2005-10-06 2007-04-19 Texas Instr Japan Ltd 半導体装置の製造方法
US7605477B2 (en) * 2007-01-25 2009-10-20 Raytheon Company Stacked integrated circuit assembly
US7564115B2 (en) 2007-05-16 2009-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Tapered through-silicon via structure
US7973413B2 (en) 2007-08-24 2011-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate via for semiconductor device
US8227902B2 (en) 2007-11-26 2012-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Structures for preventing cross-talk between through-silicon vias and integrated circuits
US7843064B2 (en) 2007-12-21 2010-11-30 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and process for the formation of TSVs
US8278152B2 (en) 2008-09-08 2012-10-02 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding process for CMOS image sensor
US7825024B2 (en) 2008-11-25 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming through-silicon vias
US8158456B2 (en) 2008-12-05 2012-04-17 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming stacked dies
US9875911B2 (en) * 2009-09-23 2018-01-23 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming interposer with opening to contain semiconductor die
US8143097B2 (en) * 2009-09-23 2012-03-27 Stats Chippac, Ltd. Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP
EP2339627A1 (en) * 2009-12-24 2011-06-29 Imec Window interposed die packaging
US7999371B1 (en) * 2010-02-09 2011-08-16 Amkor Technology, Inc. Heat spreader package and method
US8183578B2 (en) 2010-03-02 2012-05-22 Taiwan Semiconductor Manufacturing Company, Ltd. Double flip-chip LED package components
US8183579B2 (en) 2010-03-02 2012-05-22 Taiwan Semiconductor Manufacturing Company, Ltd. LED flip-chip package structure with dummy bumps
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US8426961B2 (en) 2010-06-25 2013-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded 3D interposer structure
US8581418B2 (en) 2010-07-21 2013-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-die stacking using bumps with different sizes
US8105875B1 (en) 2010-10-14 2012-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Approach for bonding dies onto interposers
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
US8803316B2 (en) 2011-12-06 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. TSV structures and methods for forming the same
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US9257333B2 (en) 2013-03-11 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures and methods of forming same
US9263839B2 (en) 2012-12-28 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for an improved fine pitch joint
US9111949B2 (en) 2012-04-09 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of wafer level package for heterogeneous integration technology
US9034695B2 (en) * 2012-04-11 2015-05-19 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated thermal solutions for packaging integrated circuits
US8803292B2 (en) 2012-04-27 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate vias and methods for forming the same
US20130307153A1 (en) 2012-05-18 2013-11-21 International Business Machines Corporation Interconnect with titanium-oxide diffusion barrier
US9196532B2 (en) 2012-06-21 2015-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit packages and methods for forming the same
US9443783B2 (en) 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
US9275924B2 (en) 2012-08-14 2016-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package having a recess filled with a molding compound
US9299649B2 (en) 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US8802504B1 (en) 2013-03-14 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9287194B2 (en) * 2013-03-06 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging devices and methods for semiconductor devices
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US9196559B2 (en) 2013-03-08 2015-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Directly sawing wafers covered with liquid molding compound
US8993380B2 (en) 2013-03-08 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package
US8987922B2 (en) 2013-03-11 2015-03-24 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for wafer level packaging
US9275925B2 (en) 2013-03-12 2016-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for an improved interconnect structure
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
JP2015056563A (ja) * 2013-09-12 2015-03-23 株式会社東芝 半導体装置およびその製造方法
US9530730B2 (en) * 2013-11-08 2016-12-27 Taiwan Semiconductor Manufacturing Company, Ltd. Configurable routing for packaging applications
US9209048B2 (en) * 2013-12-30 2015-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Two step molding grinding for packaging applications
US20150287697A1 (en) 2014-04-02 2015-10-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device and Method
US9401287B2 (en) * 2014-02-07 2016-07-26 Altera Corporation Methods for packaging integrated circuits
KR20150094135A (ko) * 2014-02-10 2015-08-19 삼성전자주식회사 반도체 패키지 및 이의 제조방법
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9425126B2 (en) 2014-05-29 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy structure for chip-on-wafer-on-substrate
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
US9899285B2 (en) * 2015-07-30 2018-02-20 Semtech Corporation Semiconductor device and method of forming small Z semiconductor package
US9704825B2 (en) * 2015-09-30 2017-07-11 Taiwan Semiconductor Manufacturing Company, Ltd. Chip packages and methods of manufacture thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102623441A (zh) * 2011-01-28 2012-08-01 三星电子株式会社 半导体装置及其制造方法
US20130210198A1 (en) * 2012-02-10 2013-08-15 Taiwan Semiconductor Manufacturing Co., Ltd. Process for forming semiconductor structure
US20130217188A1 (en) * 2012-02-16 2013-08-22 Taiwan Semiconductor Manufacturing Company, Ltd. Structures and Formation Methods of Packages with Heat Sinks

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