CN107564823B - Method for manufacturing semiconductor structure - Google Patents

Method for manufacturing semiconductor structure Download PDF

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Publication number
CN107564823B
CN107564823B CN201710454238.5A CN201710454238A CN107564823B CN 107564823 B CN107564823 B CN 107564823B CN 201710454238 A CN201710454238 A CN 201710454238A CN 107564823 B CN107564823 B CN 107564823B
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Prior art keywords
semiconductor substrate
semiconductor structure
die
adhesive
sheet
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CN201710454238.5A
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CN107564823A (en
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陈衿良
游济阳
何冠霖
梁裕民
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Abstract

Some embodiments of the present invention disclose a method for fabricating a semiconductor structure. The method comprises the following steps: providing a semiconductor substrate having a plurality of dies thereon; dispensing an underfill material and a molding compound to fill spaces under and between the dies; disposing a temporary carrier over the die; thinning the thickness of the semiconductor substrate; performing backside metallization on the thinned semiconductor substrate; removing the temporary carrier; and an attachment plate over the die. Some embodiments of the present invention also disclose a related semiconductor structure.

Description

Method for manufacturing semiconductor structure
Technical Field
Some embodiments of the present invention disclose a method for fabricating a semiconductor structure.
Background
In the field of electronic packaging, a molding process and a wafer thinning process are required after chip-on-wafer (CoW) assembly. Factors such as size, uniformity of die height, uniformity of die distribution, hardness, rigidity, coefficient of thermal expansion and glass transition temperature of molding compound and die, warpage of wafer and uniformity of warpage affect product yield.
It has been found that severe warpage easily occurs in the molded package during the reflow process, thus causing non-contact or separation between the CoW and the substrate. Therefore, how to overcome the above disadvantages becomes critical.
Disclosure of Invention
Some embodiments of the present invention disclose a method for fabricating a semiconductor structure, comprising: providing a semiconductor substrate having a plurality of dies thereon; dispensing an underfill material and a molding compound to fill spaces under and between the dies; disposing a temporary carrier over the die; thinning the thickness of the semiconductor substrate; performing backside metallization on the thinned semiconductor substrate; removing the temporary carrier; and an attachment plate over the die.
Drawings
Aspects of the present disclosure will be best understood from the following detailed description when read with the accompanying drawings. It is noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be exaggerated or minimized intentionally for clarity of discussion.
Fig. 1 through 9 are cross-sectional views of intermediate stages in the fabrication of a semiconductor structure according to exemplary embodiments of the present disclosure.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided objects. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Furthermore, spatially relative terms, such as "below" …, "below," "lower," "above," "upper," and the like, may be used herein for ease of description to describe one element or feature's relative to another element (or features) as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted in a similar manner.
Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the disclosure are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in their respective testing measurements. Also, as used herein, the word "about" generally means within 10%, 5%, 1%, or 0.5% from a given value or range. Alternatively, the word "about" means within an acceptable standard error of the mean as recognized by one of ordinary skill in the art. Except in the operating/working examples, or where otherwise specifically indicated, all numerical ranges, amounts, values, and percentages, such as those disclosed herein for amounts of material, durations of time, temperatures, operating conditions, ratios of amounts, and the like, are to be understood as modified by the word "about". Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present disclosure and attached claims are approximations that may vary depending upon the desired properties. At the very least, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Ranges may be expressed herein as from one end point to another end point or between two end points. Unless otherwise indicated, all ranges disclosed herein are inclusive of the endpoints.
An exemplary method for forming the semiconductor structure 100 in accordance with the present disclosure will now be described. Fig. 1-8 illustrate cross-sections of a semiconductor structure 100 during sequential fabrication steps. In one embodiment, the semiconductor substrate may be a silicon interposer, which may form part of a three-dimensional integrated circuit (3D IC) chip package.
Referring to fig. 1, a process for forming a semiconductor structure begins with providing a semiconductor substrate 120 (also referred to as CoW or chip-on-wafer) having a plurality of chips or dies 110 already previously mounted thereon. Accordingly, in some embodiments, die 110 may be considered a top die. Substrate 120 may be an interposer, which may be formed of any suitable material, such as, but not limited to, silicon, glass-silicon, or other substrate materials used in the semiconductor arts. In one embodiment, the substrate 120 is a silicon interposer and the interposer may be a silicon wafer. At this point in the manufacturing process, the substrate 120 has not yet been thinned. Prior to thinning, the substrate 120 may have a total thickness greater than about 100 microns. However, this is not a limitation of the present disclosure. In some embodiments, substrate 120 may have a total thickness of about 25 microns thick. For the sake of brevity, it is noted that details regarding the substrate 120 may be omitted and are not shown in fig. 1.
Referring to fig. 1, substrate 120 includes an upper portion 122 bounded by a top (front) side or surface 121 facing die 110. The substrate 120 further includes a lower portion 124 bounded by an opposing bottom (back) side or surface 123. The upper portion 122 is proximate to the die 110 and the lower portion 124 is distal to the die 110. The upper portion 122 of the substrate 120 may include front-side metallization including a conductive redistribution layer (RDL) interconnect structure 130 as known in the art, and the upper portion 122 may include a combination of various configured conductive pads, leads, vias, and trenches for forming circuits that conductively connect the groups of dies 110 shown in fig. 1 and also form conductive paths that pass vertically through the upper portion 122. In some embodiments, the substrate 120 may include Through Silicon Vias (TSVs) coupled to the RDL interconnect structure 130 (not shown in fig. 1 for simplicity).
As shown in fig. 1, die 110 is conductively coupled to substrate 120 by a plurality of microbumps 134 formed between die 110 and substrate 120. The microbumps 134 may be made of any suitable conductive material, including copper or copper-tin. In one exemplary embodiment, but not limited thereto, the microbumps 134 may be solder bumps having a diameter of about 20 microns and a pitch spacing of about 50 microns or less consistent with a 3D IC chip package architecture. The microbumps 134 may be attached to the upper portion 122 of the substrate 120 by any suitable process, such as, but not limited to, solder reflow.
In some embodiments, the upper portion 122 of the substrate 120 may further include an Integrated Passive Device (IPD) in addition to the front-side RDL interconnect structure 130. The IPD may include components such as resistors, capacitors, resonators, filters, or other components commonly found in Radio Frequency (RF) circuits.
In some embodiments, but not limited thereto, the RDL interconnect structure 130 in the upper portion 122 of the substrate 120 may be formed by back-end-of-line (BEOL) procedures commonly used in the art for forming interconnects, including damascene or dual damascene processes using a combination of photolithography (using patterned photoresist), etching, and conductive material or metal deposition, and electroplating operations. The front-side RDL interconnect structure in the upper portion 122 of the substrate 120 is formed prior to mounting the die 110 on the substrate.
With continued reference to fig. 1, at this point in the fabrication process prior to thinning of the substrate, the lower portion 124 of the substrate 120 may be a solid single piece of stone material, without any metallization, such as internal conductive structures or Through Silicon Vias (TSVs) being formed.
In fig. 2, the semiconductor structure fabrication process is followed by an underfill filling and overmolding process, where an underfill material 140 and a molding compound 142 are dispensed or injected to fill void spaces under the die 110 and between adjacent dies (shown in fig. 1). The molding compound 142 is then cured, such as by applying heat or Ultraviolet (UV) light for a period of time to harden the compound. The molding compound 142 may be slightly overmolded to extend over the die 110 as shown to ensure that the die 110 is fully encapsulated. The molding compound 142 and the underfill material 140 protect and structurally support the die 110 and the microbumps 134. Any suitable type of commercially available epoxy or polymer based molding compound or encapsulant for semiconductor fabrication may be used.
In an exemplary embodiment, a two-step molding process may be used in which the underfill material 140 is first injected under the die 110 (i.e., between the die and the substrate 120) and then overmolded with a second molding compound to encapsulate and fill the space between the dies so as to form the molding compound 142. The underfill material may be any suitable liquid epoxy, deformable gel, silicone rubber, or other material for the underfill compound.
In fig. 3, after the molding compound 142 is cured and hardened, the fabrication of the semiconductor structure is followed by a planarization process for removing excess or excess molding compound 142 to expose the top of the die 110 as shown. Planarization may be performed by any suitable mechanical and/or chemical mechanical means used in the art to remove excess molding compound 142. In some embodiments, the molding compound 142 may be removed by Chemical Mechanical Planarization (CMP), by grinding, or other techniques. This planarization process may also return to grinding some of the dies 110, as the dies 110 may not all have a uniform thickness or height. The top surface of the resulting die 110 and molding compound 142 is intended to be relatively flat, as shown in fig. 3.
Referring now to fig. 4A, a temporary carrier 150 (also referred to in the art as a "handle") is next attached and bonded to the top of the die 110 to facilitate handling of the semiconductor structure 100 and support of the substrate 120 during further processing steps. In some embodiments, the carrier 150 may be glass, silica, alumina, or other suitable material. In one embodiment, the carrier 150 may be glass. The carrier 150 may be provided with a releasable adhesive 152, the releasable adhesive 152 being used to temporarily bond the carrier 150 to the CoW structure during processing and then facilitate easy removal of the carrier 150 from the semiconductor structure. Any suitable type of commercially available releasable adhesive may be used. In some embodiments, a Thermal Interface Material (TIM) may be used to temporarily bond the carrier to the CoW structure.
In the next step shown in fig. 5A, a thinning operation is now performed to reduce the thickness of substrate 120, which in this non-limiting embodiment, substrate 120 may be silicon. The semiconductor structure of fig. 4A may be inverted as shown for the silicon thinning step.
With continued reference to fig. 5A, the silicon thinning operation may be performed by any suitable mechanical or chemical-mechanical process used in the art. In some embodiments, thinning may be performed by grinding using a grinder having a rolling plate or wheel with appropriately sized abrasives or grit adhered to the wheel. In some embodiments, the grit may be diamond.
In one embodiment, a two-stage grinding process may be used to reduce the thickness of the silicon substrate 120. A first rough grinding step may be performed on substrate 120 using a large grit material, such as a 40 to 60 micron size abrasive. A second final grinding step may be subsequently performed on the substrate 120 using a fine grit material, such as a 10 to 30 micron size abrasive material. The second final grinding step produces a relatively smooth or polished and flat bottom surface 123 (shown inverted in fig. 5A). Alternatively, Chemical Mechanical Planarization (CMP) may be used for the second final grinding step or in addition to the second final grinding step to polish the bottom surface 123 of the substrate 120. After the thinning operation, the second thickness of the silicon substrate 120 is less than the first thickness shown in fig. 1. In some exemplary embodiments, but not limited thereto, the substrate 120 may have a thickness of about 0.8 to 1mm after thinning. The reduction in substrate thickness advantageously allows for the formation of thinner die packages that consume less vertical height, thereby resulting in a smaller form factor for the die package.
It should be noted that the substrate thinning operation removes silicon material from the lower portion 124 of the substrate 120 and does not interfere with or damage the RDL interconnect structure 130 present in the upper portion 122. In one embodiment, the thinning operation is performed until a conductive frontside RDL contact pad, via, TSV, or other conductive structure that has been formed in the upper portion 122 of the substrate 120 is revealed or exposed. In some embodiments, the lower portion 124 of the substrate 120 may contain primarily TSVs (not shown in fig. 5A for simplicity). The upper end of the TSV may be conductively coupled or connected to any kind or combination of the following: conductive contacts, including but not limited to TSV to partial through vias and/or TSVs to conductive pads or horizontal leads, that form part of the front-side metallization and RDL interconnects 130 and in the upper portion 122 of the substrate 120.
Referring to fig. 6, backside metallization may then be performed to construct RDL interconnects 170, thereby completing a C4 (i.e., controlled collapse height chip connection) or "flip chip" die package that may ultimately be mounted on a system board, such as a Printed Circuit Board (PCB). Backside metallization includes the formation of conductive redistribution layer (RDL) interconnects 170, which may include a combination of conductive pads, leads, vias, trenches, and bumps as is generally known to those of ordinary skill in the art. This final metallization stage may include first depositing a first dielectric passivation layer 171 on the bottom surface 123 of the semiconductor substrate 120. The passivation layer 171 is next patterned using photolithography and then subsequently etched to create an opening that exposes the ends of the TSV to allow backside RDL metallization to be made electrically connected to the TSV. A second dielectric layer 172 may be deposited on the passivation layer 171. The backside RDL interconnects 170 are then formed in a dielectric layer 172 that includes an array of C4 bumps 174 on Under Bump Metallization (UBM) pads 173. The bumps 174 may be of any suitable material commonly used for C4 bumps and may be formed by any suitable process known in the art for fabricating flip-chip interconnects. In some embodiments, the bump 174 may be made of Cu. Bumps 174 may have a pitch spacing that is wider than micro-bumps 134, and in some embodiments on the order of about 150 to 200 microns.
After the backside RDL interconnects 170 and the array of C4 bumps 174 are formed as shown in fig. 6, the temporary carrier 150 is released and removed from the die 110 by any suitable means, as shown in fig. 7. Any residual adhesive may be removed from the top surfaces of the dies 110 and the top surface of the molding compound 142 that fills the void spaces between the dies using a suitable cleaning process. Referring now to fig. 8, next a plate 160 (also referred to in the art as a "lid") is attached and bonded to the top of the CoW structure including the die 110 and the molding compound 142. Generally, the sheet 160 has a rigidity greater than that of the CoW structure in order to reduce warpage of the CoW structure. In some embodiments, sheet 160 may comprise a material, such as a metal. In some embodiments, the sheet 160 may comprise Cu having a modulus of from about 130 to about 118 GPa. In some embodiments, sheet 160 may comprise stainless steel having a modulus of from about 190 to about 203 GPa. In some embodiments, sheet 160 may comprise a ceramic material having a modulus of from about 100 to about 175 GPa. However, this is not a limitation of the present disclosure. In some embodiments, sheet 160 may have a thickness of about 0.5mm to about 2 mm.
Note that sheet 160 may be used as a heat spreader to replace the cap that is conventionally formed after die sawing is performed on the wafer. The sheet 160 may be provided with a uniformly applied adhesive 162, the adhesive 162 being used to bond the sheet 160 to the CoW structure. Any suitable type of commercially available adhesive may be used. In some embodiments, TIMs may be used to bond a carrier to a semiconductor die structure. In some embodiments, adhesive 162 may have a thickness of about 50 microns to about 150 microns.
In the next step shown in fig. 9, the CoW structure of fig. 8 with attached sheet 160 is sawn and mounted on a substrate 182, such as a circuit board. The primer material 180 is dispensed into the gap between the sawn CoW structure and the substrate 182. Since the sheet 160 is bonded to the CoW structure before sawing, the edges of the sheet 160 and the adhesive 162 can be flush with the edges of the CoW structure without extrusion. In an exemplary embodiment, the primer material 180 may cover at least a portion of the sheet material 160. However, this is not a limitation of the present disclosure. In an exemplary embodiment, the primer material 180 may cover up to the adhesive 162 or the CoW structure.
In another exemplary embodiment, the process of attaching the sheet material is moved to an earlier stage. In particular, the sheet material is employed to replace the temporary carrier 150 during the process of FIG. 4A. As shown in fig. 4B, a sheet 160 is attached and bonded to the top of the die 110 by an adhesive 162 to support the substrate 120 and mitigate warpage of the CoW structure during further fabrication steps. In the next step shown in fig. 5B, a thinning operation is performed to reduce the thickness of substrate 120, which in this non-limiting embodiment, substrate 120 may be silicon. Thereafter, backside metallization may be performed to complete the C4 or "flip-chip" die package and post operating system (post-OS) operations as shown in fig. 8-9.
Some embodiments of the present disclosure provide a method for fabricating a semiconductor structure, comprising: providing a semiconductor substrate having a plurality of dies thereon; dispensing an underfill material and a molding compound to fill spaces under and between the dies; disposing a temporary carrier over the die; thinning the thickness of the semiconductor substrate; performing backside metallization on the thinned semiconductor substrate; removing the temporary carrier; and an attachment plate over the die.
The foregoing lists features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other operations and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present embodiments, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
Description of the symbols
100 semiconductor structure
110 bare chip
120 substrate
121 surface
122 upper part
123 surface
124 lower part
130 RDL interconnect structure
134 micro-bump
140 primer material
142 Molding compound
150 temporary carrier
152 releasable adhesive
160 plate
162 adhesive
170 RDL interconnection
171 passivation layer
172 dielectric layer
173 pad
174 projection
180 primer material
182 substrate.

Claims (58)

1. A method for fabricating a semiconductor structure, comprising:
providing a semiconductor substrate having a plurality of dies thereon;
dispensing a first underfill material and a molding compound to fill spaces under and between the dies;
disposing a temporary carrier over the die;
thinning the thickness of the semiconductor substrate;
performing backside metallization on the thinned semiconductor substrate;
attaching a board over the die by an adhesive after removing the temporary carrier;
sawing the semiconductor substrate and the plate to obtain singulated semiconductor structures;
mounting the singulated semiconductor structure on a carrier; and
dispensing a second primer material between the singulated semiconductor structures and the carrier, the second primer material covering the adhesive and at least a portion of the sheet.
2. The method of claim 1, further comprising thinning the molding compound to expose the die.
3. The method of claim 1, wherein the attaching the plate over the die comprises attaching a metal plate over the die.
4. The method of claim 3, wherein the attaching the metal plate over the die comprises attaching a Cu plate over the die.
5. The method of claim 3, wherein the attaching the metal sheet over the die comprises attaching a stainless steel sheet over the die.
6. The method of claim 1, wherein the attaching the plate over the die comprises attaching a ceramic plate over the die.
7. The method of claim 1, wherein said attaching the plate over the die comprises attaching the plate over the die by using a Thermal Interface Material (TIM).
8. A method for fabricating a semiconductor structure, comprising:
providing a semiconductor substrate having a plurality of dies thereon;
dispensing a first underfill material and a molding compound to fill spaces under and between the dies;
applying an adhesive to the sheet material;
attaching a plate over the die after dispensing the first underfill material and the molding compound;
thinning a thickness of the semiconductor substrate after attaching the sheet material;
performing backside metallization on the thinned semiconductor substrate after thinning the semiconductor substrate;
sawing the semiconductor substrate comprising the sheet material; and
forming a second primer material to cover the adhesive and at least a portion of the panel.
9. The method of claim 8, further comprising thinning the molding compound to expose the die.
10. The method of claim 8, wherein the attaching the plate over the die comprises attaching a metal plate over the die.
11. The method of claim 10, wherein the attaching the metal plate over the die comprises attaching a Cu plate over the die.
12. The method of claim 10, wherein the attaching the metal sheet over the die comprises attaching a stainless steel sheet over the die.
13. The method of claim 8, wherein the attaching the plate over the die comprises attaching a ceramic plate over the die.
14. The method of claim 8, wherein the attaching the plate over the die comprises attaching the plate over the die by using a Thermal Interface Material (TIM).
15. The method of claim 8, further comprising mounting the sawn semiconductor substrate on another semiconductor substrate.
16. A method for fabricating a semiconductor structure, comprising:
providing a semiconductor substrate having an interconnect structure at a front side thereof;
providing a die having conductive bumps;
disposing the die over the semiconductor substrate to couple the conductive bumps to the interconnect structure;
disposing a first carrier over the dies;
performing metallization on a backside of the semiconductor substrate;
attaching a board over the die by an adhesive after removing the first carrier;
sawing the semiconductor substrate and the plate to obtain singulated semiconductor structures;
mounting the singulated semiconductor structure on a second carrier; and
dispensing an underfill material between the singulated semiconductor structures and the second carrier, the underfill material covering the adhesive and at least a portion of the board.
17. The method of claim 16, wherein the attaching the plate over the die comprises attaching the plate over the die by using a Thermal Interface Material (TIM).
18. The method of claim 16, further comprising:
thinning a thickness of the semiconductor substrate before performing the metallization on the backside of the semiconductor substrate.
19. A semiconductor structure, comprising:
a semiconductor substrate having a front side and a back side opposite the front side;
a plurality of dies on the front side of the semiconductor substrate;
a plate attached over the plurality of dies, wherein the plurality of dies are between the plate and the semiconductor substrate;
an adhesive for joining the sheet material and the plurality of dies, wherein an edge of the adhesive is flush with an edge of the sheet material; and
a first primer material covering edges of the adhesive and edges of the sheet material.
20. The semiconductor structure of claim 19, further comprising a second underfill material filling a space between the plurality of dies and the semiconductor substrate.
21. The semiconductor structure of claim 20, further comprising a metallization layer on the backside of the semiconductor substrate.
22. The semiconductor structure of claim 21, further comprising a molding compound filling a space between the metallization layer and the adhesive.
23. The semiconductor structure of claim 22, wherein the edge of the adhesive is flush with an edge of the molding compound.
24. The semiconductor structure of claim 19, wherein the sheet comprises a Cu sheet.
25. The semiconductor structure of claim 19, wherein the sheet material comprises a stainless steel sheet material.
26. The semiconductor structure of claim 19, wherein the sheet comprises a ceramic sheet.
27. The semiconductor structure of claim 19, wherein the adhesive has a thickness of 50 to 150 microns.
28. A semiconductor structure, comprising:
a first semiconductor substrate having a front side and a backside opposite the front side;
a plurality of dies on the front side of the first semiconductor substrate;
a plate attached over the plurality of dies, wherein the plurality of dies are between the plate and the first semiconductor substrate;
an adhesive for bonding the sheet material and the plurality of dies;
a molding compound filling a space between the first semiconductor substrate and the slab, wherein edges of the slab are flush with edges of the molding compound;
a second semiconductor substrate, wherein the backside of the first semiconductor substrate is bonded to the second semiconductor substrate; and
a primer material covering edges of the molding compound, the adhesive, and the sheet material.
29. The semiconductor structure of claim 28, further comprising an adhesive for attaching the plate to the plurality of dies and the molding compound.
30. The semiconductor structure of claim 28, wherein the sheet comprises a metal.
31. The semiconductor structure of claim 30, wherein the plate comprises Cu.
32. The semiconductor structure of claim 30, wherein the sheet comprises stainless steel.
33. The semiconductor structure of claim 28, wherein the sheet comprises a ceramic.
34. The semiconductor structure of claim 29, wherein the adhesive comprises a thermal interface material, TIM.
35. A semiconductor structure, comprising:
a chip-on-wafer (CoW) assembly including a semiconductor substrate and a plurality of dies on the semiconductor substrate;
a sheet attached over a first side of the CoW assembly;
an adhesive for joining the sheet material and the CoW assembly, wherein an edge of the adhesive is flush with an edge of the CoW assembly;
another semiconductor substrate bonded to a second side of the CoW assembly; and
a primer material disposed between the CoW assembly and the other semiconductor substrate and covering edges of the adhesive and edges of the sheet material.
36. The semiconductor structure of claim 35, wherein the sheet comprises a metal.
37. The semiconductor structure of claim 35, wherein the sheet comprises a ceramic.
38. The semiconductor structure of claim 35, wherein the underfill material further covers at least a portion of the board material.
39. A semiconductor structure, comprising:
a semiconductor substrate having a front side and a back side opposite the front side;
a plurality of dies on the front side of the semiconductor substrate;
a plate attached over the plurality of dies, wherein the plurality of dies are between the plate and the semiconductor substrate;
an adhesive for bonding the sheet material and the plurality of dies; and
a primer material covering the adhesive and at least a portion of the sidewall of the panel.
40. The semiconductor structure of claim 39, wherein an edge of the sheet is flush with an edge of the semiconductor substrate.
41. The semiconductor structure of claim 40, further comprising a metallization layer on the backside of the semiconductor substrate.
42. The semiconductor structure of claim 41, further comprising a molding compound filling a space between the metallization layer and the adhesive.
43. The semiconductor structure of claim 42, wherein an edge of the adhesive is flush with an edge of the molding compound.
44. The semiconductor structure of claim 39, wherein the sheet comprises a Cu sheet having a modulus of from 118 to 130 GPa.
45. The semiconductor structure of claim 39, wherein the sheet comprises a stainless steel sheet having a modulus of from 190 to 203 GPa.
46. The semiconductor structure of claim 39, wherein the sheet comprises a ceramic sheet having a modulus of from 100 to 175 GPa.
47. The semiconductor structure of claim 39, wherein the adhesive has a thickness of 50 to 150 microns.
48. A semiconductor structure, comprising:
a first semiconductor substrate having a front side and a backside opposite the front side;
a plurality of dies on the front side of the first semiconductor substrate;
a plate attached over the plurality of dies, wherein the plurality of dies are between the plate and the first semiconductor substrate;
an adhesive for bonding the sheet material and the plurality of dies;
a molding compound filling a space between the first semiconductor substrate and the plate;
a second semiconductor substrate, wherein the backside of the first semiconductor substrate is bonded to the second semiconductor substrate; and
an underfill material filling a space between the first semiconductor substrate and the second semiconductor substrate and covering the adhesive and at least a portion of the board material.
49. The semiconductor structure of claim 48, further comprising an adhesive for attaching the plate to the plurality of dies and the molding compound.
50. The semiconductor structure of claim 48, wherein the sheet comprises a metal.
51. The semiconductor structure of claim 50, wherein said plate comprises Cu having a modulus of from 118 to 130 GPa.
52. The semiconductor structure of claim 50, wherein the sheet comprises stainless steel having a modulus of from 190 to 203 GPa.
53. The semiconductor structure of claim 48, wherein said sheet comprises a ceramic having a modulus of from 100 to 175 GPa.
54. The semiconductor structure of claim 49, wherein the adhesive comprises a Thermal Interface Material (TIM).
55. A semiconductor structure, comprising:
a chip-on-wafer (CoW) assembly including a semiconductor substrate and a plurality of dies on the semiconductor substrate;
a plate attached over a first side of the CoW assembly, the plate comprising at least one of a metal and a ceramic;
an adhesive for joining the sheet material and the CoW assembly;
another semiconductor substrate bonded to a second side of the CoW assembly; and
a primer material disposed between the CoW assembly and the other semiconductor substrate and covering the adhesive and at least a portion of the sheet material.
56. The semiconductor structure of claim 55, wherein the plate comprises Cu.
57. The semiconductor structure of claim 55, wherein the sheet comprises stainless steel.
58. The semiconductor structure of claim 55, wherein an edge of the slab is flush with an edge of the CoW assembly.
CN201710454238.5A 2016-06-30 2017-06-15 Method for manufacturing semiconductor structure Active CN107564823B (en)

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