CN107546978A - 升压电路 - Google Patents

升压电路 Download PDF

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CN107546978A
CN107546978A CN201710493650.8A CN201710493650A CN107546978A CN 107546978 A CN107546978 A CN 107546978A CN 201710493650 A CN201710493650 A CN 201710493650A CN 107546978 A CN107546978 A CN 107546978A
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circuit
voltage
booster
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input
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CN107546978B (zh
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今井靖
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Seiko Instruments Inc
Ablic Inc
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/06—Acceleration testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12005—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising voltage or current generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/02—Shaping pulses by amplifying
    • H03K5/023—Shaping pulses by amplifying using field effect transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Dc-Dc Converters (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

本发明提供升压电路。提供能够提高被施加升压电压的电路的耐性试验效率的升压电路。分压电路构成为能够根据测试信号而变更分压比，限幅电路构成为箝位在比通常工作时的升压电压高的电压。当在测试模式下将分压电路控制成升压电压高于通常工作时的升压电压时，利用限幅电路对升压电压进行箝位，因此，升压部连续工作。

Description

升压电路
技术领域
本发明涉及升压电路，更具体来说，涉及升压部进行间歇工作的升压电路且是进行被施加升压电压的电路的测试时的电路。
背景技术
在可电性地删除/写入/读出数据的EEPROM等非易失性存储器中，在进行删除/写入动作时，需要对所选择的存储单元施加电源电压以上的高电压。因此，非易失性存储器内置升压电路来产生期望的高电压。
图2是示出现有的用于非易失性存储器的升压电路20的电路图。现有的升压电路20具有PMOS晶体管21、分压电路22、比较电路23、振荡电路24和升压部25。升压部25根据振荡电路24输出的脉冲信号对电源电压VCC进行升压后输出升压电压VPP。分压电路22对升压电压VPP进行分压后输出分压电压VFB。比较电路23比较基准电压VREF和分压电压VFB，输出比较结果的信号。如果分压电压VFB高于基准电压VREF，则比较电路23输出低电平，振荡电路24断开，升压部25停止。此外，如果分压电压VFB低于基准电压VREF，则比较电路23输出高电平，振荡电路24接通，升压部25进行工作。
通过反复进行以上的动作，升压电路20对输出端子输出期望的升压电压VPP(例如，参照专利文献1)。
另外，PMOS晶体管21以如下方式发挥功能：在启动时，当升压电压VPP较低时，PMOS晶体管21截止，使分压电压VFB成为接地电压VSS、即使升压部25进行工作。此外，根据使能端子的信号EN控制振荡电路24和升压部25的工作。
专利文献1：日本特开2010-124590号公报
然而，在对上述那样的被施加现有的升压电路20的升压电压的存储器元件等的电路部分的初始不良进行检查时，升压部25进行间歇工作，因此，存在耐性试验的效率差的课题。即，存在这样的课题：由于实施耐性试验的时间变长，因此，制造成本增加。
发明内容
本发明是鉴于上述课题而提出的，其目的在于提供一种能够提高被施加升压电压的电路的耐性试验效率的升压电路。
本发明的升压电路对输入电压进行升压而输出升压电压，其特征在于，所述升压电路具有：振荡电路，其根据输入的信号而进行间歇工作；升压部，其接收所述振荡电路的脉冲信号而对所述输入电压进行升压；分压电路，其对所述升压电压进行分压，输出分压电压；比较电路，其比较所述分压电压和基准电压，输出比较结果作为所述信号；限幅电路，其对所述升压电压进行箝位；以及测试端子，其输入测试信号，所述分压电路能够根据所述测试信号变更分压比，当所述测试信号表示测试模式时，所述比较电路输出的所述信号使所述升压部连续工作。
发明效果
根据本发明的升压电路，构成为能够改变分压电路的分压比，并且在输出端子设有限幅电路，因此，在测试模式时，能够使升压部连续工作，从而能够提高被施加升压电压的电路的耐性试验的效率。
附图说明
图1是示出本发明的实施方式的升压电路的电路图。
图2是示出现有的升压电路的电路图。
标号说明
12：分压电路；13：比较电路；14：振荡电路；15：升压部；16：限幅电路。
具体实施方式
以下，参照附图对本发明的实施方式进行说明。
图1是示出本发明的实施方式的升压电路10的电路图。
本实施方式的升压电路10具有PMOS晶体管11、分压电路12、比较电路13、振荡电路14、升压部15和限幅电路16。分压电路12具有串联连接的电阻1～3以及NMOS晶体管4，该NMOS晶体管4的源极以及漏极与电阻3的两端连接，栅极与测试端子连接。测试端子输入作为测试信号的信号TEST。限幅电路16由NMOS晶体管5构成，该NMOS晶体管5的源极以及栅极与接地端子连接。
振荡电路14的控制端子与使能端子连接，输出端子与升压部15的输入端子连接。升压部15的控制端子与使能端子连接，输出端子与升压电压输出端子连接。PMOS晶体管11的源极与升压部15的输出端子连接，漏极与分压电路12连接，栅极输入电源电压VCC。分压电路12连接于PMOS晶体管11的漏极和接地端子之间，电阻1和电阻2的连接点与比较电路13的反相输入端子连接。比较电路13的控制端子与使能端子连接，同相输入端子输入基准电压VREF，输出端子与振荡电路14的输入端子连接。
振荡电路14例如是环形振荡器电路等，其振荡动作受比较电路13的输出信号的控制。升压部15例如是电荷泵电路等，根据振荡电路14输出的脉冲信号将电源电压VCC升压到升压电压VPP后输出。分压电路12对升压电压VPP进行分压后输出分压电压VFB。比较电路13比较分压电压VFB和基准电压VREF，如果分压电压VFB低于基准电压VREF，则输出高电平的输出信号，如果分压电压VFB高于基准电压VREF，则输出低电平的输出信号。限幅电路16构成为将升压电压输出端子的电压箝位在比期望的升压电压VPP高的电压。
接下来，对上述那样构成的升压电路10的工作进行说明。
在通常工作时，测试端子输入低电平的信号TEST，分压电路12的NMOS晶体管4截止。即，分压电压VFB是利用电阻1和电阻2、3对升压电压VPP进行分压后的电压。
当使能端子的信号EN变成高电平时，比较电路13、振荡电路14和升压部15开始工作。在初始状态下，升压电压VPP即源极的电压低于电源电压VCC与PMOS晶体管11的阈值电压的绝对值相加后的电压，因此，PMOS晶体管11截止，分压电路12的分压电压VFB成为接近接地端子的电压VSS的电压。因此，基准电压VREF高于分压电压VFB，因此，比较电路13输出高电平的输出信号。振荡电路14从比较电路13接收高电平的输出信号而开始振荡动作。升压部15从振荡电路14接收脉冲信号而开始升压动作。
当升压部15开始升压动作时，升压电压输出端子的升压电压VPP逐渐增高，因此，PMOS晶体管11导通，分压电路12与升压电压输出端子连接，分压电压VFB成为与升压电压VPP对应的电压。
当升压电压VPP上升而使得分压电压VFB超过基准电压VREF时，比较电路13输出低电平的输出信号。从比较电路13接收低电平的输出信号，振荡电路14停止振荡动作，因此，升压部15的升压动作停止。当升压部15的升压动作停止时，升压电压输出端子的升压电压VPP逐渐降低，当分压电压VFB低于基准电压VREF时，比较电路13输出高电平的输出信号。
通过反复进行以上的动作，升压电路10从输出端子输出期望的升压电压VPP。此时，由于限幅电路16被设定成箝位在比期望的升压电压VPP高的电压，因此，限幅电路16不干预升压电压输出端子的电压。
在测试模式时，测试端子输入高电平的信号TEST，分压电路12的NMOS晶体管4导通。即，分压电压VFB成为利用电阻1和电阻2对升压电压VPP进行分压后的电压，因此，在相同的升压电压VPP的情况下，成为比通常工作时低的电压。
当使能端子的信号EN变成高电平时，比较电路13、振荡电路14和升压部15开始工作。
在测试模式时，由于NMOS晶体管4导通，因此，升压部15要从输出端子输出高于通常工作时的测试模式用的升压电压VPP。但是，限幅电路16利用NMOS晶体管5的击穿电压(breakdown voltage)箝位在比测试模式用的升压电压VPP低的升压电压VPP。因此，测试模式时的分压电压VFB始终固定在比基准电压VREF低的电压。即，比较电路13能够持续输出高电平的输出信号，使升压部15连续工作。
如上所述，在测试模式时，升压电路10输出由限幅电路16确定的比通常工作时高的测试模式用的升压电压VPP，并且，升压部15连续工作。因此，升压电路10能够提高与输出端子连接的、被施加升压电压VPP的存储器元件等的电路部分的耐性试验的效率。
以上，对本发明的实施方式进行了说明，但是，本发明的升压电路10不限于上述实施方式，显然能够在不脱离本发明的主旨的范围内进行各种变更。
例如，限幅电路16使用了NMOS晶体管的击穿电压，但是，也可以使用二极管。
此外，关于分压电路12，以根据输入到测试端子的高电平的信号TEST而使NMOS晶体管4导通的方式进行了说明，但是，只要能够改变分压比即可，并不限于该电路。
此外，以升压电路10对电源电压VCC进行升压的方式进行了说明，但是，不限于电源电压VCC，只要对输入的电压进行升压即可。
此外，以升压电路10根据使能端子的信号EN停止启动的方式进行了说明，但是，也可以不具有使能端子。

Claims (3)

1.一种升压电路，该升压电路对输入电压进行升压而输出升压电压，其特征在于，所述升压电路具有：
振荡电路，其根据输入的信号而进行间歇工作；
升压部，其接收所述振荡电路的脉冲信号而对所述输入电压进行升压；
分压电路，其对所述升压电压进行分压，输出分压电压；
比较电路，其比较所述分压电压和基准电压，输出作为比较结果的所述信号；
限幅电路，其对所述升压电压进行箝位；以及
测试端子，其输入测试信号，
所述分压电路能够根据所述测试信号变更分压比，
当所述测试信号表示测试模式时，所述比较电路输出的所述信号使所述升压部连续工作。
2.根据权利要求1所述的升压电路，其特征在于，
当所述测试信号表示测试模式时，所述分压电路以使所述分压电压降低的方式变更分压比。
3.根据权利要求1或2所述的升压电路，其特征在于，
所述限幅电路将所述升压电压箝位在比通常工作时的升压电压高、比测试模式时的升压电压低的电压。
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CN112737329A (zh) * 2020-12-25 2021-04-30 上海贝岭股份有限公司 电压控制、高电压产生电路及方法、设备和存储介质

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CN110211623B (zh) * 2019-07-04 2021-05-04 合肥联诺科技股份有限公司 一种nor flash存储单元阵列的电源系统

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