JP2012244660A - 昇圧回路を備えた半導体装置 - Google Patents
昇圧回路を備えた半導体装置 Download PDFInfo
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- JP2012244660A JP2012244660A JP2011109403A JP2011109403A JP2012244660A JP 2012244660 A JP2012244660 A JP 2012244660A JP 2011109403 A JP2011109403 A JP 2011109403A JP 2011109403 A JP2011109403 A JP 2011109403A JP 2012244660 A JP2012244660 A JP 2012244660A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 239000003990 capacitor Substances 0.000 claims abstract description 29
- 238000011156 evaluation Methods 0.000 claims abstract description 23
- 238000012544 monitoring process Methods 0.000 claims abstract description 3
- 101150098959 MON1 gene Proteins 0.000 abstract description 7
- 101100291875 Neurospora crassa (strain ATCC 24698 / 74-OR23-1A / CBS 708.71 / DSM 1257 / FGSC 987) apg-13 gene Proteins 0.000 abstract description 7
- 230000002093 peripheral effect Effects 0.000 description 9
- 238000012360 testing method Methods 0.000 description 9
- 238000013461 design Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000000047 product Substances 0.000 description 6
- 241001125929 Trisopterus luscus Species 0.000 description 3
- 101000624382 Homo sapiens Protein MON2 homolog Proteins 0.000 description 2
- 102100023396 Protein MON2 homolog Human genes 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
- H01L27/0218—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of field effect structures
- H01L27/0222—Charge pumping, substrate bias generation structures
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- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Read Only Memory (AREA)
- Dc-Dc Converters (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
【解決手段】出力電圧を監視するモニタ電圧MON1に基づいて、出力電圧を所定電圧に制御する制御回路と、出力電圧を通常動作時に第1電圧に設定し、評価時に第1電圧より高い第2電圧に設定するトランジスタTR4,TR5と、出力電圧の振幅をクロック信号の振幅としてクロック信号を発生するクロックドライバ11と、コンデンサ及びダイオードを含む単位回路21が直列に複数段接続され、コンデンサに入力されるクロック信号により電源電圧VCCを昇圧するチャージポンプ12とを備える。
【選択図】図1
Description
図1は、実施形態のNAND型フラッシュメモリの設計から製造までの流れを示すフロー図である。
周辺回路内の昇圧回路は、クロック信号生成回路と、チャージポンプを含む電圧生成回路とを備える。クロック信号生成回路は、チャージポンプを駆動するためのクロック信号を生成する。電圧生成回路は、電源電圧とチャージポンプ駆動用のクロック信号により、電源電圧を昇圧する。以下に、クロック信号生成回路と電圧生成回路について説明する。
次に、実施形態の昇圧回路の動作について説明する。
VCLKSUP=I(R1+R2+R3)
=VREF1(R1+R2+R3)/(R2+R3)=2.5
また、テスト信号TESTが“H”、イネーブル信号ENが“L”のとき(評価時)、
VCLKSUP=I(R1+R2)
=VREF1(R1+R2)/R2=2.7
前記式より、通常動作時では電圧VCLKSUPは2.5Vとなり、評価時では電圧VCLKSUPは2.7Vとなる。電圧VCLKSUPはクロックドライバ11に供給され、クロックドライバ11からクロック信号PMPCLK(2.5Vまたは2.7V)が出力される。
次に、実施形態の昇圧回路におけるチャージポンプ内の基本単位回路21の段数と昇圧電圧との関係について述べる。ここでは、チャージポンプに供給される電源電圧VCCは3.3Vとする。評価時には製品仕様で規定される最低電圧2.7Vを保証する必要がないため3.3Vを使用できるものとする。
Claims (6)
- 出力電圧を監視するモニタ電圧に基づいて、前記出力電圧を所定電圧に制御する制御回路と、
前記出力電圧を通常動作時に第1電圧に設定し、評価時に前記第1電圧より高い第2電圧に設定するスイッチ回路と、
前記出力電圧の振幅をクロック信号の振幅として前記クロック信号を発生するクロックドライバと、
コンデンサ及びダイオードを含む単位回路が直列に複数段接続され、前記コンデンサに入力される前記クロック信号により入力電圧を昇圧するチャージポンプと、
を具備することを特徴とする半導体装置。 - 前記制御回路は、前記モニタ電圧と参照電圧とを比較し、比較結果に基づいた比較信号を出力する差動増幅器と、
前記比較信号がゲートに入力され、前記比較信号に応じた第3電圧を出力する第1トランジスタと、
前記第3電圧がゲートに入力され、前記第3電圧に応じた前記出力電圧を出力する第2トランジスタとを有することを特徴とする請求項1に記載の半導体装置。 - 前記スイッチ回路は、前記第2トランジスタから出力される前記出力電圧が第1抵抗を介して入力される第3トランジスタと、前記出力電圧が第2抵抗を介して入力される第4トランジスタとを有することを特徴とする請求項2に記載の半導体装置。
- 前記単位回路は、前記ダイオードの出力端に前記コンデンサの第1電極が接続され、前記コンデンサの第2電極には前記クロック信号が供給される回路を含むことを特徴とする請求項1乃至3のいずれかに記載の半導体装置。
- 前記ダイオードは、ゲートと電流通路の一端が接続されたトランジスタを含むことを特徴とする請求項1乃至4のいずれかに記載の半導体装置。
- コンデンサ及びダイオード接続されたMOSトランジスタを含む単位回路が直列に複数段接続され、前記コンデンサに入力されるクロック信号により電源電圧を昇圧するチャージポンプと、
前記クロック信号を生成する生成回路とを具備し、
前記入力電圧は2.5V、前記単位回路の段数は2であるとき、前記チャージポンプによって昇圧される電圧は12Vであることを特徴とする半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011109403A JP2012244660A (ja) | 2011-05-16 | 2011-05-16 | 昇圧回路を備えた半導体装置 |
US13/427,009 US20120293243A1 (en) | 2011-05-16 | 2012-03-22 | Semiconductor device including boosting circuit |
Applications Claiming Priority (1)
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JP2011109403A JP2012244660A (ja) | 2011-05-16 | 2011-05-16 | 昇圧回路を備えた半導体装置 |
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JP2012244660A true JP2012244660A (ja) | 2012-12-10 |
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JP2011109403A Withdrawn JP2012244660A (ja) | 2011-05-16 | 2011-05-16 | 昇圧回路を備えた半導体装置 |
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US (1) | US20120293243A1 (ja) |
JP (1) | JP2012244660A (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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KR20160096005A (ko) | 2015-02-04 | 2016-08-12 | 윈본드 일렉트로닉스 코포레이션 | 전압생성회로, 플래시 메모리 및 반도체 장치 |
US11551767B2 (en) | 2020-09-09 | 2023-01-10 | Kioxia Corporation | Semiconductor storage device having boosting circuits with different boosting capacities |
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US11199894B2 (en) * | 2018-10-30 | 2021-12-14 | Dell Products L.P. | Method and apparatus for providing high bandwidth capacitor circuit in power assist unit |
US11126250B2 (en) | 2018-10-30 | 2021-09-21 | Dell Products L.P. | Method and apparatus for extending power hold-up with power assist unit |
US11144105B2 (en) | 2018-10-30 | 2021-10-12 | Dell Products L.P. | Method and apparatus to provide platform power peak limiting based on charge of power assist unit |
US10983577B2 (en) | 2018-10-30 | 2021-04-20 | Dell Products L.P. | Method and apparatus to provide dynamic regulation of power assist unit output based on active profile |
US10951051B2 (en) | 2018-10-30 | 2021-03-16 | Dell Products, L.P. | Method and apparatus to charge power assist unit |
US10852808B2 (en) | 2018-10-31 | 2020-12-01 | Dell Products, L.P. | Method and apparatus to distribute current indicator to multiple end-points |
US10948959B2 (en) | 2018-10-31 | 2021-03-16 | Dell Products, L.P. | Method and apparatus to control power assist unit |
US10990149B2 (en) | 2018-10-31 | 2021-04-27 | Dell Products L.P. | Method and apparatus for providing peak optimized power supply unit |
US11689100B2 (en) * | 2021-07-15 | 2023-06-27 | Nxp Usa, Inc. | High-voltage charge pump using low-voltage technology |
CN114157138B (zh) * | 2021-07-30 | 2024-05-07 | 沈阳工业大学 | 一种高电压开关电容式电压变换器 |
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US5991221A (en) * | 1998-01-30 | 1999-11-23 | Hitachi, Ltd. | Microcomputer and microprocessor having flash memory operable from single external power supply |
US6404274B1 (en) * | 1998-04-09 | 2002-06-11 | Kabushiki Kaisha Toshiba | Internal voltage generating circuit capable of generating variable multi-level voltages |
JP3700173B2 (ja) * | 2002-05-28 | 2005-09-28 | ソニー株式会社 | 電圧変換制御回路及び方法 |
JP4287678B2 (ja) * | 2003-03-14 | 2009-07-01 | Okiセミコンダクタ株式会社 | 内部電源回路 |
ITMI20031924A1 (it) * | 2003-10-07 | 2005-04-08 | Atmel Corp | Convertitore da digitale ad analogico ad alta precisione con consumo di energia ottimizzato. |
US7034602B2 (en) * | 2004-03-29 | 2006-04-25 | Semiconductor Components Industries, L.L.C. | Method of forming a floating charge pump and structure therefor |
JP2007004887A (ja) * | 2005-06-23 | 2007-01-11 | Toshiba Corp | 半導体記憶装置 |
JP4843472B2 (ja) * | 2006-03-13 | 2011-12-21 | 株式会社東芝 | 電圧発生回路 |
JP2008054471A (ja) * | 2006-08-28 | 2008-03-06 | Toshiba Corp | 昇圧回路および電圧供給回路 |
US7724075B2 (en) * | 2006-12-06 | 2010-05-25 | Spansion Llc | Method to provide a higher reference voltage at a lower power supply in flash memory devices |
ITMI20062517A1 (it) * | 2006-12-28 | 2008-06-29 | St Microelectronics Srl | Regolatore di una pompa di carica e struttura circuitale comprendente detto regolatore |
US7795951B2 (en) * | 2007-11-30 | 2010-09-14 | Freescale Semiconductor, Inc. | High-dynamic range low ripple voltage multiplier |
KR101139102B1 (ko) * | 2010-12-03 | 2012-04-30 | 에스케이하이닉스 주식회사 | 전압 공급 회로 및 이를 구비한 집적 회로 |
-
2011
- 2011-05-16 JP JP2011109403A patent/JP2012244660A/ja not_active Withdrawn
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2012
- 2012-03-22 US US13/427,009 patent/US20120293243A1/en not_active Abandoned
Cited By (4)
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KR20160096005A (ko) | 2015-02-04 | 2016-08-12 | 윈본드 일렉트로닉스 코포레이션 | 전압생성회로, 플래시 메모리 및 반도체 장치 |
US9627963B2 (en) | 2015-02-04 | 2017-04-18 | Winbond Electronics Corp. | Voltage generation circuit, flash memory and semiconductor device |
KR20170082139A (ko) | 2015-02-04 | 2017-07-13 | 윈본드 일렉트로닉스 코포레이션 | 전압생성회로, 플래시 메모리 및 반도체 장치 |
US11551767B2 (en) | 2020-09-09 | 2023-01-10 | Kioxia Corporation | Semiconductor storage device having boosting circuits with different boosting capacities |
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US20120293243A1 (en) | 2012-11-22 |
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