CN107546192A - 经封装半导体装置 - Google Patents

经封装半导体装置 Download PDF

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Publication number
CN107546192A
CN107546192A CN201610905039.7A CN201610905039A CN107546192A CN 107546192 A CN107546192 A CN 107546192A CN 201610905039 A CN201610905039 A CN 201610905039A CN 107546192 A CN107546192 A CN 107546192A
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CN
China
Prior art keywords
encapsulating structure
hole
conductive projection
cutting edge
outer side
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Pending
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CN201610905039.7A
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English (en)
Inventor
林俊成
郑礼辉
蔡柏豪
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN107546192A publication Critical patent/CN107546192A/zh
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Abstract

一种经封装半导体装置包括第一封装结构、至少一外侧导电凸块、第二封装结构、密封材料以及电磁干扰(EMI)屏蔽层。第一封装结构具有第一切割边。外侧导电凸块配置于第一封装结构上且具有第二切割边。第二封装结构接附于第一封装结构上。密封材料配置于第一封装结构上，围绕第二封装结构且覆盖外侧导电凸块。密封材料具有第三切割边。电磁干扰屏蔽层接触第一切割边、第二切割边与第三切割边。电磁干扰屏蔽层电性连接于外侧导电凸块。

Description

经封装半导体装置
技术领域
本发明实施例涉及一种经封装半导体装置与制作经封装半导体装置的方法。
背景技术
集成电路的封装技术涉及将集成电路(Integrated Circuit，IC)管芯密封于密封材料以及建立需要的重布线层(redistribution layer)。因为半导体工业中持续存在低成本、高效能、增加集成电路密度与增加封装密度的需求，于封装上封装(package-on-package，POP)的叠层封装技术变得越来越普及。为了制作出越来越小的封装体，IC芯片与封装体的整合，诸如：预叠层(pre-stacking)或是系统单芯片(system on a chip，SoC)与内存的整合技术，使得封装体可以更薄。
发明内容
根据本发明的实施例，经封装半导体装置包括第一封装结构、至少一外侧导电凸块、第二封装结构、密封材料以及电磁干扰(EMI)屏蔽层。第一封装结构具有第一切割边。外侧导电凸块配置于第一封装结构上且具有第二切割边。第二封装结构接附于第一封装结构上。密封材料配置于第一封装结构上，围绕第二封装结构且覆盖外侧导电凸块。密封材料具有第三切割边。电磁干扰屏蔽层接触第一切割边、第二切割边与第三切割边。电磁干扰屏蔽层电性连接于外侧导电凸块。
附图说明
包含附图以便进一步理解本发明，且附图并入本说明书中并构成本说明书的一部分。附图说明本发明的实施例，并与描述一起用于解释本发明的原理。
图1为依据部分实施例的制作经封装半导体装置的方法而示意性表示的形成聚合物缓冲层的步骤；
图2与图3为依据部分实施例的制作经封装半导体装置的方法而示意性表示的形成通孔的步骤；
图4为依据部分实施例的制作经封装半导体装置的方法而示意性表示的管芯接合步骤；
图5为依据部分实施例的制作经封装半导体装置的方法而示意性表示的形成封装结构的步骤；
图6为依据部分实施例的制作经封装半导体装置的方法而示意性表示的于封装结构上形成重布线层的步骤；
图7为依据部分实施例的制作经封装半导体装置的方法而示意性表示的形成导电凸块的步骤；
图8与9为依据部分实施例的制作经封装半导体装置的方法而示意性表示的移除载体的步骤；
图10为依据部分实施例的制作经封装半导体装置的方法而示意性表示的形成导电凸块的步骤；
图11为依据部分实施例的制作经封装半导体装置的方法而示意性表示的于封装结构上接附封装结构的步骤；
图12为依据部分实施例的制作经封装半导体装置的方法而示意性表示的单一化工艺的步骤；
图13示意性地表示依据部分实施例的经封装半导体装置；
图14为部分实施例的经封装半导体装置的局部放大示意图。
附图标号说明
100：第一封装结构；
100E：第一切割边；
110：载体；
120：聚合物缓冲层；
150：导电通孔组；
152：外侧通孔；
152A、154A、162A：上表面；
152B、154B：被暴露的表面；
152E、154E：外边缘；
154：内侧通孔；
156：图案层；
158：开口；
160、510：管芯；
162：导电接合垫；
170：管芯贴合黏合剂；
180、530：模塑料；
180R：凹陷；
180T：顶部；
190、520：重布线层；
192：走线；
200：底导电凸块；
300：载体膜；
400、600：导电凸块；
410：外侧导电凸块；
410E：第二切割边；
420：内侧导电凸块；
500：第二封装结构
700：密封材料；
700E：第三切割边；
700T：顶表面；
800：叠层封装装置；
800E：侧边缘；
810：电磁干扰屏蔽层；
900：经封装半导体装置；
900B：底部；
910：中间导电凸块；
B：能量束；
G1、G2、G3：距离；
H：高度；
S：单一化工艺；
WB、WP、WV：宽度；
WC：接触宽度。
具体实施方式
以下揭露内容提供用于实施所提供的目标中的不同特征的许多不同实施例或实例。以下所描述的构件及配置的具体实例是为了以简化的方式传达本揭露为目的。当然，这些仅仅为实例而非用以限制。举例来说，于以下描述中，在第一特征上方或在第一特征上形成第二特征可包括第二特征与第一特征形成为直接接触的实施例，且亦可包括第二特征与第一特征之间可形成有额外特征使得第二特征与第一特征可不直接接触的实施例。此外，本揭露在各种实例中可使用相同的组件符号及/或字母来指代相同或类似的部件。组件符号的重复使用是为了简单及清楚起见，且并不表示所欲讨论的各个实施例及/或配置本身之间的关系。
另外，为了易于描述附图中所表示的一个构件或特征与另一组件或特征的关系，本文中可使用例如「在...下」、「在...下方」、「下部」、「在…上」、「在…上方」、「上部」及类似术语的空间相对术语。除了附图中所表示的定向之外，所述空间相对术语意欲涵盖组件在使用或操作时的不同定向。设备可被另外定向(旋转90度或在其他定向)，而本文所用的空间相对术语相应地作出解释。
参照图1，提供载体110并将聚合物缓冲层120形成于载体110上。在一些实施例中，载体110可为具有足够坚硬性质或是刚性的基板，以为后续工艺提供稳固的支撑。载体110可以是玻璃基板，但不以此为限。在一些实施例中，载体110可自形成其上的装置移除而完成最终装置，因此可在载体110上形成未表示于图中的暂时黏着层，以在制造过程中将聚合物缓冲层120与载体110连接。暂时黏着层可由胶体材料制造，或是由包括至少一胶层与至少一聚合物层的多个层来形成。
在一些实施例中，可在聚合物缓冲层120上形成未表示于图中的种子金属层。形成种子金属层的方法包括化学气相沉积(chemical vapor deposition，CVD)、物理气相沉积(physical vapor deposition，PVD)、原子层沉积(atomic layer deposition，ALD)、高密度电浆化学气相沉积(high density plasma CVD，HDPCVD)法、其他合适方法、或上述方法的任何组合。接着，如图2所示，将多个导电通孔组150形成于聚合物缓冲层120上。在一些实施例中，种子金属层可被省略，且导电通孔组150可形成于聚合物缓冲层120上而无种子金属层插置于聚合物缓冲层120与导电通孔组150之间。
在一些实施例中，导电通孔组150的每一者包括至少一个外侧通孔152与至少一个内侧通孔154。以呈现于图2的结构为例，两个导电通孔组150彼此相邻设置时，其中一个导电通孔组150的外侧通孔152相较于同一个导电通孔组150的内侧通孔154而言，更为接近邻近的导电通孔组150的外侧通孔152。
在一些实施例中，外侧通孔152与内侧通孔154可通过以下举例说明的步骤来形成，但不以此为限。在聚合物缓冲层120上形成图案层156，且图案层156具有多个对应于个别预定位置的开口158。在一些实施例中，图案层156的材料可为光阻材料、光敏性材料或类似材料，且图案层156可通过光刻工艺来形成，以使图案层156具有开口158。此后，图案层156的开口158可被填充以导电材料以形成外侧通孔152与内侧通孔154。举例而言，导电材料包括钛、钨、铝、铜、金属合金、金属硅化物、其他合适材料或是上述材料的任何组合。此外，将导电材料填充于开口158的方法包括化学气相沉积、物理气相沉积、原子层沉积、高密度电浆化学气相沉积法、镀覆法、其他合适方法或上述方法的任何组合。在一些实施例中，聚合物缓冲层120与图案层156之间的种子金属层可应用于镀覆法中，例如电镀，但不以此为限。在一些实施例中，种子金属层的材料可包括钛、铜或上述材料的组合。
接着，如图3所示，移除图案层156，而在图案层156移除之后，外侧通孔152与内侧通孔154彼此相隔开。在一些实施例中，移除图案层156的方法可包括剥除工艺或是蚀刻工艺。其中一个导电通孔组150的外侧通孔152可与邻近的导电通孔组150的外侧通孔152以距离G1相隔开。换言之，距离G1形成于其中一个导电通孔组150的外侧通孔152的外边缘152E与邻近的导电通孔组150的外侧通孔152的外边缘152E之间。外侧通孔152与内侧通孔154可具有足够的高度H以提供垂直的电性传导路径。
参照图4，使用晶粒贴合膜(die attach film)，将多个管芯(die)160放置于聚合物缓冲层120上并贴附于聚合物缓冲层120。在一些实施例中，管芯贴合黏合剂170可使用于管芯160的背侧。管芯160的每一者具有多个导电接合垫162。在此描述的示例中，导电接合垫162以面朝上的方式定向。在一实施例中，管芯160的导电接合垫162可包括铜柱(Cupost)或柱状凸块。管芯160可分别为任何的集成电路且可为内存或应用处理器(application processor,AP)，其中应用处理器诸如微处理器、数字信号处理器、通用处理器或是特殊应用集成电路(application specific integrated circuit，ASIC)。在一些实施例中，外侧通孔152与内侧通孔154个别的高度H足够让外侧通孔152与内侧通孔154的顶部超出或是等于管芯160的顶部的高度准位。
如图5所示，将管芯160接附至聚合物缓冲层120后，形成模塑料180以密封管芯160与导电通孔组150。模塑料180填充外侧通孔152与内侧通孔154之间的空间、内侧通孔154之间的空间、相邻两导电通孔组150的外侧通孔152之间的空间以及内侧通孔154与管芯160之间的空间。在一些实施中，模塑料180一体的密封与包覆管芯160及导电通孔组150。模塑料180的材料可为可通过热固化工艺或是紫外光固化工艺被固化的树脂。
接续密封工艺后，可于模塑料180的顶部180T施行研磨工艺。研磨工艺移除至少一部分的模塑料180。在一些实施例中，研磨工艺持续进行直到外部通孔152的上表面152A的一部分、内部通孔154的上表面154A的一部份与导电接合垫162的上表面162A的一部份暴露出来。在一些实施例中，研磨工艺可包括化学机械研磨(Chemical-MechanicalPlanarization，CMP)、抛光工艺或类似的工艺。
再者，参照图6，可于模塑料180经研磨的表面上形成重布线层190。重布线层190可包括有诸如铜走线的至少一导体分布于至少一个介电材料层中。在一示例中，走线192形成于绝缘层194中，且重布线层190中的走线192可连接至外侧通孔152的上表面152A、内侧通孔154的上表面154A以及导电接合垫162的上表面162A。此外，走线192可提供预定的布局以规划出管芯160与导电通孔组150的电性传导路径。
如图6所示，多个第一封装结构100现已形成于载体110上，且这些第一封装结构100使用相同的模塑料(例如模塑料180)密封。其中一个第一封装结构100可包括管芯160、导电通孔组150、模塑料180与重布线层190。管芯160与导电通孔组150被模塑料180密封与围绕。此外，外侧通孔152与内侧通孔154可贯穿模塑料180，而导电通孔组150可将重布线层190的一部分与后续堆栈的管芯或组件电性连接。换言之，导电通孔组150可提供垂直电性传输路径，使得重布线层190可电性连接于另一组件。在此，另一组件诸如位于模塑料180的相对侧的管芯或是其他构件。
在一些实施例中，重布线层190的表面可接收焊锡凸块或是其他电性连接件。举例而言，参照图7，形成多个底导电凸块200于重布线层190上，且底导电凸块200可分别电性连接于重布线层190的走线192。底导电凸块200可为控制塌陷高度芯片连接件(controlledcollapsing chip connectors，C4)、焊锡凸块或是其他用以连接至外部组件的连接件。再者，既然底导电凸块200电性连接于重布线层190，底导电凸块200的至少一部份可通过重布线层190与导电通孔组150来电性连接于另一组件，像是在后续工艺中要配置于模塑料180相对侧的芯片或是其他构件。
此后，参照图8，图7中所呈现的结构在此被上下颠倒定向。在图8的步骤中，被相同的模塑料180密封在一起的第一封装结构100被接附到载体膜300而以载体膜300覆盖这些底导电凸块200。进行脱黏工艺(debonding process)以自第一封装结构100将载体110移除。在一实施例中，脱黏工艺可包括将能量束B由载体110的一侧施加至暂时黏着层(未示于图中)。在一些实施例中，能量束B可为具有足够能量以让暂时黏着层的黏着性质劣化的激光束。在其他实施例中，能量束B可提供足够的能量以将暂时黏着层烧失。在移除载体110的工艺中，覆盖住底导电凸块200的载体膜300可支撑第一封装结构100且保护底导电凸块200以避免底导电凸块200在后续工艺中受到损坏或是脱离。此外，能量束B可为点状射束、线性射束等，而所谓的束或射束并不限于形成特定的照射面积。
参照图9，移除载体110后，可进行背侧接垫开口工艺。进行背侧接垫开口工艺可移除至少部份的聚合物缓冲层120，其通过激光钻孔、干/湿清洗或类似方式使外侧通孔152与内侧通孔154暴露出来。在一些实施例中，背侧接垫开口工艺会持续进行直到外侧通孔152与内侧通孔154暴露出来。此后，可进行焊锡糊浆形成工艺。
外侧通孔152被暴露的表面152B与内侧通孔154被暴露的表面154B可接收焊锡凸块或其他电性连接件。举例来说，参照图10，多个导电凸块400形成于外侧通孔152与内侧通孔154上，且分别电性连接于外侧通孔152与内侧通孔154。导电凸块400可为控制塌陷高度芯片连接件、焊锡凸块或是其他用以连接至外部组件的连接件。根据配置位置，导电凸块400可包括多个外侧导电凸块410与多个内侧导电凸块420。外侧导电凸块410电性连接于外侧通孔152。此外，一个外侧通孔152可电性连接于一个外侧导电凸块410与一个内侧导电凸块420。
在一些实施例中，电性连接于其中一个第一封装结构100的外侧导电凸块410，相较于电性连接于相同第一封装结构100的内侧导电凸块420来说，更接近于电性连接至邻近的第一封装结构100的外侧导电凸块410。外侧导电凸块410可采用一部分的外侧导电凸块410超出外侧通孔152的外边缘152E的方式而配置于外侧通孔152上。换言之，其中一个第一封装结构100的外侧导电凸块410与邻近的第一封装结构100的外侧导电凸块410之间的距离G2可小于此第一封装结构100的外侧通孔152与邻近的第一封装结构100的外部通孔152之间的距离G1。
如图10所示，外侧导电凸块410在外边缘152E附近接触对应的外侧通孔152。并且，外侧导电凸块410接触于对应的外侧通孔152的接触面积可占据外侧通孔152的一部分顶表面。外侧导电凸块410具有的宽度WB可大于外侧导电凸块410接触于外侧通孔152的上表面152A的接触宽度WC。在一些实施例中，外侧导电凸块410接触于外侧通孔152的接触宽度WC可为5微米(μm)至50微米，或可为20微米。
参照图11，可将多个第二封装结构500分别接合至第一封装结构100上，且形成密封材料700以密封第二封装结构500。在一些实施例中，第二封装结构500可通过导电凸块600接合至第一封装结构100。导电凸块600可放置于形成在外侧通孔152与内侧通孔154上的内侧导电凸块420上，且导电凸块600可接合于形成在外侧通孔152与内侧通孔154上的内侧导电凸块420上。换言之，第二封装结构500可采用覆晶方式接合至第一封装结构100。第二封装结构500可为使用覆晶技术接合至第一封装结构100的内存组件。在一些实施例中，内存组件可包括动态随机存取内存(DRAM)，但不以此为限。
在一些实施例中，第二封装结构500的其中一个包括至少一管芯510、重布线层520与模塑料530。管芯510可配置于重布线层520上并与重布线层520电性连接。模塑料530可于重布线层520上方密封管芯510。此外，导电凸块600可配置在第二封装结构500中暴露出重布线层520的底部。在一些实施例中，第二封装结构500可不覆盖外侧导电凸块410，使得外侧导电凸块410在第二封装结构500接合至第一封装结构100之后被暴露出来。可形成密封材料700来填充第一封装结构100与第二封装结构500之间的空间。密封材料700覆盖外侧导电凸块410且围绕第二封装结构500。在一些实施例中，密封材料700在第二封装结构500的周边可具有斜面或是凹陷的轮廓，并作为填底胶。在其他实施例中，密封材料700的顶表面可低于第二封装结构500的顶表面。
同时参照图11与图12，进行单一化工艺S以形成多个叠层封装(POP)装置800。沿着切割轨迹来切割图11表示的结构以进行单一化工艺S。可控制切割轨迹使其路径位于距离G2的区域内而不超出距离G1的区域。在一些实施例中，在单一化工艺S后，第一封装结构100可具有第一切割边100E，外侧导电凸块410可具有第二切割边410E，且密封材料700可具有第三切割边700E，使得外侧导电凸块410如图12所示地暴露出来。此外，外侧通孔152的外边缘152E可不在第一封装结构100的第一切割边100E露出而保持被模塑料180围绕。换言之，第一切割边100E为第一封装结构100的模塑料180被暴露出来的部份。
在一些实施例中，距离G3可存在于外侧通孔152的外边缘152E与第一切割边100E之间，且模塑料180填充距离G3所在区域。在单一化工艺期间，外侧通孔152可不被切割而维持着被模塑料180覆盖，这避免了外侧通孔152被切割而导致的金属污迹作用。在单一化工艺期间，让外侧通孔152被切割的情形下，第一切割边100E可能因为外侧通孔152的金属污迹作用而不平坦也不平顺。因此，进行单一化工艺并使模塑料180保持于覆盖且围绕外侧通孔152，这有助于提升良率且提升第一封装结构100在第一切割边100E的平坦性。
载体膜300可在单一化工艺后移除，且接续地于单独的叠层封装装置800上形成电磁干扰(electromagnetic interference，EMI)屏蔽层810。如此一来，即形成如图13所示的经封装半导体装置900。电磁干扰屏蔽层810经制作成以共型方式覆盖第一切割边100E、第二切割边410E、第三切割边700E与密封材料700的顶表面700T。在一些实施例中，外侧导电凸块410在第二切割边410E暴露出来，且电磁干扰屏蔽层810可以电性耦合于暴露出来的外侧导电凸块410。电磁干扰屏蔽层810可在使用时提供阻挡电磁干扰的功能。在一些实施例中，暴露出来的外侧导电凸块410通过对应的外侧通孔152与重布线层190连接至底导电凸块200，以将电磁干扰屏蔽层810电性接地。
电磁干扰屏蔽层810可以电传导性材料来制作。电磁干扰屏蔽层810的材料可包括铜、镍、镍铁合金、铜镍合金、银等。但不以此为限。在一些实施例中，电磁干扰屏蔽层810可使用电镀法、无电镀法、溅镀法、物理气相沉积法、化学气相沉积法、大气环境电浆沉积法、喷涂或是其他合适的金属沉积工艺来制作。在一些实施例中，第一切割边100E、第二切割边410E与第三切割边700E共同形成侧边缘800E。侧边缘800E为平坦的而无因为金属污迹效应而产生的皱褶。形成于平坦的侧边缘800E上的电磁干扰屏蔽层810的厚度可实质上为均匀的。换言之，电磁干扰屏蔽层810可共形于侧边缘800E而提供良好的电磁干扰屏蔽效应。以导电性或磁性材料制作的屏障来阻挡电磁场，而使得电磁干扰屏蔽层810可用以降低或是屏蔽空间中的电磁场。电磁干扰屏蔽层810在一些实施例中可抑制诸如无线电波、电磁场与静电场的耦合。
参照图13，经封装半导体装置900可包括第一封装结构100、多个底导电凸块200、多个导电凸块400、第二封装结构500、多个导电凸块600、密封材料700与电磁干扰屏蔽层810。底导电凸块200与导电凸块400可配置于第一封装结构100的两相对表面。第二封装结构500可通过导电凸块600接合至第一封装结构100。导电凸块600可连接至导电凸块400中的内侧导电凸块420以形成多个中间导电凸块910。在一些实施例中，密封材料700填充第一封装结构100与第二封装结构500之间的间隙。密封材料700可围绕第二封装结构500、中间导电凸块910与导电凸块400中的外侧导电凸块410。经封装半导体装置900的第一封装结构100、外侧导电凸块410与密封材料700可具有第一切割边100E、第二切割边410E与第三切割边700E。第一切割边100E、第二切割边410E与第三切割边700E共同形成侧边缘800E。电磁干扰屏蔽层810覆盖侧边缘800E与密封材料700的顶表面700T。此外，底导电凸块200可暴露出来而不被电磁干扰屏蔽层810覆盖。
在一些实施例中，第一封装结构100可包括聚合物缓冲层120、多个外侧通孔152、多个内侧通孔154、管芯160、模塑料180与重布线层190。模塑料180可密封管芯160，且围绕外侧通孔152与内侧通孔154。外侧通孔152与内侧通孔154可贯穿模塑料180以将导电凸块400与重布线层190电性连接。此外，外侧通孔152的外边缘152E可被模塑料180覆盖而不在第一切割边100E暴露出来。
底导电凸块200可配置于重布线层190上且在经封装半导体装置900的底部900B暴露出来，以连接至外部组件。导电凸块400可包括外侧导电凸块410与内侧导电凸块420。外侧导电凸块410配置在第一封装结构100的周边。内侧导电凸块420连接至导电凸块600以将第一封装结构100与第二封装结构500电性连接。在一些实施例中，内侧导电凸块420连接至导电凸块600以形成中间导电凸块910。外侧导电凸块410可连接至外侧通孔152且具有暴露出来的第二切割边410E。在一些实施例中，一个外侧通孔152的宽度WV足够大以连接一个外侧导电凸块410与一个内侧导电凸块420。举例而言，外部通孔152的宽度WV可以为300微米至1200微米。在一些实施例中，外部通孔152的宽度WV可为1050微米。电磁干扰屏蔽层810可直接覆盖于暴露出来的外部导电凸块410上以将外侧通孔152与对应的底导电凸块200电性连接。
第二封装结构500可以覆晶方式接合至第一封装结构100。在一些实施例中，导电凸块600可放置于第二封装结构500上，并接着将第二封装结构500上的导电凸块600接附至第一封装结构100上的内侧导电凸块420而形成了连接在第一封装结构100与第二封装结构500之间中间导电凸块910。在一些实施例中，第一封装结构100可大于第二封装结构500，且第一封装结构100上的外侧导电凸块410可不被第二封装结构500覆盖也不连接至第二封装结构500。换言之，第二封装结构500上的导电凸块600可不接附至外侧导电凸块410。
密封材料700可密封第二封装结构500、外侧导电凸块410与中间导电凸块910以将第一封装结构100与第二封装结构500封装在一起而建构出于封装上封装的叠层封装装置。电磁干扰屏蔽层810可以共形的方式覆盖第一切割边100E、第二切割边410E、第三切割边700E与顶表面700T，而不连接至底导电凸块200。电磁干扰屏蔽层810可通过外侧导电凸块410电性连接于外侧通孔152而不直接接触外侧通孔152。换言之，电磁干扰屏蔽层810可通过模塑料180而实体上与外侧通孔152隔离。
参照图14，外侧导电凸块410可部分地接触外侧通孔152，且由外侧导电凸块410接触于外侧通孔152处向外延伸出去。外侧导电凸块410可具有宽度WP，宽度WP大于外侧导电凸块410接触于外侧通孔152的上表面152A的接触宽度WC。一并参照图10与图14，外侧导电凸块410受到单一化工艺后的宽度WP可实质上相同于或是小于外侧导电凸块410在单一化工艺之前的宽度WB。再者，接触宽度WC可小于宽度WP与宽度WB两者。在一些实施例中，宽度WP相对于接触宽度WC的比例可为大于2至1。在一些实施例中，外侧导电凸块410接触于外侧通孔152的上表面152A的接触宽度WC可为5微米到100微米或是20微米到50微米。此外，模塑料180可围绕外侧通孔152，且外侧通孔152的外边缘152E可与第一切割边100E分离一距离G3。在一些实施例中，外侧导电凸块410可进一步覆盖外侧通孔152的外边缘152E的一部份，使外侧导电凸块410可稳固地接触于外侧通孔152。在一些实施例中，模塑料180可在外侧通孔152附近具有凹陷180R，且一部分的密封材料700可填充此凹陷180R。换言之，凹陷180R可被密封材料700填充且一部分的密封材料700可填充于外侧导电凸块410与模塑料180之间。
在本发明实施例中，经封装半导体装置包括第一封装结构、至少一外侧导电凸块、第二封装结构、密封材料以及电磁干扰(EMI)屏蔽层。第一封装结构具有第一切割边。外侧导电凸块配置于第一封装结构上且具有第二切割边。第二封装结构接附于第一封装结构上。密封材料配置于第一封装结构上，围绕第二封装结构且覆盖外侧导电凸块。密封材料具有第三切割边。电磁干扰屏蔽层接触第一切割边、第二切割边与第三切割边。电磁干扰屏蔽层电性连接于外侧导电凸块。
在本发明实施例中，经封装半导体装置包括第一封装结构、至少一外侧导电凸块、第二封装结构、密封材料与电磁干扰屏蔽层。第一封装结构包括管芯、模塑料与至少一外侧通孔。管芯与外侧通孔被模塑料密封，且外侧通孔贯穿模塑料。外侧导电凸块配置于第一封装结构且连接至外侧通孔。第二封装结构接附于第一封装结构上。密封材料配置于第一封装结构上，围绕第二封装结构且覆盖外侧导电凸块。电磁干扰屏蔽层接触密封材料、第一封装结构与外侧导电凸块。外侧导电凸块接触电磁干扰屏蔽层与外侧通孔。电磁干扰屏蔽层通过外侧导电凸块电性连接至外侧通孔。
在本发明实施例中，经封装半导体装置的制作方法包括至少以下步骤。将多个外侧导电凸块分别形成在由模塑料密封的多个第一封装结构上。一个第一封装结构上的一个外侧导电凸块与相邻的第一封装结构上的另一个外侧导电凸块分隔一距离。第二封装结构接附至第一封装结构上且第二封装结构暴露出外侧导电凸块。使用密封材料将第二封装结构密封在第一封装结构上。进行单一化工艺以将密封材料、外侧导电凸块与模塑料切穿，以形成多个叠层封装装置且外侧导电凸块在叠层封装装置的侧边暴露出来。
在部分实施例中，第一切割边、第二切割边与第三切割边形成侧边缘且电磁干扰屏蔽层以共形方式覆盖侧边缘。第一封装结构包括管芯、模塑料与至少一外侧通孔。管芯与外侧通孔被模塑料密封。外侧通孔贯穿模塑料且电磁干扰屏蔽层通过外侧导电凸块而电性连接外侧通孔。外侧通孔的外边缘被模塑料覆盖且与第一切割边相隔一距离。外侧导电凸块的宽度大于外侧导电凸块接触于外侧通孔的接触宽度。将多个中间导电凸块连接于第一封装结构与第二封装结构之间，其中中间导电凸块被密封材料围绕。外侧导电通孔连接至外侧导电凸块与一个中间导电凸块。将多个底导电凸块配置于第一封装结构并在经封装半导体装置的底部暴露出底导电凸块。沿着不同第一封装结构的外侧导电凸块间的距离存在处而延伸的切割路径切割密封材料与模塑料而进行单一化工艺。于封装上封装的叠层封装装置，在单一化工艺后，个别具有第一封装结构的第一切割边、外侧导电凸块的第二切割边与密封材料的第三切割边。第一切割边暴露出模塑料。
上述内容已描述几个实施例的特征使所属技术领域中具有通常知识者更好的了解本揭露内容的观点。所属技术领域中具有通常知识者应领会到其可使用本揭露内容作为修改或设计其他工艺与结构的基础，以为了实现相同目的及/或达成在此引入的实施例的相同优点。任何所属技术领域中具有通常知识者应也理解不脱离本揭露内容所述的精神和范围内的等同架构，且在不脱离本发明实施例的精神和范围内，当可作各式的更动、取代与替换。

Claims (1)

1.一种经封装半导体装置，包括：
第一封装结构，其具有第一切割边；
至少一外侧导电凸块，配置于所述第一封装结构上且具有第二切割边；
第二封装结构，接附于所述第一封装结构上；
密封材料，配置于所述第一封装结构上，围绕所述第二封装结构，且覆盖所述外侧导电凸块，其中所述密封材料具有第三切割边；以及
电磁干扰屏蔽层，配置于所述第一切割边、所述第二切割边与所述第三切割边上，且电性连接所述外侧导电凸块。
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