TW201801264A - 經封裝半導體裝置與製作經封裝半導體裝置的方法 - Google Patents

經封裝半導體裝置與製作經封裝半導體裝置的方法 Download PDF

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TW201801264A
TW201801264A TW105133487A TW105133487A TW201801264A TW 201801264 A TW201801264 A TW 201801264A TW 105133487 A TW105133487 A TW 105133487A TW 105133487 A TW105133487 A TW 105133487A TW 201801264 A TW201801264 A TW 201801264A
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package structure
conductive
cutting edge
conductive bumps
layer
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TW105133487A
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林俊成
鄭禮輝
蔡柏豪
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台灣積體電路製造股份有限公司
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Abstract

在本發明實施例中，經封裝半導體裝置包括第一封裝結構、至少一外側導電凸塊、第二封裝結構、密封材料以及電磁干擾(EMI)屏蔽層。第一封裝結構具有第一切割邊。外側導電凸塊配置於第一封裝結構上且具有第二切割邊。第二封裝結構接附於第一封裝結構上。密封材料配置於第一封裝結構上，圍繞第二封裝結構且覆蓋外側導電凸塊。密封材料具有第三切割邊。電磁干擾屏蔽層接觸第一切割邊、第二切割邊與第三切割邊。電磁干擾屏蔽層電性連接於外側導電凸塊。

Description

經封裝半導體裝置與製作經封裝半導體裝置的方法
本發明實施例是有關於一種經封裝半導體裝置與製作經封裝半導體裝置的方法。
積體電路的封裝技術涉及將積體電路(Integrated Circuit， IC)晶片密封於密封材料以及建立需要的重佈線層(redistribution layer)。因為半導體工業中持續存在低成本、高效能、增加積體電路密度與增加封裝密度的需求，於封裝上封裝(package-on-package， POP)的層疊式封裝技術變得越來越普及。為了製作出越來越小的封裝體，IC晶片與封裝體的整合，諸如：預疊層(pre-stacking)或是系統單晶片(system on a chip， SoC)與記憶體的整合技術，使得封裝體可以更薄。
根據本發明的實施例，經封裝半導體裝置包括第一封裝結構、至少一外側導電凸塊、第二封裝結構、密封材料以及電磁干擾(EMI)屏蔽層。第一封裝結構具有第一切割邊。外側導電凸塊配置於第一封裝結構上且具有第二切割邊。第二封裝結構接附於第一封裝結構上。密封材料配置於第一封裝結構上，圍繞第二封裝結構且覆蓋外側導電凸塊。密封材料具有第三切割邊。電磁干擾屏蔽層接觸第一切割邊、第二切割邊與第三切割邊。電磁干擾屏蔽層電性連接於外側導電凸塊。
以下揭露內容提供用於實施所提供的標的中的不同特徵的許多不同實施例或實例。以下所描述的構件及配置的具體實例是為了以簡化的方式傳達本揭露為目的。當然，這些僅僅為實例而非用以限制。舉例來說，於以下描述中，在第一特徵上方或在第一特徵上形成第二特徵可包括第二特徵與第一特徵形成為直接接觸的實施例，且亦可包括第二特徵與第一特徵之間可形成有額外特徵使得第二特徵與第一特徵可不直接接觸的實施例。此外，本揭露在各種實例中可使用相同的元件符號及/或字母來指代相同或類似的部件。元件符號的重複使用是為了簡單及清楚起見，且並不表示所欲討論的各個實施例及/或配置本身之間的關係。
另外，為了易於描述附圖中所表示的一個構件或特徵與另一組件或特徵的關係，本文中可使用例如「在...下」、「在...下方」、「下部」、「在…上」、「在…上方」、「上部」及類似術語的空間相對術語。除了附圖中所表示的定向之外，所述空間相對術語意欲涵蓋元件在使用或操作時的不同定向。設備可被另外定向（旋轉90度或在其他定向），而本文所用的空間相對術語相應地作出解釋。
參照圖1，提供載體110並將聚合物緩衝層120形成於載體110上。在一些實施例中，載體110可為具有足夠堅硬性質或是剛性的基板，以為後續製程提供穩固的支撐。載體110可以是玻璃基板，但不以此為限。在一些實施例中，載體110可自形成其上的裝置移除而完成最終裝置，因此可在載體110上形成未表示於圖中的暫時黏著層，以在製造過程中將聚合物緩衝層120與載體110連接。暫時黏著層可由膠體材料製成，或是由包括至少一膠層與至少一聚合物層的多個層來形成。
在一些實施例中，可在聚合物緩衝層120上形成未表示於圖中的種子金屬層。形成種子金屬層的方法包括化學氣相沉積(chemical vapor deposition， CVD)、物理氣相沉積(physical vapor deposition， PVD)、原子層沉積( atomic layer deposition， ALD)、高密度電漿化學氣相沉積( high density plasma CVD， HDPCVD)法、其他合適方法、或上述方法的任何組合。接著，如圖2所示，將多個導電通孔組150形成於聚合物緩衝層120上。在一些實施例中，種子金屬層可被省略，且導電通孔組150可形成於聚合物緩衝層120上而無種子金屬層插置於聚合物緩衝層120與導電通孔組150之間。
在一些實施例中，導電通孔組150的每一者包括至少一個外側通孔152與至少一個內側通孔154。以呈現於圖2的結構為例，兩個導電通孔組150彼此相鄰設置時，其中一個導電通孔組150的外側通孔152相較於同一個導電通孔組150的內側通孔154而言，更為接近鄰近的導電通孔組150的外側通孔152。
在一些實施例中，外側通孔152與內側通孔154可通過以下舉例說明的步驟來形成，但不以此為限。在聚合物緩衝層120上形成圖案層156，且圖案層156具有多個對應於個別預定位置的開口158。在一些實施例中，圖案層156的材料可為光阻材料、光敏性材料或類似材料，且圖案層156可通過微影製程來形成，以使圖案層156具有開口158。此後，圖案層156的開口158可被填充以導電材料以形成外側通孔152與內側通孔154。舉例而言，導電材料包括鈦、鎢、鋁、銅、金屬合金、金屬矽化物、其他合適材料或是上述材料的任何組合。此外，將導電材料填充於開口158的方法包括化學氣相沉積、物理氣相沉積、原子層沉積、高密度電漿化學氣相沉積法、鍍覆法、其他合適方法或上述方法的任何組合。在一些實施例中，聚合物緩衝層120與圖案層156之間的種子金屬層可應用於鍍覆法中，例如電鍍，但不以此為限。在一些實施例中，種子金屬層的材料可包括鈦、銅或上述材料的組合。
接著，如圖3所示，移除圖案層156，而在圖案層156移除之後，外側通孔152與內側通孔154彼此相隔開。在一些實施例中，移除圖案層156的方法可包括剝除製程或是蝕刻製程。其中一個導電通孔組150的外側通孔152可與鄰近的導電通孔組150的外側通孔152以距離G1相隔開。換言之，距離G1形成於其中一個導電通孔組150的外側通孔152的外邊緣152E與鄰近的導電通孔組150的外側通孔152的外邊緣152E之間。外側通孔152與內側通孔154可具有足夠的高度H以提供垂直的電性傳導路徑。
參照圖4，使用晶粒貼合膜(die attach film)，將多個晶粒160放置於聚合物緩衝層120上並貼附於聚合物緩衝層120。在一些實施例中，晶粒貼合黏劑170可使用於晶粒160的背側。晶粒160的每一者具有多個導電接合墊162。在此描述的示例中，導電接合墊162以面朝上的方式定向。在一實施例中，晶粒160的導電接合墊162可包括銅柱(Cu post)或柱狀凸塊。晶粒160可分別為任何的積體電路且可為記憶體或應用處理器(application processor, AP)，其中應用處理器諸如微處理器、數位訊號處理器、通用處理器或是特殊應用積體電路(application specific integrated circuit， ASIC)。在一些實施例中，外側通孔152與內側通孔154個別的高度H足夠讓外側通孔152與內側通孔154的頂部超出或是等於晶粒160的頂部的高度準位。
如圖5所示，將晶粒160接附至聚合物緩衝層120後，形成模造成型化合物180以密封晶粒160與導電通孔組150。模造成型化合物180填充外側通孔152與內側通孔154之間的空間、內側通孔154之間的空間、相鄰兩導電通孔組150的外側通孔152之間的空間以及內側通孔154與晶粒160之間的空間。在一些實施中，模造成型化合物180一體的密封與包覆晶粒160及導電通孔組150。模造成型化合物180的材料可為可通過熱固化製程或是紫外光固化製程被固化的樹脂。
接續密封製程後，可於模造成型化合物180的頂部180T施行研磨製程。研磨製程移除至少一部分的模造成型化合物180。在一些實施例中，研磨製程持續進行直到外部通孔152的上表面152A的一部分、內部通孔154的上表面154A的一部份與導電接合墊162的上表面162A的一部份暴露出來。在一些實施例中，研磨製程可包括化學機械研磨(Chemical-Mechanical Planarization， CMP)、拋光製程或類似的製程。
再者，參照圖6，可於模造成型化合物180經研磨的表面上形成重佈線層190。重佈線層190可包括有諸如銅走線的至少一導體分佈於至少一個介電材料層中。在一示例中，走線192形成於絕緣層194中，且重佈線層190中的走線192可連接至外側通孔152的上表面152A、內側通孔154的上表面154A以及導電接合墊162的上表面162A。此外，走線192可提供預定的佈局以規劃出晶粒160與導電通孔組150的電性傳導路徑。
如圖6所示，多個第一封裝結構100現已形成於載體110上，且這些第一封裝結構100使用相同的模造成型化合物(例如模造成型化合物180)密封。其中一個第一封裝結構100可包括晶粒160、導電通孔組150、模造成型化合物180與重佈線層190。晶粒160與導電通孔組150被模造成型化合物180密封與圍繞。此外，外側通孔152與內側通孔154可貫穿模造成型化合物180，而導電通孔組150可將重佈線層190的一部分與後續堆疊的晶粒或元件電性連接。換言之，導電通孔組150可提供垂直電性傳輸路徑，使得重佈線層190可電性連接於另一元件。在此，另一元件諸如位於模造成型化合物180的相對側的晶粒或是其他構件。
在一些實施例中，重佈線層190的表面可接收焊錫凸塊或是其他電性連接件。舉例而言，參照圖7，形成多個底導電凸塊200於重佈線層190上，且底導電凸塊200可分別電性連接於重佈線層190的走線192。底導電凸塊200可為控制塌陷高度晶片連接件(controlled collapsing chip connectors， C4)、焊錫凸塊或是其他用以連接至外部元件的連接件。再者，既然底導電凸塊200電性連接於重佈線層190，底導電凸塊200的至少一部份可通過重佈線層190與導電通孔組150來電性連接於另一元件，像是在後續製程中要配置於模造成型化合物180相對側的晶片或是其他構件。
此後，參照圖8，圖7中所呈現的結構在此被上下顛倒定向。在圖8的步驟中，被相同的模造成型化合物180密封在一起的第一封裝結構100被接附到載體膜300而以載體膜300覆蓋這些底導電凸塊200。進行脫膠製程(debonding process)以自第一封裝結構100將載體110移除。在一實施例中，脫膠製程可包括將能量束B由載體110的一側施加至暫時黏著層(未示於圖中)。在一些實施例中，能量束B可為具有足夠能量以讓暫時黏著層的黏著性質劣化的雷射束。在其他實施例中，能量束B可提供足夠的能量以將暫時黏著層燒失。在移除載體110的製程中，覆蓋住底導電凸塊200的載體膜300可支撐第一封裝結構100且保護底導電凸塊200以避免底導電凸塊200在後續製程中受到損壞或是脫離。此外，能量束B可為點狀射束、線性射束等，而所謂的束或射束並不限於形成特定的照射面積。
參照圖9，移除載體110後，可進行背側接墊開口製程。進行背側接墊開口製程可移除至少部份的聚合物緩衝層120，其通過雷射鑽孔、乾/濕清洗或類似方式使外側通孔152與內側通孔154暴露出來。在一些實施例中，背側接墊開口製程會持續進行直到外側通孔152與內側通孔154暴露出來。此後，可進行焊錫糊漿形成製程。
外側通孔152被暴露的表面152B與內側通孔154被暴露的表面154B可接收焊錫凸塊或其他電性連接件。舉例來說，參照圖10，多個導電凸塊400形成於外側通孔152與內側通孔154上，且分別電性連接於外側通孔152與內側通孔154。導電凸塊400可為控制塌陷高度晶片連接件、焊錫凸塊或是其他用以連接至外部元件的連接件。根據配置位置，導電凸塊400可包括多個外側導電凸塊410與多個內側導電凸塊420。外側導電凸塊410電性連接於外側通孔152。此外，一個外側通孔152可電性連接於一個外側導電凸塊410與一個內側導電凸塊420。
在一些實施例中，電性連接於其中一個第一封裝結構100的外側導電凸塊410，相較於電性連接於相同第一封裝結構100的內側導電凸塊420來說，更接近於電性連接至鄰近的第一封裝結構100的外側導電凸塊410。外側導電凸塊410可採用一部分的外側導電凸塊410超出外側通孔152的外邊緣152E的方式而配置於外側通孔152上。換言之，其中一個第一封裝結構100的外側導電凸塊410與鄰近的第一封裝結構100的外側導電凸塊410之間的距離G2可小於此第一封裝結構100的外側通孔152與鄰近的第一封裝結構100的外部通孔152之間的距離G1。
如圖10所示，外側導電凸塊410在外邊緣152E附近接觸對應的外側通孔152。並且，外側導電凸塊410接觸於對應的外側通孔152的接觸面積可佔據外側通孔152的一部分頂表面。外側導電凸塊410具有的寬度WB可大於外側導電凸塊410接觸於外側通孔152的上表面152A的接觸寬度WC。在一些實施例中，外側導電凸塊410接觸於外側通孔152的接觸寬度WC可為5微米(µm)至50微米，或可為20微米。
參照圖11，可將多個第二封裝結構500分別接合至第一封裝結構100上，且形成密封材料700以密封第二封裝結構500。在一些實施例中，第二封裝結構500可通過導電凸塊600接合至第一封裝結構100。導電凸塊600可放置於形成在外側通孔152與內側通孔154上的內側導電凸塊420上，且導電凸塊600可接合於形成在外側通孔152與內側通孔154上的內側導電凸塊420上。換言之，第二封裝結構500可採用覆晶方式接合至第一封裝結構100。第二封裝結構500可為使用覆晶技術接合至第一封裝結構100的記憶體元件。在一些實施例中，記憶體元件可包括動態隨機存取記憶體(DRAM)，但不以此為限。
在一些實施例中，第二封裝結構500的其中一個包括至少一晶粒510、重佈線層520與模造成型化合物530。晶粒510可配置於重佈線層520上並與重佈線層520電性連接。模造成型化合物530可於重佈線層520上方密封晶粒510。此外，導電凸塊600可配置在第二封裝結構500中暴露出重佈線層520的底部。在一些實施例中，第二封裝結構500可不覆蓋外側導電凸塊410，使得外側導電凸塊410在第二封裝結構500接合至第一封裝結構100之後被暴露出來。可形成密封材料700來填充第一封裝結構100與第二封裝結構500之間的空間。密封材料700覆蓋外側導電凸塊410且圍繞第二封裝結構500。在一些實施例中，密封材料700在第二封裝結構500的周邊可具有斜面或是凹陷的輪廓，並作為填底膠。在其他實施例中，密封材料700的頂表面可低於第二封裝結構500的頂表面。
同時參照圖11與圖12，進行單體化製程S以形成多個疊層封裝(POP)裝置800。沿著切割軌跡來切割圖11表示的結構以進行單體化製程S。可控制切割軌跡使其路徑位於距離G2的區域內而不超出距離G1的區域。在一些實施例中，在單體化製程後，第一封裝結構100可具有第一切割邊100E，外側導電凸塊410可具有第二切割邊410E，且密封材料700可具有第三切割邊700E，使得外側導電凸塊410如圖12所示地暴露出來。此外，外側通孔152的外邊緣152E可不在第一封裝結構100的第一切割邊100E露出而保持被模造成型化合物180圍繞。換言之，第一切割邊100E為第一封裝結構100的模造成型化合物180被暴露出來的部份。
在一些實施例中，距離G3可存在於外側通孔152的外邊緣152E與第一切割邊100E之間，且模造成型化合物180填充距離G3所在區域。在單體化製程期間，外側通孔152可不被切割而維持著被模造成型化合物180覆蓋，這避免了外側通孔152被切割而導致的金屬污跡作用。在單體化製程期間，讓外側通孔152被切割的情形下，第一切割邊100E可能因為外側通孔152的金屬污跡作用而不平坦也不平順。因此，進行單體化製程並使模造成型化合物180保持於覆蓋且圍繞外側通孔152，這有助於提昇良率且提昇第一封裝結構100在第一切割邊100E的平坦性。
載體膜300可在單體化製程後移除，且接續地於單獨的疊層封裝裝置800上形成電磁干擾(electromagnetic interference， EMI)屏蔽層810。如此一來，即形成如圖13所示的經封裝半導體裝置900。電磁干擾屏蔽層810經製作成以共型方式覆蓋第一切割邊100E、第二切割邊410E、第三切割邊700E與密封材料700的頂表面700T。在一些實施例中，外側導電凸塊410在第二切割邊410E暴露出來，且電磁干擾屏蔽層810可以電性耦合於暴露出來的外側導電凸塊410。電磁干擾屏蔽層810可在使用時提供阻擋電磁干擾的功能。在一些實施例中，暴露出來的外側導電凸塊410通過對應的外側通孔152與重佈線層190連接至底導電凸塊200，以將電磁干擾屏蔽層810電性接地。
電磁干擾屏蔽層810可以電傳導性材料來製作。電磁干擾屏蔽層810的材料可包括銅、鎳、鎳鐵合金、銅鎳合金、銀等。但不以此為限。在一些實施例中，電磁干擾屏蔽層810可使用電鍍法、無電鍍法、濺鍍法、物理氣相沉積法、化學氣相沉積法、大氣環境電漿沉積法、噴塗或是其他合適的金屬沉積製程來製作。在一些實施例中，第一切割邊100E、第二切割邊410E與第三切割邊700E共同形成側邊緣800E。側邊緣800E為平坦的而無因為金屬污跡效應而產生的皺褶。形成於平坦的側邊緣800E上的電磁干擾屏蔽層810的厚度可實質上為均勻的。換言之，電磁干擾屏蔽層810可共形於側邊緣800E而提供良好的電磁干擾屏蔽效應。以導電性或磁性材料製作的屏障來阻擋電磁場，而使得電磁干擾屏蔽層810可用以降低或是屏蔽空間中的電磁場。電磁干擾屏蔽層810在一些實施例中可抑制諸如無線電波、電磁場與靜電場的耦合。
參照圖13，經封裝半導體裝置900可包括第一封裝結構100、多個底導電凸塊200、多個導電凸塊400、第二封裝結構500、多個導電凸塊600、密封材料700與電磁干擾屏蔽層810。底導電凸塊200與導電凸塊400可配置於第一封裝結構100的兩相對表面。第二封裝結構500可通過導電凸塊600接合至第一封裝結構100。導電凸塊600可連接至導電凸塊400中的內側導電凸塊420以形成多個中間導電凸塊910。在一些實施例中，密封材料700填充第一封裝結構100與第二封裝結構500之間的間隙。密封材料700可圍繞第二封裝結構500、中間導電凸塊910與導電凸塊400中的外側導電凸塊410。經封裝半導體裝置900的第一封裝結構100、外側導電凸塊410與密封材料700可具有第一切割邊100E、第二切割邊410E與第三切割邊700E。第一切割邊100E、第二切割邊410E與第三切割邊700E共同形成側邊緣800E。電磁干擾屏蔽層810覆蓋側邊緣800E與密封材料700的頂表面700T。此外，底導電凸塊200可暴露出來而不被電磁干擾屏蔽層810覆蓋。
在一些實施例中，第一封裝結構100可包括聚合物緩衝層120、多個外側通孔152、多個內側通孔154、晶粒160、模造成型化合物180與重佈線層190。模造成型化合物180可密封晶粒160，且圍繞外側通孔152與內側通孔154。外側通孔152與內側通孔154可貫穿模造成型化合物180以將導電凸塊400與重佈線層190電性連接。此外，外側通孔152的外邊緣152E可被模造成型化合物180覆蓋而不在第一切割邊100E暴露出來。
底導電凸塊200可配置於重佈線層190上且在經封裝半導體裝置900的底部900B暴露出來，以連接至外部元件。導電凸塊400可包括外側導電凸塊410與內側導電凸塊420。外側導電凸塊410配置在第一封裝結構100的周邊。內側導電凸塊420連接至導電凸塊600以將第一封裝結構100與第二封裝結構500電性連接。在一些實施例中，內側導電凸塊420連接至導電凸塊600以形成中間導電凸塊910。外側導電凸塊410可連接至外側通孔152且具有暴露出來的第二切割邊410E。在一些實施例中，一個外側通孔152的寬度WV足夠大以連接一個外側導電凸塊410與一個內側導電凸塊420。舉例而言，外部通孔152的寬度WV 可以為300微米至1200微米。在一些實施例中，外部通孔152的寬度WV可為1050微米。電磁干擾屏蔽層810可直接覆蓋於暴露出來的外部導電凸塊410上以將外側通孔152與對應的底導電凸塊200電性連接。
第二封裝結構500可以覆晶方式接合至第一封裝結構100。在一些實施例中，導電凸塊600可放置於第二封裝結構500上，並接著將第二封裝結構500上的導電凸塊600接附至第一封裝結構100上的內側導電凸塊420而形成了連接在第一封裝結構100與第二封裝結構500之間中間導電凸塊910。在一些實施例中，第一封裝結構100可大於第二封裝結構500，且第一封裝結構100上的外側導電凸塊410可不被第二封裝結構500覆蓋也不連接至第二封裝結構500。換言之，第二封裝結構500上的導電凸塊600可不接附至外側導電凸塊410。
密封材料700可密封第二封裝結構500、外側導電凸塊410與中間導電凸塊910以將第一封裝結構100與第二封裝結構500封裝在一起而建構出於封裝上封裝的疊層封裝裝置。電磁干擾屏蔽層810可以共形的方式覆蓋第一切割邊100E、第二切割邊410E、第三切割邊700E與頂表面700T，而不連接至底導電凸塊200。電磁干擾屏蔽層810可通過外側導電凸塊410電性連接於外側通孔152而不直接接觸外側通孔152。換言之，電磁干擾屏蔽層810可通過模造成型化合物180而實體上與外側通孔152隔離。
參照圖14，外側導電凸塊410可部分地接觸外側通孔152，且由外側導電凸塊410接觸於外側通孔152處向外延伸出去。外側導電凸塊410可具有寬度WP，寬度WP大於外側導電凸塊410接觸於外側通孔152的上表面152A的接觸寬度WC。一併參照圖10與圖14，外側導電凸塊410受到單體化製程後的寬度WP可實質上相同於或是小於外側導電凸塊410在單體化製程之前的寬度WB。再者，接觸寬度WC可小於寬度WP與寬度WB兩者。在一些實施例中，寬度WP相對於接觸寬度WC的比例可為大於2至1。在一些實施例中，外側導電凸塊410接觸於外側通孔152的上表面152A的接觸寬度WC可為5微米到100微米或是20微米到50微米。此外，模造成型化合物180可圍繞外側通孔152，且外側通孔152的外邊緣152E可與第一切割邊100E分離一距離G3。在一些實施例中，外側導電凸塊410可進一步覆蓋外側通孔152的外邊緣152E的一部份，使外側導電凸塊410可穩固地接觸於外側通孔152。在一些實施例中，模造成型化合物180可在外側通孔152附近具有凹陷180R，且一部分的密封材料700可填充此凹陷180R。換言之，凹陷180R可被密封材料700填充且一部分的密封材料700可填充於外側導電凸塊410與模造成型化合物180之間。
在本發明實施例中，經封裝半導體裝置包括第一封裝結構、至少一外側導電凸塊、第二封裝結構、密封材料以及電磁干擾(EMI)屏蔽層。第一封裝結構具有第一切割邊。外側導電凸塊配置於第一封裝結構上且具有第二切割邊。第二封裝結構接附於第一封裝結構上。密封材料配置於第一封裝結構上，圍繞第二封裝結構且覆蓋外側導電凸塊。密封材料具有第三切割邊。電磁干擾屏蔽層接觸第一切割邊、第二切割邊與第三切割邊。電磁干擾屏蔽層電性連接於外側導電凸塊。
在本發明實施例中，經封裝半導體裝置包括第一封裝結構、至少一外側導電凸塊、第二封裝結構、密封材料與電磁干擾屏蔽層。第一封裝結構包括晶粒、模造成型化合物與至少一外側通孔。晶粒與外側通孔被模造成型化合物密封，且外側通孔貫穿模造成型化合物。外側導電凸塊配置於第一封裝結構且連接至外側通孔。第二封裝結構接附於第一封裝結構上。密封材料配置於第一封裝結構上，圍繞第二封裝結構且覆蓋外側導電凸塊。電磁干擾屏蔽層接觸密封材料、第一封裝結構與外側導電凸塊。外側導電凸塊接觸電磁干擾屏蔽層與外側通孔。電磁干擾屏蔽層通過外側導電凸塊電性連接至外側通孔。
在本發明實施例中，經封裝半導體裝置的製作方法包括至少以下步驟。將多個外側導電凸塊分別形成在由模造成型化合物密封的多個第一封裝結構上。一個第一封裝結構上的一個外側導電凸塊與相鄰的第一封裝結構上的另一個外側導電凸塊分隔一距離。第二封裝結構接附至第一封裝結構上且第二封裝結構暴露出外側導電凸塊。使用密封材料將第二封裝結構密封在第一封裝結構上。進行單體化製程以將密封材料、外側導電凸塊與模造成型化合物切穿，以形成多個疊層封裝裝置且外側導電凸塊在疊層封裝裝置的側邊暴露出來。
在部分實施例中，第一切割邊、第二切割邊與第三切割邊形成側邊緣且電磁干擾屏蔽層以共形方式覆蓋側邊緣。第一封裝結構包括晶粒、模造成型化合物與至少一外側通孔。晶粒與外側通孔被模造成型化合物密封。外側通孔貫穿模造成型化合物且電磁干擾屏蔽層通過外側導電凸塊而電性連接外側通孔。外側通孔的外邊緣被模造成型化合物覆蓋且與第一切割邊相隔一距離。外側導電凸塊的寬度大於外側導電凸塊接觸於外側通孔的接觸寬度。將多個中間導電凸塊連接於第一封裝結構與第二封裝結構之間，其中中間導電凸塊被密封材料圍繞。外側導電通孔連接至外側導電凸塊與一個中間導電凸塊。將多個底導電凸塊配置於第一封裝結構並在經封裝半導體裝置的底部暴露出底導電凸塊。沿著不同第一封裝結構的外側導電凸塊間的距離存在處而延伸的切割路徑切割密封材料與模造成型化合物而進行單體化製程。於封裝上封裝的疊層封裝裝置，在單體化製程後，個別具有第一封裝結構的第一切割邊、外側導電凸塊的第二切割邊與密封材料的第三切割邊。第一切割邊暴露出模造成型化合物。
上述內容已描述幾個實施例的特徵使所屬技術領域中具有通常知識者更好的了解本揭露內容的觀點。所屬技術領域中具有通常知識者應領會到其可使用本揭露內容作為修改或設計其他製程與結構的基礎，以為了實現相同目的及/或達成在此引入的實施例的相同優點。任何所屬技術領域中具有通常知識者應也理解不脫離本揭露內容所述的精神和範圍內的等同架構，且在不脫離本發明實施例的精神和範圍內，當可作各式的更動、取代與替換。
100‧‧‧第一封裝結構
100E‧‧‧第一切割邊
110‧‧‧載體
120‧‧‧聚合物緩衝層
150‧‧‧導電通孔組
152‧‧‧外側通孔
152A、154A、162A‧‧‧上表面
152B、154B‧‧‧被暴露的表面
152E、154E‧‧‧外邊緣
154‧‧‧內側通孔
156‧‧‧圖案層
158‧‧‧開口
160、510‧‧‧晶粒
162‧‧‧導電接合墊
170‧‧‧晶粒貼合黏劑
180、530‧‧‧模造成型化合物
180R‧‧‧凹陷
180T‧‧‧頂部
190、520‧‧‧重佈線層
192‧‧‧走線
200‧‧‧底導電凸塊
300‧‧‧載體膜
400、600‧‧‧導電凸塊
410‧‧‧外側導電凸塊
410E‧‧‧第二切割邊
420‧‧‧內側導電凸塊
500‧‧‧第二封裝結構
700‧‧‧密封材料
700E‧‧‧第三切割邊
700T‧‧‧頂表面
800‧‧‧疊層封裝裝置
800E‧‧‧側邊緣
810‧‧‧電磁干擾屏蔽層
900‧‧‧經封裝半導體裝置
900B‧‧‧底部
910‧‧‧中間導電凸塊
B‧‧‧能量束
G1、G2、G3‧‧‧距離
H‧‧‧高度
S‧‧‧單體化製程
WB、WP、WV‧‧‧寬度
WC‧‧‧接觸寬度
由以下詳細說明伴隨所附圖式以了解本揭露的觀點。依據本產業的標準實務，各式特徵並非以等比例表示。實際上，為了論述的明確性，各式特徵的尺寸可人為地增加或縮小。 圖1為依據部分實施例的製作經封裝半導體裝置的方法而示意性表示的形成聚合物緩衝層的步驟。 圖2與圖3為依據部分實施例的製作經封裝半導體裝置的方法而示意性表示的形成通孔的步驟。 圖4為依據部分實施例的製作經封裝半導體裝置的方法而示意性表示的晶粒接合步驟。 圖5為依據部分實施例的製作經封裝半導體裝置的方法而示意性表示的形成封裝結構的步驟。 圖6為依據部分實施例的製作經封裝半導體裝置的方法而示意性表示的於封裝結構上形成重佈線層的步驟。 圖7為依據部分實施例的製作經封裝半導體裝置的方法而示意性表示的形成導電凸塊的步驟。 圖8與9為依據部分實施例的製作經封裝半導體裝置的方法而示意性表示的移除載體的步驟。 圖10為依據部分實施例的製作經封裝半導體裝置的方法而示意性表示的形成導電凸塊的步驟。 圖11為依據部分實施例的製作經封裝半導體裝置的方法而示意性表示的於封裝結構上接附封裝結構的步驟。 圖12為依據部分實施例的製作經封裝半導體裝置的方法而示意性表示的單體化製程的步驟。 圖13示意性地表示依據部分實施例的經封裝半導體裝置。 圖14為部分實施例的經封裝半導體裝置的局部放大示意圖。
100‧‧‧第一封裝結構
100E‧‧‧第一切割邊
120‧‧‧聚合物緩衝層
152‧‧‧外側通孔
154‧‧‧內側通孔
160‧‧‧晶粒
180‧‧‧模造成型化合物
190‧‧‧重佈線層
200‧‧‧底導電凸塊
400‧‧‧導電凸塊
410‧‧‧外側導電凸塊
410E‧‧‧第二切割邊
420‧‧‧內側導電凸塊
500‧‧‧第二封裝結構
600‧‧‧導電凸塊
700‧‧‧密封材料
700E‧‧‧第三切割邊
700T‧‧‧頂表面
800E‧‧‧側邊緣
810‧‧‧電磁干擾屏蔽層
900‧‧‧經封裝半導體裝置
900B‧‧‧底部
910‧‧‧中間導電凸塊
WV‧‧‧寬度

Claims (1)

  1. 一種經封裝半導體裝置，包括： 第一封裝結構，其具有第一切割邊； 至少一外側導電凸塊，配置於所述第一封裝結構上且具有第二切割邊； 第二封裝結構，接附於所述第一封裝結構上； 密封材料，配置於所述第一封裝結構上，圍繞所述第二封裝結構，且覆蓋所述外側導電凸塊，其中所述密封材料具有第三切割邊；以及 電磁干擾屏蔽層，配置於所述第一切割邊、所述第二切割邊與所述第三切割邊上，且電性連接所述外側導電凸塊。
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