CN107452789A - 用于器件制造的改进布局 - Google Patents

用于器件制造的改进布局 Download PDF

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CN107452789A
CN107452789A CN201710303374.4A CN201710303374A CN107452789A CN 107452789 A CN107452789 A CN 107452789A CN 201710303374 A CN201710303374 A CN 201710303374A CN 107452789 A CN107452789 A CN 107452789A
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史蒂文·托马斯·皮克
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Abstract

本发明披露了一种器件以及制造器件的方法。该器件包括：半导体基板；多个源极线，其形成在半导体基板的表面上。多个源极线沿X方向和Y方向这两个方向布置。该器件还包括：多个栅极线，其布置在多个源极线中的在X方向上的源极线上方；源极接点线，其与多个源极线中的在Y方向上终止的源极线连接；栅极接点线，其与多个栅极线连接；以及漏极接点。

Description

用于器件制造的改进布局
背景技术
沟槽栅极技术常用于改进半导体器件(特别是高压器件)中的击穿电压特性。在沟槽栅极技术中，栅极被竖直地埋在源极中，且通常通过隔离罩隔开。沟槽栅极技术的其它优势包括减小可能至少在一些应用中是不期望的结型栅场效应晶体管(JFET)影响。然而，在想要低压构造时，由于需要减小嵌入式栅极的宽度，沟槽栅极技术确实会带来一些劣势。
发明内容
本发明内容用于以简化的形式介绍将在下文具体实施方式中进一步描述的构思的选择。本发明内容不意在确认所要求保护的主题的关键特征或必要特征，也不意在用来限制所要求保护的主题的范围。
在一个实施例中，披露了一种器件。该器件包括：半导体基板；多个源极线，其形成在所述半导体基板的表面上。所述多个源极线沿X方向和Y方向这两个方向布置。所述器件还包括：多个栅极线，其布置在所述多个源极线中的在X方向上的源极线上方；源极接点线，其与所述多个源极线中的在Y方向上终止的源极线连接；栅极接点线，其与所述多个栅极线连接；以及漏极接点。
在一些实施例中，所述半导体基板的表面包括：外延层，其中，所述外延层的顶表面包括p型主体植入物。n型层沿所述多个源极线中的在Y方向上的源极线延伸。所述栅极线从所述半导体基板的表面突出。源极层与栅极层之间存在隔离层。所述隔离层仅在X方向上存在。所述多个源极线中的各个源极线之间的距离是基于器件的期望电特性而由用户限定的。第二隔离层被埋在沟槽中以覆盖所述多个源极线的被埋部分。
在另一实施例中，披露了制造器件的方法。所述方法包括：在晶圆的顶表面中形成外延层；在所述外延层的顶表面中形成主体层；仅在Y方向上形成多个源极植入条；形成包括X方向和Y方向上的沟槽的沟槽交叉网(网状物)。Y方向上的沟槽穿过(切穿)所述多个源极植入条中的每一个。所述方法还包括：用介电材料填充所述沟槽交叉网中的沟槽；在所述介电材料中形成源极沟槽；用源极多晶硅填充所述源极沟槽；在所述源极沟槽中形成栅极沟槽；以及用栅极多晶硅填充所述栅极沟槽，使得所述栅极多晶硅的一部分突出到所述晶圆的顶表面上方。
在一些实施例中，在用栅极多晶硅填充所述栅极沟槽之前，将隔离沟槽形成在所述源极沟槽中并且用隔离材料填充所述隔离沟槽。形成源极沟槽的方法包括：形成用于形成源极接点条的源极接点沟槽。形成栅极沟槽包括：形成用于形成栅极接点条的栅极接点沟槽。
附图说明
以可以详细理解本发明的上述特征的方式，通过参考实施例可以对本发明作更具体的描述(在上文被简单地概括)，这些实施例中的一些在附图中示出。然而，应注意，附图仅示出本发明的典型实施例，并且由于本发明可以允许其它等效实施例，因此附图不被认为是对本发明范围的限制。在结合附图阅读该描述的基础上，对于本领域的技术人员来说所要求保护的主题的优势将变得显而易见，在附图中，相同的附图标记被用于代表相同的元件，并且其中：
图1描绘了根据本发明的一个或多个实施例的器件的截面的示意图，该示意图示出了沉积在位于X方向和Y方向这两个方向上的沟槽中的隔离材料；
图2示出了根据本发明的一个或多个实施例的沉积在隔离层中的沟槽中的源极层；
图3描绘了根据本发明的一个或多个实施例的在X方向上的刻蚀的隔离层和源极层；
图4描绘了根据本发明的一个或多个实施例的沿X方向形成在源极层上方的栅极层；以及
图5描绘了根据一个或多个实施例的器件的俯视图，该俯视图示出了栅极和源极的构型以及栅极和源极的接点。
应该注意到，附图未按比例绘制。已省略了附图转换之间的中间步骤，以免混淆本发明。这些中间步骤是本领域技术人员已知的。
具体实施方式
应注意，本文中所描述的实施例使用n沟道器件仅出于举例的目的。本领域技术人员应认识到，这些实施例还可以应用于p沟道器件。已将许多已知的制造步骤、组件和连接器从描述中省略，以免混淆本发明。
图1描绘了处于初始制造阶段的器件的截面的示意图。晶圆100掺杂有n型植入物。晶圆100的上表面上植入有n型或n+型外延层102。应注意，附图中示出的各个层的深度未按比例绘制。外延层102的上表面上植入有p型主体区域104。然后，根据期望的源极间距沿Y方向以等间隔植入n型条106，在本文中稍后讨论n型条106的重要性。
然后，刻蚀沟槽的截面图案。Y方向上的沟槽与n型层106重叠。为了易于描述，仅示出沟槽图案的一部分。实际上，沟槽网将呈现为如图5中的平面图所示的那样。在一个实施例中，沟槽壁上沉积有介电材料。在另一实施例中，沟槽填充有介电材料108。如果整个沟槽填充有介电材料，则将需要对介电材料的一部分进行刻蚀以生成用于源极层的沟槽。如先前提到的，用于执行以上步骤(例如，植入杂质、刻蚀沟槽等)的方法是本领域已知的。如果介电材料108沉积在沟槽的壁上或者如果在用介电材料108填充第一组沟槽之后刻蚀第二组沟槽，则根据期望的漏极特性介电层108的厚度通常在100nm与600nm之间。
应注意，可以在晶圆100上重复形成图案，并且在本文所描述的处理完成之后，可以切下并封装单个分立器件。封装包括形成金属接点。在一些实施例中并且仅用于举例，沟槽宽度对于100v器件可以是6微米并且对于50v器件可以是4.5微米。
图2示出了沉积在沟槽中的源极层110。如上所述，介电材料108可以沉积在图1所描述的沟槽的壁上。作为选择，当用介电材料108填充第一沟槽时在介电层108中刻蚀沟槽。这些新的沟槽具有比介电层108的宽度小的宽度和深度，使得在沟槽壁与主体区域层104以及沟槽壁与外延层102之间留有所需量的介电质。在这些沟槽中，沉积有n型多晶硅层(源极层)110。在沉积了源极层110之后，可以执行化学机械平坦化(CMP)以使顶表面变得平坦。
图3描绘了在X方向上的一组新的沟槽109。在上述CMP处理后，将光致抗蚀剂沉积在表面的上方，使得源极层110和相邻的氧化物介电层108仅沿X方向露出。然后，如图所示，执行刻蚀以基于正被形成的器件的期望电特性沿X方向将介电层108和源极层110刻蚀到期望的深度。在仅沿X方向形成这些沟槽109之后，执行栅极氧化处理以沿X方向在沟槽的底部和壁上沉积薄的介电层113(图4)。
在将介电层113沉积在源极层110上方的沿X方向的这些沟槽的壁和底部上之后，通过在这些沟槽中沉积n型多晶硅形成栅极层112。可以在形成栅极层112之后执行CMP处理。随后，可以形成用于源极、漏极和栅极的顶部隔离层和接点(未示出)。
图5描绘了从晶圆100切下的器件的俯视图，该俯视图示出了栅极线112和源极线110以及栅极接点124和源极接点126。如相对于图3所描述的，用于源极接点线126的沟槽与源极层110的构型一起形成，并且栅极接点线124与形成有栅极层112的沟槽一起形成。源极接点线126用于附接源极金属接点，并且栅极接点线124用于附接栅极金属接点。漏极接点附接在晶圆100上。如所描绘的，源极接点线126在Y方向上连接至源极层110，并且栅极接点线124在X方向上连接至栅极层112。虽然未在图5中示出，但应注意，源极层110还位于栅极层112下方。此外，如所描绘的，源极层110包括沿X方向和Y方向这两个方向布置的源极线，其中，X方向上的源极线与Y方向上的源极线交叉。X方向上的源极线与栅极层112的栅极线重叠。在一些实施例中，不是所有X方向上的源极线都可以与栅极线重叠。
为了改变器件的电特性，可以改变栅极间距120和源极间距122。利用这种方形布局方案，可以大大提高击穿电压(BVdss)。当栅极间距120大于源极间距122时，可以优化器件的动态性能。因此，栅漏电荷(Qgd)可以小于栅源电荷(Qgs)。使Qgd<<<Qgs能够改进栅极跳动(gate bounce)和尖峰性能(spiking performance)。可以使用本文所提供的布局简单地通过改变栅极间距和源极间距来根据应用类型容易地改变器件的开关性能。由于对于较高电压而言沟道电阻小于顶部沟槽与底部沟槽之间的距离(外延电阻)，因此由于减小的栅极多晶硅的密度和最小的器件的状态电阻(Rdson，导通电阻)的影响可以改进动态性能。
这些实施例中的一些或全部可以组合，一些可以完全省略，并且在仍能实现在本文中所描述的产品的同时可以添加额外的处理步骤。因此，可以以许多不同的变型来实现在本文中所描述的主题，并且所有这些变型都被认为在所要求保护的范围内。
尽管通过举例的方式已描述了一个或多个实施方式，但就具体实施例而言，应当理解的是，一个或多个实施方式不限于所披露的实施例。相反，希望涵盖对本领域的技术人员显而易见的各种修改和类似的布置。因此，所附权利要求的范围应被赋予最宽泛的解释，从而包含全部这种修改和类似的布置。
除非在本文中另有说明或与上下文明显矛盾，否则在描述本主题的上下文中(具体地，在以下权利要求的上下文中)使用术语“一个”和“一种”和“这种”以及类似的表达应被解释为涵盖单数和复数。除非在本文中另有说明，否则本文中的值的范围的表述仅意在用作单独地表示落在该范围内的每个单个值的简写方法，并且每个单个值如同其在本文中被单独表述一样被并入本说明书中。此外，前述描述仅意在说明的目的，而并非意在限制，这是因为在下文中所列举的权利要求及其有权享有的任何等同内容限定了所寻求的保护范围。除非在本文中另有说明，否则在本文中提供的任何或全部实例或示例性语言(例如，“诸如……等”)的使用仅意在更好地说明本主题，而不是意在限制本主题的范围。在权利要求中和书面说明中术语“基于”以及表示导致结果的条件的其它类似短语的使用，不意在排除导致该结果的任何其它条件。说明书中的所有语言都不应解释为将任何非要求保护的元件表示为对于要求保护的本发明的实施是必不可少的。
在本文中描述了优选实施例，这些优选实施例包括发明人已知的用于实施所要求保护的主题的最好模式。当然，在阅读前述描述的基础上，对于本领域的普通技术人员来说这些优选实施例的变型将变得显而易见。发明人期望技术人员适当地采用这种变型，并且发明人意图以不同于在本文中具体描述的方式实施所要求保护的主题。因此，该要求保护的主题包括：如适用法律所容许的在主题所附权利要求中表述的主题的全部修改和等同内容。此外，除非在本文中另有说明或与上下文明显矛盾，否则包括上述元件的所有可能变型的任何组合。

Claims (13)

1.一种器件，包括：
半导体基板；
多个源极线，其形成在所述半导体基板的表面上，其中，所述多个源极线沿X方向和Y方向这两个方向布置；
多个栅极线，其布置在所述多个源极线中的在X方向上的源极线上方；
源极接点线，其与所述多个源极线中的在Y方向上终止的源极线连接；
栅极接点线，其与所述多个栅极线连接；以及
漏极接点。
2.根据权利要求1所述的器件，其中，所述半导体基板的表面包括外延层。
3.根据权利要求2所述的器件，其中，所述外延层的顶表面包括p型主体植入物。
4.根据权利要求1所述的器件，其中，n型层沿所述多个源极线中的在Y方向上的源极线延伸。
5.根据权利要求1所述的器件，其中，所述栅极线从所述半导体基板的表面突出。
6.根据权利要求1所述的器件，还包括源极层与栅极层之间的隔离层。
7.根据权利要求6所述的器件，其中，所述隔离层仅在X方向上存在。
8.根据权利要求1所述的器件，其中，所述多个源极线中的各个源极线之间的距离是基于所述器件的期望电特性而由用户限定的。
9.根据权利要求1所述的器件，还包括埋在沟槽中以覆盖所述多个源极线的被埋部分的隔离层。
10.一种制造器件的方法，所述方法包括：
在晶圆的顶表面中形成外延层；
在所述外延层的顶表面中形成主体层；
仅在Y方向上形成多个源极植入条；
形成包括X方向和Y方向上的沟槽的沟槽交叉网，其中，Y方向上的沟槽穿过所述多个源极植入条中的每一个；
将介电材料沉积在所述沟槽交叉网中的沟槽的壁上；
用源极多晶硅填充所述沟槽交叉网中的沟槽；
仅在X方向上的源极沟槽中形成栅极沟槽；以及
用栅极多晶硅填充所述栅极沟槽，使得所述栅极多晶硅的一部分突出到所述晶圆的顶表面上方。
11.根据权利要求10所述的方法，其中，在用栅极多晶硅填充所述栅极沟槽之前，将介电材料沉积到所述栅极沟槽的壁上。
12.根据权利要求10所述的方法，其中，形成源极沟槽包括：形成用于形成源极接点条的源极接点沟槽。
13.根据权利要求10所述的方法，其中，形成栅极沟槽包括：形成用于形成栅极接点条的栅极接点沟槽。
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