CN107359161B - 半导体器件 - Google Patents

半导体器件 Download PDF

Info

Publication number
CN107359161B
CN107359161B CN201710271669.8A CN201710271669A CN107359161B CN 107359161 B CN107359161 B CN 107359161B CN 201710271669 A CN201710271669 A CN 201710271669A CN 107359161 B CN107359161 B CN 107359161B
Authority
CN
China
Prior art keywords
ground potential
potential line
disposed
circuit
analog
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710271669.8A
Other languages
English (en)
Other versions
CN107359161A (zh
Inventor
森下泰之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Publication of CN107359161A publication Critical patent/CN107359161A/zh
Application granted granted Critical
Publication of CN107359161B publication Critical patent/CN107359161B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/044—Physical layout, materials not provided for elsewhere
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region

Abstract

提供一种可以具有抗噪声性和抗ESD性二者的半导体器件。该半导体器件包括：第一数字电路和第二数字电路；分别对应于第一数字电路和第二数字电路设置的第一接地电位线和第二接地电位线；第一模拟电路和第二模拟电路；分别对应于第一模拟电路和第二模拟电路设置的第三接地电位线和第四接地电位线；第一双向二极管组，设置在第一接地电位线和第二接地电位线之间；第二双向二极管组，设置在第三地电位线和第四地电位线之间；和第三双向二极管组，设置在第一接地电位线和第三接地电位线之间。第三双向二极管组中的双向二极管的级数大于包括在第一双向二极管组和第二双向二极管组中的每个双向二极管组中的双向二极管的级数。

Description

半导体器件
相关申请的交叉引用
于2016年5月10日提交的日本专利申请No.2016-094296的全部内容，包括说明书、附图和摘要，通过引用合并于本文中。
技术领域
本公开涉及一种半导体器件，特别涉及ESD(静电放电)保护。
背景技术
在半导体器件中，设置静电保护元件以防止内部电路被静电破坏。例如，由二极管、晶闸管(SCR：硅控整流器)等形成的静电保护元件耦合在提供电源电位的布线(电源电位线)和提供接地电位的布线(接地电位线)之间。当在电源电位线和接地电位线之间施加静电时，静电通过静电保护元件放电，并且不会对内部电路施加过大的电压，从而可以防止内部电路被损坏。
此外，在电源系统分离的半导体器件中，接地电位线也被分成多个系统，并且预定数量的二极管可以反并联耦合在分开的接地电位线之间。
在这方面，日本未审查专利申请公开No.2010-80472公开了一种配置，其中在分开的接地电位线之间设置双向二极管以确保放电路径。
发明内容
另一方面，关于噪声传播，仅确保其数量对应于二极管的级数的电位势垒，从而优选地提供多级二极管以改善抗噪声性。
然而，当均匀布置多级二极管时，放电路径的阻抗增加，从而容易发生内部电路的电压击穿。因此，需要针对内部电路的ESD保护措施。在这方面，存在需要ESD保护措施的内部电路的大量节点，因此芯片设计验证需要很多时间。此外，芯片面积可能变大。
本公开内容旨在解决上述问题，并且本公开的目的是提供可以具有抗噪声性和抗ESD性二者的半导体器件。
从本说明书和附图的描述中，其他目的和新颖特征将变得显而易见。
根据实施例，一种半导体器件包括：第一数字电路和第二数字电路；分别对应于第一数字电路和第二数字电路设置的第一接地电位线和第二接地电位线；第一模拟电路和第二模拟电路；分别对应于第一模拟电路和第二模拟电路设置的第三接地电位线和第四接地电位线；第一双向二极管组，设置在第一接地电位线和第二接地电位线之间；第二双向二极管组，设置在第三地电位线和第四地电位线之间；和第三双向二极管组，设置在第一接地电位线和第三接地电位线之间。第三双向二极管组中的双向二极管的级数大于包括在第一双向二极管组和第二双向二极管组中的每个双向二极管组中的双向二极管的级数。
根据实施例，可以实现抗噪声性和抗ESD性二者。
附图说明
图1是用于解释根据实施例的整个半导体器件1的示图。
图2是用于解释根据实施例的半导体器件1的接地电位线的配置的示图。
图3是示出根据实施例的每个电路区域的配置的构思的示图。
图4是示出根据实施例的改型例子1的每个电路区域的配置的构思的示图。
图5是示出根据实施例的改型例子2的每个电路区域的配置的构思的示图。
具体实施方式
将参照附图详细描述实施例。在附图中对相同或对应的部分赋予相同的附图标记，并且不再重复其描述。在实施例中，半导体器件表示以下中的任一个：形成为使得集成电子电路的半导体晶片、通过将半导体晶片分割成单片而形成的每个半导体芯片、以及通过树脂等封装单个或多个半导体芯片的器件。
图1是用于解释根据实施例的整个半导体器件1的示图。
如图1所示，半导体器件1包括设置在外周区域中的输入/输出电路(IO)区域2、布置在内部区域中并形成为具有预定功能的ASIC(专用集成电路)的核心逻辑区域3、以及设置在IO区域2外部的焊盘5。
在IO区域2中，设置作为信号的输入/输出接口的电路。在本示例中，分别设置模拟IO电路和数字IO电路。
另外，在核心逻辑区域3中也分别提供了模拟系统和数字系统。在本示例中，分别提供模拟核心电路和数字核心电路。
图2是用于解释根据实施例的半导体器件1的接地电位线的配置的示图。
如图2所示，接地电位线被独立地设置在每个区域中。
在本示例中，关于核心逻辑区域3，示出了其中设置数字核心电路的数字核心电路区域6和其中设置模拟核心电路的模拟核心电路区域8。
此外，关于IO区域2，示出了其中设置数字IO电路的数字IO电路区域7和其中设置模拟IO电路的模拟IO电路区域9。
示出了其中数字核心电路区域6被设置有用于向数字核心电路提供接地电压的多个接地电位线DVSS1的情况。
示出了其中模拟核心电路区域8被设置有用于将接地电压提供给模拟核心电路的多个接地电位线AVSS1的情况。
示出了其中数字IO电路区域7被设置有用于向数字IO电路提供接地电压的多个接地电位线DVSS2的情况。
示出了其中模拟IO电路区域9被设置有用于将接地电压提供给模拟IO核心电路的多个接地电位线AVSS2的情况。
在彼此分离的一组接地电位线和一组接地电位线之间设置一个双向二极管元件或多个双向二极管元件。
在本示例中，一级双向二极管元件10被设置在都是数字系统的接地电位线DVSS1和接地电位线DVSS2之间。
此外，一级双向二极管元件13被设置在都是模拟系统的接地电位线AVSS1和接地电位线AVSS2之间。
另一方面，当耦合数字系统和模拟系统时，设置两级双向二极管元件。例如，在接地电位线AVSS1和接地电位线DVSS1之间设置两级双向二极管元件14和15。此外，在接地电位线AVSS2和接地电位线DVSS2之间设置两级双向二极管元件11和12。
图3是示出根据实施例的每个电路区域的配置的构思的示图。
如图3所示，作为示例，数字IO电路区域7被设置有接收输入信号并进行操作的两级反相器。
作为示例，设置P沟道MOS晶体管PT1和PT2以及N沟道MOS晶体管NT1和NT2。
P沟道MOS晶体管PT1和N沟道MOS晶体管NT1被设置在电源电位线DVDD2和接地电位线DVSS2之间，并接收输入信号的输入。P沟道MOS晶体管PT2和N沟道MOS晶体管NT2设置在电源电位线DVDD2和接地电位线DVSS2之间，并且接收P沟道MOS晶体管PT1和N沟道MOS晶体管NT1的耦合节点的输入。
示出了其他电路区域被设置有相同反相器的情况。
在本示例中，需要在彼此独立的接地电位线之间设置放电路径，从而设置双向二极管元件。例如，在接地电位线DVSS1和接地电位线DVSS2之间设置双向二极管元件10。
另一方面，当容易产生噪声的数字电路靠近易受噪声影响的模拟电路而设置时，如果设置了相同级数的双向二极管元件，则抗噪声性可能不足。
因此，在本示例中，在数字核心电路区域6中设置的接地电位线DVSS1和设置在模拟核心电路区域8中的接地电位线AVSS1之间设置两级双向二极管元件14和15。
换句话说，设置在数字系统电路和模拟系统电路之间的双向二极管元件的级数大于在数字系统电路和数字系统电路之间或者在模拟系统电路和模拟系统电路之间设置的双向二极管元件的级数。尽管图3中未示出，但在设置在数字IO电路区域7中的接地电位线DVSS2与设置在模拟IO电路区域9中的接地电位线AVSS2之间提供两级双向二极管元件11和12。
通过上述配置，可以在增加数字系统电路和模拟系统电路之间的抗噪声性的同时确保抗ESD性。
此外，在数字系统电路和模拟系统电路之间设置多级双向二极管元件，使得可以容易地知道放电路径中阻抗增加的部分，并且容易进行芯片设计验证。也可以抑制芯片的面积的增加。
此外，可以提高用于CDM(带电器件模型)测试的抗ESD性。
(改型示例1)
图4是示出根据实施例的改型例子1的每个电路区域的配置的构思的示图。
如图4所示，该配置与图3的配置的不同在于提供箝位电路。
具体而言，不同之处在于，将用于防止ESD损坏的N沟道MOS晶体管50提供到反相器的输入栅极，作为箝位电路。
N沟道MOS晶体管50被设置在输入栅极和接地电位线AVSS1之间，并且N沟道MOS晶体管50的栅极被耦合到接地电位线AVSS1。
通过这种配置，向其中放电路径的阻抗增加并且可能发生电压击穿的部分提供箝位电路。因此，可以进一步提高抗ESD性。
(改型示例2)
图5是示出根据实施例的改型例子2的每个电路区域的配置的构思的示图。
如图5所示，该配置与图3的配置的不同之处在于提供多个箝位电路。
具体地，不同之处在于，用于防止ESD损坏的N沟道MOS晶体管50、51和52被提供至可能发生电压击穿的反相器的输入栅极作为箝位电路。
N沟道MOS晶体管51被设置在输入栅极和接地电位线AVSS2之间，并且N沟道MOS晶体管51的栅极被耦合到接地电位线AVSS2。
N沟道MOS晶体管52被设置在输入栅极和接地电位线DVSS1之间，并且N沟道MOS晶体管52的栅极被耦合到接地电位线DVSS1。
N沟道MOS晶体管50被设置在输入栅极和接地电位线AVSS1之间，并且N沟道MOS晶体管50的栅极被耦合到接地电位线AVSS1。
在这种配置中，箝位电路被提供给每个电路的输入栅极。由此，能够进一步提高抗ESD性。
此外，在本示例中，N沟道MOS晶体管50的元件尺寸可以从其他N沟道MOS晶体管51和52的元件尺寸改变。
可以通过将N沟道MOS晶体管50的元件尺寸增加到大于其它N沟道MOS晶体管51和52的元件尺寸来进一步提高抗ESD性。
虽然已经基于实施例具体描述了本公开，但是不用说，本公开不限于实施例，并且可以在不脱离本公开的范围的情况下进行各种修改。

Claims (5)

1.一种半导体器件，包括：
第一数字电路和第二数字电路；
分别对应于所述第一数字电路和所述第二数字电路设置的第一接地电位线和第二接地电位线；
第一模拟电路和第二模拟电路；
分别对应于所述第一模拟电路和所述第二模拟电路设置的第三接地电位线和第四接地电位线；
第一双向二极管组，设置在所述第一接地电位线和所述第二接地电位线之间；
第二双向二极管组，设置在所述第三接地电位线和所述第四接地电位线之间；和
第三双向二极管组，设置在所述第一接地电位线和所述第三接地电位线之间，
其中所述第三双向二极管组中的双向二极管的级数大于包括在所述第一双向二极管组和所述第二双向二极管组中的每个双向二极管组中的双向二极管的级数,
其中所述第一模拟电路还包括包含输入栅极的第一晶体管元件和设置在所述输入栅极与所述第三接地电位线之间的第一箝位元件，
其中所述第二模拟电路还包括包含输入栅极的第二晶体管元件和设置在所述输入栅极与所述第四接地电位线之间的第二箝位元件，以及
其中所述第一箝位元件的尺寸大于所述第二箝位元件的尺寸。
2.根据权利要求1所述的半导体器件，
其中所述第一双向二极管组和所述第二双向二极管组由一级形成，并且所述第三双向二极管组由两级或更多级形成。
3.根据权利要求1所述的半导体器件，
其中所述第一双向二极管组被设置在其中设置所述第一数字电路的数字核心区域与其中设置所述第二数字电路的数字输入/输出区域之间，
其中所述第二双向二极管组被设置在其中设置所述第一模拟电路的模拟核心区域与其中设置所述第二数字电路的模拟输入/输出区域之间，以及
其中所述第三双向二极管组被设置在所述数字核心区域与所述模拟核心区域之间。
4.根据权利要求3所述的半导体器件，还包括：
第四双向二极管组，所述第四双向二极管组被设置在所述第二接地电位线和所述第四接地电位线之间并具有双向二极管级，其级数大于包括在所述第一双向二极管组和所述第二双向二极管组中的每个双向二极管组中的双向二极管的级数，
其中所述第四双向二极管组被设置在所述数字输入/输出区域与所述模拟输入/输出区域之间。
5.根据权利要求1所述的半导体器件，
其中所述第一箝位元件耦合在所述输入栅极和所述第三接地电位线之间，并且所述第一箝位元件的栅极由与所述第三接地电位线耦合的N沟道MOS晶体管形成。
CN201710271669.8A 2016-05-10 2017-04-24 半导体器件 Active CN107359161B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2016094296A JP6595948B2 (ja) 2016-05-10 2016-05-10 半導体装置
JP2016-094296 2016-05-10

Publications (2)

Publication Number Publication Date
CN107359161A CN107359161A (zh) 2017-11-17
CN107359161B true CN107359161B (zh) 2023-06-23

Family

ID=60271519

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710271669.8A Active CN107359161B (zh) 2016-05-10 2017-04-24 半导体器件

Country Status (5)

Country Link
US (2) US10424920B2 (zh)
JP (1) JP6595948B2 (zh)
KR (1) KR20170126797A (zh)
CN (1) CN107359161B (zh)
TW (1) TW201806125A (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117254682B (zh) * 2023-11-20 2024-03-12 成都芯翼科技有限公司 一种抗干扰电压转换电路

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1525565A (zh) * 2003-02-27 2004-09-01 恩益禧电子股份有限公司 半导体集成器件及用于设计该半导体集成器件的设备
JP2010080472A (ja) * 2008-09-24 2010-04-08 Seiko Epson Corp 半導体装置
CN102208407A (zh) * 2010-03-31 2011-10-05 上海宏力半导体制造有限公司 复合电源电路以及双向晶闸管

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5616943A (en) * 1993-09-29 1997-04-01 At&T Global Information Solutions Company Electrostatic discharge protection system for mixed voltage application specific integrated circuit design
US6075686A (en) * 1997-07-09 2000-06-13 Industrial Technology Research Institute ESD protection circuit for mixed mode integrated circuits with separated power pins
US5991135A (en) * 1998-05-11 1999-11-23 Vlsi Technology, Inc. System including ESD protection
JP2001185686A (ja) * 1999-12-24 2001-07-06 Seiko Epson Corp 半導体集積装置
JP2006319267A (ja) * 2005-05-16 2006-11-24 Sanyo Electric Co Ltd 半導体集積回路
US7649214B2 (en) * 2005-10-17 2010-01-19 Taiwan Semiconductor Manufacturing Co., Ltd. ESD protection system for multiple-domain integrated circuits
JP2011096879A (ja) * 2009-10-30 2011-05-12 Panasonic Corp 半導体集積回路
JP5719126B2 (ja) * 2010-06-16 2015-05-13 ルネサスエレクトロニクス株式会社 内部回路と静電保護回路を具備する半導体集積回路
JP2013030573A (ja) * 2011-07-28 2013-02-07 Elpida Memory Inc 半導体装置
EP3054481A1 (en) * 2015-02-04 2016-08-10 Nxp B.V. Semiconductor device comprising an ESD protection circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1525565A (zh) * 2003-02-27 2004-09-01 恩益禧电子股份有限公司 半导体集成器件及用于设计该半导体集成器件的设备
JP2010080472A (ja) * 2008-09-24 2010-04-08 Seiko Epson Corp 半導体装置
CN102208407A (zh) * 2010-03-31 2011-10-05 上海宏力半导体制造有限公司 复合电源电路以及双向晶闸管

Also Published As

Publication number Publication date
CN107359161A (zh) 2017-11-17
US10424920B2 (en) 2019-09-24
KR20170126797A (ko) 2017-11-20
JP2017204516A (ja) 2017-11-16
JP6595948B2 (ja) 2019-10-23
US11201465B2 (en) 2021-12-14
TW201806125A (zh) 2018-02-16
US20190348835A1 (en) 2019-11-14
US20170331284A1 (en) 2017-11-16

Similar Documents

Publication Publication Date Title
US7420789B2 (en) ESD protection system for multi-power domain circuitry
US8830640B2 (en) Electrostatic discharge protection circuit
US8749932B2 (en) Semiconductor device with a plurality of power supply systems
US9013843B2 (en) Multiple device voltage electrostatic discharge clamp
KR101039856B1 (ko) 정전기 방전 회로
US20100246074A1 (en) ESD Protection scheme for designs with positive, negative, and ground rails
US20080080107A1 (en) ESD protection for integrated circuits with multiple power domains
TW202008676A (zh) 積體電路的靜電放電防護裝置
JP2009147040A (ja) 半導体集積回路装置
US7417837B2 (en) ESD protection system for multi-power domain circuitry
CN107359161B (zh) 半导体器件
US10361557B2 (en) Semiconductor device
US7362555B2 (en) ESD protection circuit for a mixed-voltage semiconductor device
US20080165459A1 (en) Pad ESD Spreading Technique
KR100631957B1 (ko) 정전기 방전 보호 회로
US7538996B2 (en) Circuit with protection against electrostatic destruction
JPH03234063A (ja) 半導体集積回路
KR100735629B1 (ko) 디지털/아날로그 혼합 모드 ｉｃ의 정전기 방전 보호 회로
JP5819489B2 (ja) 半導体装置
KR20080111670A (ko) 정전기 방전 보호 회로 및 이를 포함하는 반도체 장치
JP6536274B2 (ja) 半導体装置
JP5337173B2 (ja) 半導体装置
JP2006093598A (ja) 半導体集積回路
KR20120039192A (ko) 반도체 장치
KR100876894B1 (ko) 반도체 장치의 내부 회로 보호 장치

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant