CN107331745A - A kind of epitaxial wafer of light emitting diode and preparation method thereof - Google Patents
A kind of epitaxial wafer of light emitting diode and preparation method thereof Download PDFInfo
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- CN107331745A CN107331745A CN201710400369.5A CN201710400369A CN107331745A CN 107331745 A CN107331745 A CN 107331745A CN 201710400369 A CN201710400369 A CN 201710400369A CN 107331745 A CN107331745 A CN 107331745A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
- H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
- H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
- H01L33/325—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen characterised by the doping materials
Abstract
The invention discloses a kind of epitaxial wafer of light emitting diode and preparation method thereof, belong to technical field of semiconductors.Epitaxial wafer includes substrate and the cushion being sequentially laminated on substrate, undoped gallium nitride layer, n type gallium nitride layer, defect barrier layer, first stress release layer, second stress release layer, tertiary stress releasing layer, luminescent layer and p-type gallium nitride layer, defect barrier layer is the gallium nitride layer of doped silicon, first stress release layer is the gallium nitride layer of doped silicon, second stress release layer includes multiple first sublayers and multiple second sublayers of alternately laminated setting, first sublayer be undoped with indium gallium nitrogen layer, second sublayer is the gallium nitride layer of doped silicon, tertiary stress releasing layer is the indium gallium nitrogen layer of doped silicon；The doping concentration of silicon is less than the first stress release layer in defect barrier layer, and the doping concentration of silicon is higher than the doping concentration of silicon in each second sublayer, each second sublayer and is less than tertiary stress releasing layer in the first stress release layer.The present invention can improve luminous efficiency.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of epitaxial wafer of light emitting diode and preparation method thereof.
Background technology
Light emitting diode (English：Light Emitting Diode, referred to as：LED) it is a kind of semi-conductor electricity that can be luminous
Subcomponent.With the semiconductor light-emitting-diode that gallium nitride (GaN) is representative, with energy gap is big, high electronics saturation drift speed
The good characteristics such as degree, high temperature resistant, high power capacity, have vast prospect in emerging opto-electronics.Chip is LED most heavy
The part wanted, epitaxial wafer is raw material prepared by chip.
Existing GaN base LED passes through in the U-shaped GaN layer of hetero-substrates (such as Sapphire Substrate) Epitaxial growth, N
Type GaN layer, luminescent layer, p-type GaN layer are formed.Wherein, luminescent layer include alternately laminated indium gallium nitrogen (InGaN) quantum well layer and
Hole in electronics in N-type GaN layer and p-type GaN layer is limited in InGaN SQWs by GaN quantum barrier layers, GaN quantum barrier layers
Recombination luminescence in layer.
During the present invention is realized, inventor has found that prior art at least has problems with：
It is dissimilar materials between GaN and substrate, lattice mismatch is big, causes to produce stress in epitaxial wafer growth course and lack
Fall into, stress and defect extend to luminescent layer along the stacked direction of epitaxial wafer, add InGaN quantum well layers and GaN quantum barrier layers it
Between there is also lattice mismatch, can further increase the stress and defect in luminescent layer, cause to carry out non-spoke between electronics and hole
Penetrate compound, thus reduce the radiation recombination in electronics and hole, eventually reduce the internal quantum efficiency of light emitting diode.
The content of the invention
In order to solve problem of the prior art, the embodiments of the invention provide a kind of LED epitaxial slice and its system
Preparation Method.The technical scheme is as follows：
In a first aspect, the embodiments of the invention provide a kind of epitaxial wafer of light emitting diode, the epitaxial wafer includes substrate
And stack gradually cushion over the substrate, undoped gallium nitride layer, n type gallium nitride layer, luminescent layer and p-type gallium nitride
Layer, the epitaxial wafer also includes defect barrier layer, the first stress release layer, the second stress release layer and tertiary stress releasing layer,
The defect barrier layer is stacked on the n type gallium nitride layer, and first stress release layer is layered in the defect barrier layer
On, second stress release layer is layered on first stress release layer, and the tertiary stress releasing layer is layered in described
Between second stress release layer and the luminescent layer；The defect barrier layer is the gallium nitride layer of doped silicon, first stress
Releasing layer is the gallium nitride layer of doped silicon, and second stress release layer includes multiple first sublayers and multiple second sublayers, many
Individual first sublayer and multiple second sublayers are alternately laminated sets, each first sublayer be undoped with indium gallium nitrogen
Layer, each second sublayer is the gallium nitride layer of doped silicon, and the tertiary stress releasing layer is the indium gallium nitrogen layer of doped silicon；Institute
The doping concentration for stating silicon in defect barrier layer is less than the doping concentration of silicon in first stress release layer, and first stress is released
The doping concentration for putting silicon in layer is higher than silicon in the doping concentration of silicon in each described second sublayer, each described second sublayer
Doping concentration is less than the doping concentration of silicon in the tertiary stress releasing layer.
Alternatively, the doping concentration of silicon is 10 in the defect barrier layer17cm-3~1018cm-3, the defect barrier layer
Thickness is 50nm~200nm.
Alternatively, the doping concentration of silicon is more than 10 in first stress release layer19cm-3, first stress release layer
Thickness be 100~300nm.
Alternatively, the doping concentration of silicon is 10 in each second sublayer17cm-3~1018cm-3, second sublayer
Thickness is 50nm~100nm.
Alternatively, the doping concentration of silicon is more than 10 in the tertiary stress releasing layer19cm-3, the tertiary stress releasing layer
Thickness be 100nm~300nm.
Alternatively, the thickness of first sublayer is 1nm~5nm.
Alternatively, the luminescent layer includes multiple quantum well layers and multiple quantum barrier layers, multiple quantum well layers and many
The individual quantum barrier layer is alternately laminated to be set, and each quantum well layer is indium gallium nitrogen layer, and each quantum barrier layer is nitridation
Gallium layer；The content of indium component is more than 0 with the ratio between content of indium component in each quantum well layer in each described first sublayer
And less than 0.2.
Alternatively, the quantity of second sublayer is identical with the quantity of first sublayer, the quantity of first sublayer
For 2~20.
Second aspect, it is described the embodiments of the invention provide a kind of preparation method of such as epitaxial wafer that first aspect is provided
Preparation method includes：
One substrate is provided；
Grown buffer layer, undoped gallium nitride layer, n type gallium nitride layer, defect barrier layer, first successively over the substrate
Stress release layer, the second stress release layer, tertiary stress releasing layer, luminescent layer and p-type gallium nitride layer；
Wherein, the defect barrier layer is the gallium nitride layer of doped silicon, and first stress release layer is the nitrogen of doped silicon
Change gallium layer, second stress release layer includes multiple first sublayers and multiple second sublayers, multiple first sublayers and many
Individual second sublayer is alternately laminated to be set, each first sublayer be undoped with indium gallium nitrogen layer, each second son
Layer is the gallium nitride layer of doped silicon, and the tertiary stress releasing layer is the indium gallium nitrogen layer of doped silicon；Silicon in the defect barrier layer
Doping concentration be less than the doping concentration of silicon in first stress release layer, the doping of silicon in first stress release layer
Concentration is higher than the doping concentration of silicon in the doping concentration of silicon in each described second sublayer, each described second sublayer less than described
The doping concentration of silicon in tertiary stress releasing layer.
Alternatively, the luminescent layer includes multiple quantum well layers and multiple quantum barrier layers, multiple quantum well layers and many
The individual quantum barrier layer is alternately laminated to be set, and each quantum well layer is indium gallium nitrogen layer, and each quantum barrier layer is nitridation
Gallium layer；The growth temperature of each first sublayer is higher than the growth temperature of each quantum well layer 50 DEG C~and 100 DEG C, each
The growth temperature of second sublayer is higher than the growth temperature of each quantum barrier layer 20 DEG C~and 50 DEG C.
The beneficial effect that technical scheme provided in an embodiment of the present invention is brought is：
Released by the setting defect barrier layer between N-type GaN layer and luminescent layer, the first stress release layer, the second stress
Layer, tertiary stress releasing layer are put, defect barrier layer is the low-doped gallium nitride layer of silicon, and the first stress release layer is that silicon is highly doped
Gallium nitride layer, the second stress release layer be undoped with indium gallium nitrogen layer and the low-doped gallium nitride layer of silicon superlattice structure, the
Three stress release layers are the highly doped indium gallium nitrogen layer of silicon, on the one hand the first stress release layer, the second stress release layer, tertiary stress
The lattice constant of releasing layer is conducive to reducing between n type gallium nitride layer and luminescent layer between n type gallium nitride layer and luminescent layer
Lattice mismatch so that the stress accumulated when reducing light emitting layer grown, play a part of discharging bottom stress, it is possible to reduce quantum
The stress produced when well layer and quantum barrier layer alternating growth, is reduced due to the lattice defect in the excessive caused luminescent layer of stress,
So as to increase electronics and the radiation recombination efficiency in hole, the internal quantum efficiency of light emitting diode is finally improved；On the other hand lack
The doping concentration height alternating of silicon in barrier layer, the first stress release layer, the second stress release layer, tertiary stress releasing layer is fallen into,
It is also that alternately (the high partial ohmic of doping concentration concentration is low, the low portion of doping concentration for height to make its integrally-built resistance
Sub-resistance is high), the high part of resistance can slow down the speed of electron transfer, more electronic energies is stayed in light-emitting zone and hole
Recombination luminescence, reduction crosses luminescent layer and overflows to the electron amount of p-type gallium nitride layer by layer, while interspersed in the middle of the high part of resistance
The low structure of resistance make overall electrical resistance excessive again, so as to avoid the occurrence of the problem of forward voltage is too high.
Brief description of the drawings
Technical scheme in order to illustrate the embodiments of the present invention more clearly, makes required in being described below to embodiment
Accompanying drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for
For those of ordinary skill in the art, on the premise of not paying creative work, other can also be obtained according to these accompanying drawings
Accompanying drawing.
Fig. 1 is a kind of structural representation for LED epitaxial slice that the embodiment of the present invention one is provided；
Fig. 2 is the structural representation for the second stress release layer that the embodiment of the present invention one is provided；
Fig. 3 is a kind of flow chart of the preparation method for LED epitaxial slice that the embodiment of the present invention two is provided；
Fig. 4 is a kind of flow chart of the preparation method for LED epitaxial slice that the embodiment of the present invention three is provided.
Embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing to embodiment party of the present invention
Formula is described in further detail.
Embodiment one
The embodiments of the invention provide a kind of epitaxial wafer of light emitting diode, referring to Fig. 1, the epitaxial wafer include substrate 10 with
And stack gradually cushion 20, undoped gallium nitride layer 30, defect barrier layer 41, the first stress release layer over the substrate 10
42nd, the second stress release layer 43, tertiary stress releasing layer 44, n type gallium nitride layer 50, multiple quantum well layer 60 and p-type gallium nitride layer
70。
In the present embodiment, as shown in figure 1, cushion 20 is laminated over the substrate 10, undoped gallium nitride layer 30 is layered in
On cushion 20, defect barrier layer 41 is layered on undoped gallium nitride layer 30, and the first stress release layer 42 is layered in defect resistance
In barrier 41, the second stress release layer 43 is layered on the first stress release layer 42, and tertiary stress releasing layer 44 is layered in second
On stress release layer 43, n type gallium nitride layer 50 is layered on tertiary stress releasing layer 44, and multiple quantum well layer 60 is layered in N-type nitrogen
Change on gallium layer 50, p-type gallium nitride layer 70 is layered on multiple quantum well layer 60.
Specifically, defect barrier layer 41 is the gallium nitride layer of doped silicon, and the first stress release layer 42 is the nitridation of doped silicon
Gallium layer, referring to Fig. 2, the second stress release layer 43 includes multiple first sublayer 43a and multiple second sublayer 43b, multiple first sons
Layer 43a and multiple second sublayer 43b it is alternately laminated set, each first sublayer 43a be undoped with indium gallium nitrogen layer, each second
Sublayer 43b is the gallium nitride layer of doped silicon, and tertiary stress releasing layer 44 is the indium gallium nitrogen layer of doped silicon.Silicon in defect barrier layer 41
Doping concentration be less than the doping concentration of silicon in the first stress release layer 42, the doping concentration of silicon in the first stress release layer 42
Higher than the doping concentration of silicon in each second sublayer 43b, the doping concentration of silicon is released less than tertiary stress in each second sublayer 43b
Put the doping concentration of silicon in layer 44.
The embodiment of the present invention passes through the setting defect barrier layer between N-type GaN layer and luminescent layer, the first stress release
Layer, the second stress release layer, tertiary stress releasing layer, defect barrier layer are the low-doped gallium nitride layer of silicon, the first stress release
Layer is the highly doped gallium nitride layer of silicon, the second stress release layer be undoped with indium gallium nitrogen layer and the low-doped gallium nitride layer of silicon
Superlattice structure, tertiary stress releasing layer is the highly doped indium gallium nitrogen layer of silicon, and on the one hand the first stress release layer, the second stress are released
The lattice constant of layer, tertiary stress releasing layer is put between n type gallium nitride layer and luminescent layer, is conducive to reducing n type gallium nitride
Lattice mismatch between layer and luminescent layer, so that the stress accumulated when reducing light emitting layer grown, plays the work of release bottom stress
With, it is possible to reduce the stress produced when quantum well layer and quantum barrier layer alternating growth, is reduced because stress is excessive caused luminous
Lattice defect in layer, so as to increase electronics and the radiation recombination efficiency in hole, finally improves the interior quantum of light emitting diode
Efficiency；Silicon mixes in another aspect defect barrier layer, the first stress release layer, the second stress release layer, tertiary stress releasing layer
Miscellaneous concentration level alternating, it is also that alternately (the high partial ohmic of doping concentration concentration is low, silicon for height to make its integrally-built resistance
The low partial ohmic of doping concentration is high), the high part of resistance can slow down the speed of electron transfer, stay in more electronic energies
Light-emitting zone lights with hole-recombination, and reduction crosses luminescent layer and overflows to the electron amount of p-type gallium nitride layer by layer, while resistance is high
Part in the middle of the low structure of interspersed resistance make overall electrical resistance excessive again, so as to avoid the occurrence of, forward voltage is too high to ask
Topic.
Alternatively, the doping concentration of silicon can be 10 in defect barrier layer 4117cm-3~1018cm-3.If defect barrier layer 41
The doping concentration of middle silicon is less than 1017cm-3, then can be because electron concentration is too low and causes forward voltage Vf to raise；If defect stops
The doping concentration of silicon is more than 10 in layer 4118cm-3, then can be because electron concentration is too high and does not reach the effect for stopping electronics.
Preferably, the thickness on defect barrier layer 41 can be 50nm~200nm.If the thickness on defect barrier layer 41 is less than
50nm, then be able to can not play a part of stopping electronics and defect due to excessively thin；If the thickness on defect barrier layer 41 is more than
200nm, then can cause resistance too big, the problem of forward voltage Vf is too high occur due to too thick.
Alternatively, the doping concentration of silicon can be more than 10 in the first stress release layer 4219cm-3.If the first stress release layer
The doping concentration of silicon is less than 10 in 4219cm-3, then reduction forward voltage Vf effect is not had.
Preferably, the thickness of the first stress release layer 42 can be 100~300nm.If the thickness of the first stress release layer 42
Degree is less than 100nm, then does not have the effect of reduction forward voltage Vf and release stress；If the thickness of the first stress release layer 42 is big
In 300nm, then may be blocked up due to thickness and increase defect.
Alternatively, the doping concentration of silicon can be 10 in each second sublayer 43b17cm-3~1018cm-3.If the second sublayer
The doping concentration of silicon is less than 10 in 43b17cm-3, then can be because electron concentration is too low and causes forward voltage Vf high；If the second son
The doping concentration of silicon is more than 10 in layer 43b18cm-3, then can be because electron concentration is too high and does not reach the effect for stopping electronics.
Preferably, the second sublayer 43b thickness can be 50nm~100nm.If the second sublayer 43b thickness is less than
50nm, then can not play a part of stopping electronics due to excessively thin and discharge stress；If the second sublayer 43b thickness is more than
100nm, then can cause resistance too big, the problem of forward voltage Vf is too high occur due to too thick.
Alternatively, the doping concentration of silicon can be more than 10 in tertiary stress releasing layer 4419cm-3.If tertiary stress releasing layer
The doping concentration of silicon is less than 10 in 4419cm-3, then reduction forward voltage Vf effect is not had.
Preferably, the thickness of tertiary stress releasing layer 44 can be 100~300nm.If the thickness of tertiary stress releasing layer 44
Degree is less than 100nm, then does not have the effect of release stress；, may be by if the thickness of tertiary stress releasing layer 44 is more than 300nm
It is blocked up and increase defect in thickness.
Alternatively, the first sublayer 43a thickness can be 1nm~5nm.If the first sublayer 43a thickness is less than 1nm,
The effect of release stress is not had；, can be because indium gallium nitrogen layer is too thick and causes to answer if the first sublayer 43a thickness is more than 5nm
Power increase.
Alternatively, the second sublayer 43b quantity is identical with the first sublayer 43a quantity, and the first sublayer 43a quantity can be with
For 2~20.If the first sublayer 43a quantity is less than 2, the effect of release stress is not had；If the first sublayer 43a number
Amount is more than 20, then may increase stress due to blocked up.
Specifically, luminescent layer can include multiple quantum well layers and multiple quantum barrier layers, multiple quantum well layers and multiple amounts
Sub- barrier layer is alternately laminated to be set, and each quantum well layer is indium gallium nitrogen layer, and each quantum barrier layer is gallium nitride layer.
Alternatively, the ratio between content of indium component can be with the content of indium component and each quantum well layer in each first sublayer
More than 0 and less than 0.2.If the content of indium component reaches with the ratio between content of indium component in each quantum well layer in each first sublayer
To 0.2, then it may reduce because the potential barrier of the first sublayer is too low and causes the restriction effect to electronics too big and cross the first son
Layer reaches the electronics sum of quantum well layer, is unfavorable for improving the internal quantum efficiency of light emitting diode.
Specifically, the material of substrate can be sapphire, or other materials, such as silicon nitride, gallium nitride, monocrystalline silicon
Deng.Cushion can be gallium nitride layer, and thickness is 20nm~40nm.The thickness of undoped gallium nitride layer is 0.5 μm~2 μm.N-type
Gallium nitride layer is the gallium nitride layer of doped silicon, and thickness is 0.8 μm~3 μm, and the doping concentration of silicon is 1018cm-3~1019cm-3.Amount
The thickness of sub- well layer is 2nm~3nm, and the thickness of quantum barrier layer is 5nm~30nm, the quantity of quantum barrier layer and the number of quantum well layer
Amount is identical, and the quantity of quantum well layer is 6~15.P-type gallium nitride layer is magnesium-doped gallium nitride layer, and thickness is 0.3 μm~0.5
μm。
Embodiment two
The embodiments of the invention provide a kind of extension piece preparation method of light emitting diode, it is adaptable to prepares embodiment one and carries
The epitaxial wafer of confession, referring to Fig. 3, the preparation method includes：
Step 101：One substrate is provided.
In the specific implementation, can first substrate is made annealing treatment in hydrogen atmosphere, then by temperature control be 1050 DEG C
~1180 DEG C, nitrogen treatment is carried out 10 minutes, to clean substrate surface.
Step 102：On substrate successively grown buffer layer, undoped gallium nitride layer, n type gallium nitride layer, defect barrier layer,
First stress release layer, the second stress release layer, tertiary stress releasing layer, luminescent layer and p-type gallium nitride layer.
In the present embodiment, defect barrier layer is the gallium nitride layer of doped silicon, and the first stress release layer is the nitrogen of doped silicon
Change gallium layer, the second stress release layer includes multiple first sublayers and multiple second sublayers, multiple first sublayers and multiple second sons
Layer it is alternately laminated set, each first sublayer be undoped with indium gallium nitrogen layer, each second sublayer be doped silicon gallium nitride layer,
Tertiary stress releasing layer is the indium gallium nitrogen layer of doped silicon；The doping concentration of silicon is less than in the first stress release layer in defect barrier layer
The doping concentration of silicon is higher than the doping concentration of silicon in each second sublayer in the doping concentration of silicon, the first stress release layer, respectively
The doping concentration of silicon is less than the doping concentration of silicon in tertiary stress releasing layer in individual second sublayer.
The embodiment of the present invention passes through the setting defect barrier layer between N-type GaN layer and luminescent layer, the first stress release
Layer, the second stress release layer, tertiary stress releasing layer, defect barrier layer are the low-doped gallium nitride layer of silicon, the first stress release
Layer is the highly doped gallium nitride layer of silicon, the second stress release layer be undoped with indium gallium nitrogen layer and the low-doped gallium nitride layer of silicon
Superlattice structure, tertiary stress releasing layer is the highly doped indium gallium nitrogen layer of silicon, and on the one hand the first stress release layer, the second stress are released
The lattice constant of layer, tertiary stress releasing layer is put between n type gallium nitride layer and luminescent layer, is conducive to reducing n type gallium nitride
Lattice mismatch between layer and luminescent layer, so that the stress accumulated when reducing light emitting layer grown, plays the work of release bottom stress
With, it is possible to reduce the stress produced when quantum well layer and quantum barrier layer alternating growth, is reduced because stress is excessive caused luminous
Lattice defect in layer, so as to increase electronics and the radiation recombination efficiency in hole, finally improves the interior quantum of light emitting diode
Efficiency；Silicon mixes in another aspect defect barrier layer, the first stress release layer, the second stress release layer, tertiary stress releasing layer
Miscellaneous concentration level alternating, it is also that alternately (the high partial ohmic of doping concentration concentration is low, silicon for height to make its integrally-built resistance
The low partial ohmic of doping concentration is high), the high part of resistance can slow down the speed of electron transfer, stay in more electronic energies
Light-emitting zone lights with hole-recombination, and reduction crosses luminescent layer and overflows to the electron amount of p-type gallium nitride layer by layer, while resistance is high
Part in the middle of the low structure of interspersed resistance make overall electrical resistance excessive again, so as to avoid the occurrence of, forward voltage is too high to ask
Topic.
Specifically, luminescent layer can include multiple quantum well layers and multiple quantum barrier layers, multiple quantum well layers and multiple amounts
Sub- barrier layer is alternately laminated to be set, and each quantum well layer is indium gallium nitrogen layer, and each quantum barrier layer is gallium nitride layer.
Alternatively, the growth temperature of each the first sublayer can be higher than the growth temperature of each quantum well layer by 50 DEG C~100
℃.If the difference of the growth temperature of the growth temperature of each the first sublayer and each quantum well layer is less than 50 DEG C, easily due to
Temperature is too low and introduces new defect；If the difference of the growth temperature of each the first sublayer and the growth temperature of each quantum well layer
More than 100 DEG C, then being incorporated to for indium component in indium gallium nitrogen layer may be influenceed.
Alternatively, the growth temperature of each the second sublayer can be higher than the growth temperature of each quantum barrier layer 20 DEG C~50 DEG C
℃.If the difference of the growth temperature of each the second sublayer and the growth temperature of each quantum barrier layer is less than -20 DEG C, it may rise not
To the effect of release stress；If the difference of the growth temperature of each the second sublayer and the growth temperature of each quantum barrier layer is more than 50
DEG C, might have temperature it is too high and influence the first sublayer indium separate out, cause crystal mass poor.
In the present embodiment, whole process is using metallo-organic compound chemical gaseous phase deposition (English：Meta1Organic
Chemical Vapor Deposition, referred to as：MOCVD) reaction chamber is realized, gallium is used as using trimethyl gallium (TMGa) when realizing
Source, high-purity ammonia (NH3) as nitrogen source, trimethyl indium is as indium source, and trimethyl aluminium selects silane as silicon source, N type dopant,
P-type dopant is from two luxuriant magnesium.
Specifically, cushion can be gallium nitride layer, during grown buffer layer, can be passed through TMGa sources and NH3, control temperature
For 450 DEG C~600 DEG C, pressure is 400torr~600torr, and growth thickness is 20nm~40nm gallium nitride layer.
When growing undoped gallium nitride layer, TMGa sources and NH are passed through3, it is 1000 DEG C~1200 DEG C to control temperature, and pressure is
50torr~760torr, growth thickness is 0.5 μm~2 μm of gallium nitride layer.
When growing n type gallium nitride layer, it is 1000 DEG C~1200 DEG C to control temperature, and pressure is 50torr~760torr, growth
Thickness is 0.8 μm~3 μm, doping concentration is 1018cm-3~1019cm-3Gallium nitride layer.
During growth defect barrier layer, it is 1000 DEG C~1200 DEG C to control temperature, and pressure is 200torr~400torr, growth
Thickness is that 50nm~200nm, doping concentration are 1017cm-3~1018cm-3Gallium nitride layer.
During one stress release layer of growth regulation, it is 950 DEG C~1100 DEG C to control temperature, and pressure is 200torr~400torr,
Growth thickness is 100~300nm, doping concentration reaches 1019cm-3Gallium nitride layer.
During two stress release layer of growth regulation, control pressure be 200torr~400torr, alternating growth thickness be 50nm~
150nm, doping concentration are 1017cm-3~1018cm-3Gallium nitride layer and thickness for 1nm~5nm undoped with indium gallium nitride
Layer, the growth temperature of indium gallium nitrogen layer is 750 DEG C~950 DEG C, the growth temperature of gallium nitride layer for 820 DEG C~1000 DEG C, gallium nitride
The quantity of layer is identical with the quantity of indium gallium nitrogen layer, and the quantity of indium gallium nitrogen layer is 2~20.
During three stress release layer of growth regulation, it is 850 DEG C~950 DEG C to control temperature, and pressure is 200torr~400torr, raw
Long thickness is 100~300nm, doping concentration reaches 1019cm-3Gallium nitride layer.
When growing luminescent layer, control pressure is 200torr~400torr, and alternating growth thickness is 2nm~3nm indium gallium
Nitrogen layer and the gallium nitride layer that thickness is 5nm~30nm, the growth temperature of indium gallium nitrogen layer is 700 DEG C~850 DEG C, the life of gallium nitride layer
Long temperature is 800 DEG C~950 DEG C, and the quantity of gallium nitride layer is identical with the quantity of indium gallium nitrogen layer, and the quantity of indium gallium nitrogen layer is 6~15
It is individual.
During growing P-type gallium nitride layer, it is 950 DEG C~1150 DEG C to control temperature, and pressure is 50torr~760torr, growth
Thickness is 0.4 μm of magnesium-doped gallium nitride layer.
It should be noted that in the present embodiment, the first stress release layer, the second stress release layer, tertiary stress release
The growth temperature of layer is less than the growth temperature of n type gallium nitride layer, and close to the growth temperature of luminescent layer, is also beneficial to discharge bottom
The stress tired out to n type gallium nitride lamination.
Alternatively, after grown buffer layer, the preparation method can also include：
Stopping is passed through TMGa sources, and it is 1000 DEG C~1200 DEG C to control temperature, and the original of 5 minutes~10 minutes is carried out to cushion
Position annealing.
It should be noted that after epitaxial growth terminates, first by the temperature control of reaction chamber 700 DEG C~800 DEG C it
Between, the annealing of 5 minutes~15 minutes is carried out under pure nitrogen gas atmosphere, then the temperature of reaction chamber is down to room temperature.Then, will
Single chip is made through semiconducter process such as over cleaning, deposition, photoetching and etchings in epitaxial wafer.
Embodiment three
The embodiments of the invention provide the preparation that a kind of preparation method of the epitaxial wafer of light emitting diode, the present embodiment are provided
Method is that the one kind for the preparation method that embodiment three is provided is implemented.Specifically, referring to Fig. 4, the preparation method includes：
Step 201：One Sapphire Substrate is provided.
Step 202：It is 575 DEG C to control growth temperature, and growth pressure is 500torr, on a sapphire substrate growth thickness
For 30nm gallium nitride layer, cushion is formed.
Step 203：It is 1100 DEG C to control growth temperature, and growth pressure is 405torr, and growth thickness is on nucleating layer
1.25 μm of undoped gallium nitride layer.
Step 204：It is 1100 DEG C to control growth temperature, and growth pressure is 405torr, is grown on undoped gallium nitride layer
Thickness is 1.9 μm of n type gallium nitride layer.
Step 205：It is 1100 DEG C to control growth temperature, and growth pressure is 300torr, is grown on n type gallium nitride layer thick
Degree is that 125nm, doping concentration are 5*1017cm-3cm-3Gallium nitride layer, form defect barrier layer.
Step 206：It is 1025 DEG C to control growth temperature, and growth pressure is 300torr, the growth thickness on defect barrier layer
It is 2*10 for 200nm, doping concentration19cm-3Gallium nitride layer, formed the first stress release layer.
Step 207：It is 300torr to control growth pressure, and 10 thickness of alternating growth are on the first stress release layer
100nm, doping concentration are 5*1017cm-3Gallium nitride layer and 10 thickness for 3nm undoped with indium gallium nitride layer, indium gallium
The growth temperature of nitrogen layer is 850 DEG C, and the growth temperature of gallium nitride layer is 910 DEG C, forms the second stress release layer.
Step 208：It is 900 DEG C to control growth temperature, and growth pressure is 300torr, and growth thickness is 100nm, silicon doping
Concentration is 2*1019cm-3Gallium nitride layer, formed tertiary stress releasing layer.
Step 209：It is 300torr to control growth pressure, and 10 thickness of alternating growth are on tertiary stress releasing layer
The gallium nitride quantum barrier layer that 2.5nm indium gallium nitrogen quantum well layer and 10 thickness are 17.5nm, the growth of indium gallium nitrogen quantum well layer
Temperature is 775 DEG C, and the growth temperature of gallium nitride quantum barrier layer is 875 DEG C, forms luminescent layer.
Step 210：It is 1050 DEG C to control growth temperature, and growth pressure is 405torr, the growth thickness on multiple quantum well layer
For 0.4 μm of p-type gallium nitride layer.
In the present embodiment, defect barrier layer, the first stress release layer, the second stress release layer and tertiary stress releasing layer
Parameters be only for example.Discharged according to defect barrier layer, the first stress release layer, the second stress release layer and tertiary stress
The change of the doping concentration of silicon in layer, keeps defect barrier layer, the first stress release layer, the second stress release layer and tertiary stress
The other parameters of releasing layer are constant, and the parameters of other each layers are also constant, the epitaxial wafer prepared and existing epitaxial wafer
(not having defect barrier layer, the first stress release layer, the second stress release layer and tertiary stress releasing layer, other parameters are identical) phase
Than the ratio that luminous efficiency is improved is as shown in following table one：
Table one
Contrast table one is it can be found that defect barrier layer, the first stress release layer, the second stress release layer and tertiary stress are released
Put in the alternate overall structure of doping concentration height of layer composition, the high part doping concentration of doping concentration is higher, luminous efficiency
It is higher；The low part doping concentration of doping concentration is lower simultaneously, and luminous efficiency is higher；As can be seen here, the high part of doping concentration
Doping concentration difference is bigger between the low part of doping concentration, and luminous efficiency is higher.
According to the change of the first sublayer and the growth temperature of the second sublayer, keep defect barrier layer, the first stress release layer,
The other parameters of second stress release layer and tertiary stress releasing layer are constant, and the parameters of other each layers are also constant, prepare
The epitaxial wafer gone out (does not have defect barrier layer, the first stress release layer, the second stress release layer and the 3rd to answer with existing epitaxial wafer
Power releasing layer, other parameters are identical) to compare, the ratio that luminous efficiency is improved is as shown in following table two：
Table two
| The growth temperature of first sublayer | The growth temperature of second sublayer | The ratio that luminous efficiency is improved |
| 750℃ | 820℃ | 0.2% |
| 750℃ | 910℃ | 0.4% |
| 750℃ | 1000℃ | 0.3% |
| 850℃ | 820℃ | 0.7% |
| 850℃ | 910℃ | 0.9% |
| 850℃ | 1000℃ | 0.8% |
| 950℃ | 820℃ | 0.3% |
| 950℃ | 910℃ | 0.55 |
| 950℃ | 1000℃ | 0.4% |
Contrast table two is it can be found that the rise of the growth temperature with the first sublayer, luminous efficiency is first raised and reduced again；Together
When first raise and reduce again with the growth temperature of the second sublayer, luminous efficiency；As can be seen here, the growth temperature of the first sublayer,
The growth temperature of two sublayers is in certain scope, luminous efficiency highest.
The embodiments of the present invention are for illustration only, and the quality of embodiment is not represented.
The foregoing is only presently preferred embodiments of the present invention, be not intended to limit the invention, it is all the present invention spirit and
Within principle, any modification, equivalent substitution and improvements made etc. should be included in the scope of the protection.
Claims (10)
1. a kind of epitaxial wafer of light emitting diode, the epitaxial wafer includes substrate and stacks gradually buffering over the substrate
Layer, undoped gallium nitride layer, n type gallium nitride layer, luminescent layer and p-type gallium nitride layer, it is characterised in that the epitaxial wafer also includes
Defect barrier layer, the first stress release layer, the second stress release layer and tertiary stress releasing layer, the defect barrier layer are stacked in
On the n type gallium nitride layer, first stress release layer is layered on the defect barrier layer, second stress release layer
It is layered on first stress release layer, the tertiary stress releasing layer is layered in second stress release layer and the hair
Between photosphere；The defect barrier layer is the gallium nitride layer of doped silicon, and first stress release layer is the gallium nitride of doped silicon
Layer, second stress release layer includes multiple first sublayers and multiple second sublayers, multiple first sublayers and multiple institutes
State the alternately laminated setting of the second sublayer, each first sublayer be undoped with indium gallium nitrogen layer, each second sublayer is
The gallium nitride layer of doped silicon, the tertiary stress releasing layer is the indium gallium nitrogen layer of doped silicon；Silicon mixes in the defect barrier layer
Miscellaneous concentration is less than the doping concentration of silicon in the doping concentration of silicon in first stress release layer, first stress release layer
Higher than the doping concentration of silicon in the second sublayer each described, the doping concentration of silicon is less than the described 3rd in each described second sublayer
The doping concentration of silicon in stress release layer.
2. epitaxial wafer according to claim 1, it is characterised in that the doping concentration of silicon is in the defect barrier layer
1017cm-3~1018cm-3, the thickness on the defect barrier layer is 50nm~200nm.
3. epitaxial wafer according to claim 2, it is characterised in that the doping concentration of silicon is big in first stress release layer
In 1019cm-3, the thickness of first stress release layer is 100~300nm.
4. epitaxial wafer according to claim 3, it is characterised in that the doping concentration of silicon is in each second sublayer
1017cm-3~1018cm-3, the thickness of second sublayer is 50nm~100nm.
5. epitaxial wafer according to claim 4, it is characterised in that the doping concentration of silicon is big in the tertiary stress releasing layer
In 1019cm-3, the thickness of the tertiary stress releasing layer is 100nm~300nm.
6. the epitaxial wafer according to any one of Claims 1 to 5, it is characterised in that the thickness of first sublayer be 1nm~
5nm。
7. the epitaxial wafer according to any one of Claims 1 to 5, it is characterised in that the luminescent layer includes multiple SQWs
Layer and multiple quantum barrier layers, multiple quantum well layers and the alternately laminated setting of multiple quantum barrier layers, each quantum
Well layer is indium gallium nitrogen layer, and each quantum barrier layer is gallium nitride layer；In each described first sublayer the content of indium component with it is every
The ratio between content of indium component is more than 0 and less than 0.2 in the individual quantum well layer.
8. the epitaxial wafer according to any one of Claims 1 to 5, it is characterised in that the quantity of second sublayer with it is described
The quantity of first sublayer is identical, and the quantity of first sublayer is 2~20.
9. a kind of preparation method of epitaxial wafer as described in any one of claim 1~8, it is characterised in that the preparation method
Including：
One substrate is provided；
Grown buffer layer, undoped gallium nitride layer, n type gallium nitride layer, defect barrier layer, the first stress successively over the substrate
Releasing layer, the second stress release layer, tertiary stress releasing layer, luminescent layer and p-type gallium nitride layer；
Wherein, the defect barrier layer is the gallium nitride layer of doped silicon, and first stress release layer is the gallium nitride of doped silicon
Layer, second stress release layer includes multiple first sublayers and multiple second sublayers, multiple first sublayers and multiple institutes
State the alternately laminated setting of the second sublayer, each first sublayer be undoped with indium gallium nitrogen layer, each second sublayer is
The gallium nitride layer of doped silicon, the tertiary stress releasing layer is the indium gallium nitrogen layer of doped silicon；Silicon mixes in the defect barrier layer
Miscellaneous concentration is less than the doping concentration of silicon in the doping concentration of silicon in first stress release layer, first stress release layer
Higher than the doping concentration of silicon in the second sublayer each described, the doping concentration of silicon is less than the described 3rd in each described second sublayer
The doping concentration of silicon in stress release layer.
10. preparation method according to claim 9, it is characterised in that the luminescent layer includes multiple quantum well layers and many
Individual quantum barrier layer, multiple quantum well layers and multiple quantum barrier layers are alternately laminated sets, each quantum well layer is
Indium gallium nitrogen layer, each quantum barrier layer is gallium nitride layer；The growth temperature of each first sublayer is than each quantum
The growth temperature of well layer is high 50 DEG C~100 DEG C, life of the growth temperature than each quantum barrier layer of each second sublayer
Long temperature is high 20 DEG C~and 50 DEG C.
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