CN109860357B - Gallium nitride-based light emitting diode epitaxial wafer and growth method thereof - Google Patents

Gallium nitride-based light emitting diode epitaxial wafer and growth method thereof Download PDF

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CN109860357B
CN109860357B CN201811276029.7A CN201811276029A CN109860357B CN 109860357 B CN109860357 B CN 109860357B CN 201811276029 A CN201811276029 A CN 201811276029A CN 109860357 B CN109860357 B CN 109860357B
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epitaxial wafer
gallium nitride
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semiconductor layer
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CN109860357A (en
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王曼
张琰琰
陆香花
周飚
胡加辉
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HC Semitek Suzhou Co Ltd
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Abstract

The invention discloses a gallium nitride-based light emitting diode epitaxial wafer and a growth method thereof, belonging to the technical field of semiconductors. The gallium nitride-based light emitting diode epitaxial wafer comprises a substrate, an N-type semiconductor layer, a stress release layer, an active layer and a P-type semiconductor layer, wherein the N-type semiconductor layer, the stress release layer, the active layer and the P-type semiconductor layer are sequentially stacked on the substrate; the electronic adjusting layer is made of N-type doped aluminum gallium nitride, and the doping concentration of an N-type dopant in the electronic adjusting layer is gradually reduced along the stacking direction of the gallium nitride-based light emitting diode epitaxial wafer. The invention can improve the recombination luminous efficiency of electrons and holes in the active layer.

Description

Gallium nitride-based light emitting diode epitaxial wafer and growth method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a gallium nitride-based light emitting diode epitaxial wafer and a growth method thereof.
Background
A Light Emitting Diode (LED) is a semiconductor Diode that can convert electrical energy into Light energy. The III-V family semiconductor material is known as the third generation semiconductor material and has excellent photoelectric property. LEDs made of gallium nitride (GaN) -based materials among iii-v semiconductor materials can emit various colors of light by controlling the composition of the materials, which is the focus of research in the industry.
The epitaxial wafer is a primary finished product in the LED preparation process. The conventional LED epitaxial wafer includes a substrate, an N-type semiconductor layer, an active layer, and a P-type semiconductor layer, which are sequentially stacked on the substrate. The P-type semiconductor layer is used for providing holes for carrying out compound luminescence, the N-type semiconductor layer is used for providing electrons for carrying out compound luminescence, the active layer is used for carrying out radiation compound luminescence of the electrons and the holes, and the substrate is used for providing a growth surface for the epitaxial material.
In the process of implementing the invention, the inventor finds that the prior art has at least the following problems:
the number of electrons provided by the N-type semiconductor layer is much greater than the number of holes of the P-type semiconductor layer, plus the volume of electrons is much smaller than the volume of holes, resulting in the number of electrons injected into the active layer being much greater than the number of holes. The redundant electrons of the active layer are easy to jump into the P-type semiconductor layer to be non-radiatively recombined with the holes, so that the quantity of the holes injected into the active layer is less, and the recombination luminous efficiency of the electrons and the holes in the active layer is reduced.
Disclosure of Invention
The embodiment of the invention provides a gallium nitride-based light-emitting diode epitaxial wafer and a growth method thereof, which can solve the problem that the electron overflow reduces the composite luminous efficiency in the prior art. The technical scheme is as follows:
in one aspect, an embodiment of the present invention provides a gallium nitride-based light emitting diode epitaxial wafer, where the gallium nitride-based light emitting diode epitaxial wafer includes a substrate, an N-type semiconductor layer, a stress release layer, an active layer, and a P-type semiconductor layer, where the N-type semiconductor layer, the stress release layer, the active layer, and the P-type semiconductor layer are sequentially stacked on the substrate, and the gallium nitride-based light emitting diode epitaxial wafer further includes an electronic adjustment layer, and the electronic adjustment layer is disposed between the stress release layer and the active layer; the electronic adjusting layer is made of N-type doped aluminum gallium nitride, and the doping concentration of an N-type dopant in the electronic adjusting layer is gradually reduced along the stacking direction of the gallium nitride-based light emitting diode epitaxial wafer.
Optionally, a maximum value of the doping concentration of the N-type dopant in the electronic adjustment layer is smaller than the doping concentration of the N-type dopant in the N-type semiconductor layer, and a minimum value of the doping concentration of the N-type dopant in the electronic adjustment layer is 0.
Preferably, the doping concentration of the N-type dopant in the electronic adjustment layer is 0-1018/cm3
Optionally, the number of aluminum atoms in the electron adjustment layer is less than the number of gallium atoms in the electron adjustment layer.
Preferably, the content of the aluminum component in the electronic adjustment layer gradually increases along the lamination direction of the gallium nitride-based light emitting diode epitaxial wafer.
Preferably, the content of the aluminum component in the electronic adjustment layer is gradually reduced along the lamination direction of the gallium nitride-based light emitting diode epitaxial wafer.
Optionally, the thickness of the electronic adjustment layer is 0.5nm to 10 nm.
On the other hand, the embodiment of the invention provides a growth method of a gallium nitride-based light emitting diode epitaxial wafer, which comprises the following steps:
providing a substrate;
sequentially growing an N-type semiconductor layer, a stress release layer, an electronic adjustment layer, an active layer and a P-type semiconductor layer on the substrate;
the electronic adjusting layer is made of N-type doped aluminum gallium nitride, and the doping concentration of an N-type dopant in the electronic adjusting layer is gradually reduced along the stacking direction of the gallium nitride-based light emitting diode epitaxial wafer.
Optionally, the growth conditions of the electronic adjustment layer are the same as those of the stress release layer, and the growth conditions include growth temperature and growth pressure.
Preferably, the growth temperature of the electronic adjustment layer is 750-900 ℃, and the growth pressure of the electronic adjustment layer is 100-300 torr.
The technical scheme provided by the embodiment of the invention has the following beneficial effects:
the electron adjusting layer is inserted in front of the active layer, the electron adjusting layer is made of N-type doped aluminum gallium nitride, the energy level of the aluminum gallium nitride is high, a certain blocking effect on electrons is achieved, the speed of injecting electrons into the active layer can be effectively reduced, transverse expansion of the electrons is facilitated, the recombination opportunity of electrons and holes in the active layer is improved, and the recombination luminous efficiency of the electrons and the holes in the active layer is further improved. And the doping concentration of the N-type dopant in the electronic adjustment layer is gradually reduced, the doping concentration of the part of the N-type dopant close to the active layer is lower, and under the condition of ensuring current expansion, the defect generated by doping can be effectively prevented from extending to the active layer, so that the non-radiative recombination center generated by the defect is reduced, and the recombination luminous efficiency of electrons and holes in the active layer is equivalently improved.
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In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a gan-based led epitaxial wafer according to an embodiment of the present invention;
fig. 2 is a flowchart of a method for growing a gan-based led epitaxial wafer according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
The embodiment of the invention provides a gallium nitride-based light emitting diode epitaxial wafer. Fig. 1 is a schematic structural diagram of a gallium nitride-based light emitting diode epitaxial wafer according to an embodiment of the present invention. Referring to fig. 1, the gan-based light emitting diode epitaxial wafer includes a substrate 10, an N-type semiconductor layer 20, a stress relief layer 30, an electron adjustment layer 40, an active layer 50, and a P-type semiconductor layer 60, wherein the N-type semiconductor layer 20, the stress relief layer 30, the electron adjustment layer 40, the active layer 50, and the P-type semiconductor layer 60 are sequentially stacked on the substrate 10.
In this embodiment, the material of the electron adjustment layer 40 is N-type doped aluminum gallium nitride, and the doping concentration of the N-type dopant in the electron adjustment layer 40 is gradually decreased along the stacking direction of the gan-based light emitting diode epitaxial wafer.
According to the embodiment of the invention, the electron adjusting layer is inserted in front of the active layer, the material of the electron adjusting layer is N-type doped aluminum gallium nitride, the energy level of the aluminum gallium nitride is higher, and the electron adjusting layer has a certain blocking effect on electrons, so that the speed of injecting electrons into the active layer can be effectively slowed down, the transverse expansion of the electrons is facilitated, the recombination opportunity of electrons and holes in the active layer is improved, and the recombination luminous efficiency of the electrons and the holes in the active layer is further improved. And the doping concentration of the N-type dopant in the electronic adjustment layer is gradually reduced, the doping concentration of the part of the N-type dopant close to the active layer is lower, and under the condition of ensuring current expansion, the defect generated by doping can be effectively prevented from extending to the active layer, so that the non-radiative recombination center generated by the defect is reduced, and the recombination luminous efficiency of electrons and holes in the active layer is equivalently improved. In addition, the aluminum atoms have a light reflecting effect, and light absorption inside the epitaxial wafer can be reduced.
Alternatively, the maximum value of the doping concentration of the N-type dopant in the electron adjustment layer 40 may be smaller than the doping concentration of the N-type dopant in the N-type semiconductor layer 20, and the minimum value of the doping concentration of the N-type dopant in the electron adjustment layer 40 may be 0. The doping concentration of the N-type dopant in the N-type semiconductor layer is gradually reduced to the doping concentration of the N-type dopant in the active layer, and the N-type semiconductor layer and the active layer are matched, so that the negative influence caused by doping is reduced as much as possible, and the luminous efficiency of the LED is finally improved.
Specifically, the doping concentration of the N-type dopant in the electron adjustment layer 40 may be 0to 1018/cm3E.g. doping concentration of N-type dopant from 10 in the electronic adjustment layer 4018/cm3The temperature is gradually reduced to 0, and the realization effect is good.
Alternatively, the number of aluminum atoms in the electron adjustment layer 40 may be smaller than the number of gallium atoms in the electron adjustment layer 40 to maintain the bulk structure of gallium nitride.
Specifically, the material of the electron adjusting layer 40 may be N-type doped AlxGa1-xN, x is more than 0 and less than 0.5, and the realization effect is good.
Preferably, the content of the aluminum component in the electronic adjustment layer 40 may gradually increase along the stacking direction of the gan-based LED epitaxial wafer, and the lattice matching degree between the electronic adjustment layer and the adjacent semiconductor layer may be improved, so as to improve the crystal quality of the electronic adjustment layer, reduce impurity light absorption, and improve the light emitting efficiency of the LED.
Preferably, the content of the aluminum component in the electronic adjustment layer 40 can be gradually reduced along the lamination direction of the gan-based LED epitaxial wafer, so that the effect of blocking dislocation and defects can be improved, the non-radiative recombination centers generated by the defects can be reduced, and the light emitting efficiency of the LED can be improved.
Alternatively, the thickness of the electron adjustment layer 40 may be 0.5nm to 10 nm. If the thickness of the electron adjusting layer is less than 0.5nm, the electron adjusting layer may not be thin enough to effectively slow down the injection of electrons into the active layer; if the thickness of the electronic adjustment layer is greater than 10nm, lattice mismatch may be additionally caused due to the thicker electronic adjustment layer, which reduces the overall crystal quality of the epitaxial wafer and reduces the light emitting efficiency of the LED.
Specifically, the material of the substrate 10 may employ sapphire (the main material is alumina), such as sapphire having a crystal orientation of [0001 ]. The material of the N-type semiconductor layer 20 may be N-type doped (e.g., silicon) gan. The stress relieving layer 30 may include a plurality of first sub-layers and a plurality of second sub-layers, which are alternately stacked. The first sublayer is made of undoped indium gallium nitride, and the second sublayer is made of undoped gallium nitride. The active layer 50 includes a plurality of quantum wells and a plurality of quantum barriers, which are alternately stacked; the material of the quantum well can adopt undoped indium gallium nitride, and the material of the quantum barrier can adopt undoped gallium nitride. The P-type semiconductor layer 60 may be P-type doped (e.g., mg) gan.
Further, the thickness of the N-type semiconductor layer 20 may be 1.5 to 5.5 μm, preferably 3.5 μm; the doping concentration of the N-type dopant in the N-type semiconductor layer 20 may be 1018cm-3~1019cm-3Preferably 5 x 1018cm-3. The thickness of the first sublayer may be 1nm to 3nm, preferably 2 nm; the thickness of the second sublayer may be 45nm to 50nm, preferably 48 nm. The number of the second sub-layers is the same as the number of the first sub-layersThe number of the cells may be 2 to 20, and preferably 11. The thickness of the quantum well can be 1 nm-4 nm, preferably 2.5 nm; the thickness of the quantum barrier can be 8 nm-18 nm, and is preferably 13 nm; the number of quantum barriers is the same as the number of quantum wells, and the number of quantum wells may be 6 to 12, preferably 9. The thickness of the P-type semiconductor layer 60 may be 100nm to 800nm, preferably 450 nm; the doping concentration of the P-type dopant in the P-type semiconductor layer 60 may be 1018/cm3~1020/cm3Preferably 1019/cm3
Optionally, as shown in fig. 1, the gan-based led epitaxial wafer may further include a buffer layer 71, where the buffer layer 71 is disposed between the substrate 10 and the N-type semiconductor layer 20to relieve stress and defects generated by lattice mismatch between the substrate material and the gan and provide nucleation centers for epitaxial growth of the gan material.
Specifically, the material of the buffer layer 71 may be gallium nitride or aluminum nitride.
Further, the thickness of the buffer layer 71 may be 15nm to 35nm, preferably 25 nm.
Preferably, as shown in fig. 1, the gan-based led epitaxial wafer may further include an undoped gan layer 72, where the undoped gan layer 72 is disposed between the buffer layer 71 and the N-type semiconductor layer 20to further alleviate stress and defects caused by lattice mismatch between the substrate material and the gan, and provide a growth surface with good crystal quality for the main structure of the epitaxial wafer.
In a specific implementation, the buffer layer is a thin layer of gallium nitride that is first grown at low temperature on the patterned substrate, and is therefore also referred to as a low temperature buffer layer. Then, the longitudinal growth of gallium nitride is carried out on the low-temperature buffer layer, and a plurality of mutually independent three-dimensional island-shaped structures called three-dimensional nucleation layers can be formed; then, transverse growth of gallium nitride is carried out on all the three-dimensional island structures and among the three-dimensional island structures to form a two-dimensional plane structure which is called a two-dimensional recovery layer; and finally, growing a thicker gallium nitride layer called an intrinsic gallium nitride layer on the two-dimensional growth layer at a high temperature. The three-dimensional nucleation layer, two-dimensional recovery layer, and intrinsic gallium nitride layer are collectively referred to as undoped gallium nitride layer in this embodiment.
Further, the thickness of the undoped gallium nitride layer 72 may be 0.5 μm to 4.5 μm, preferably 2.5 μm.
Optionally, as shown in fig. 1, the gan-based LED epitaxial wafer may further include an electron blocking layer 81, and the electron blocking layer 81 is disposed between the active layer 50 and the P-type semiconductor layer 60 to block electrons from jumping into the P-type semiconductor layer to combine with holes in a non-radiative manner, thereby reducing the light emitting efficiency of the LED.
Specifically, the electron blocking layer 81 may be made of P-type doped aluminum gallium nitride, such as AlyGa1-yN, y is more than 0.1 and less than 0.5; the doping concentration of the P-type dopant in the electron blocking layer 81 may be 1018/cm3~1020/cm3Preferably 1019/cm3
Further, the thickness of the electron blocking layer 81 may be 200nm to 1000nm, preferably 600 nm.
Preferably, as shown in fig. 1, the gan-based led epitaxial wafer may further include a low-temperature P-type layer 82, where the low-temperature P-type layer 82 is disposed between the active layer 30 and the electron blocking layer 81, so as to avoid indium atoms in the active layer from being precipitated due to a high growth temperature of the electron blocking layer, which affects the light emitting efficiency of the led.
Specifically, the material of the low temperature P-type layer 82 may be the same as the material of the P-type semiconductor layer 60. In the present embodiment, the material of the low temperature P-type layer 82 may be P-type doped gan.
Further, the thickness of the low-temperature P-type layer 82 may be 20nm to 1000nm, preferably 60 nm; the doping concentration of the P-type dopant in the low temperature P-type layer 82 may be 1018/cm3~1020/cm3Preferably 1019/cm3
Optionally, as shown in fig. 1, the gan-based led epitaxial wafer may further include a contact layer 90, where the contact layer 90 is disposed on the P-type semiconductor layer 60 to form an ohmic contact with an electrode or a transparent conductive film formed in a chip manufacturing process.
Specifically, the contact layer 90 may be made of P-type doped indium gallium nitride or gallium nitride.
Further, the thickness of the contact layer 90 may be 5nm to 300nm, preferably 100 nm; the doping concentration of the P-type dopant in the contact layer 90 may be 1021/cm3~1022/cm3Preferably 5 x 1021/cm3
The embodiment of the invention provides a growth method of a gallium nitride-based light-emitting diode epitaxial wafer, which is suitable for growing the gallium nitride-based light-emitting diode epitaxial wafer shown in figure 1. Fig. 2 is a flowchart of a method for growing a gan-based led epitaxial wafer according to an embodiment of the present invention. Referring to fig. 2, the growing method includes:
step 201: a substrate is provided.
Optionally, the step 201 may include:
controlling the temperature to be 1000-1200 ℃ (preferably 1100 ℃), and annealing the substrate for 6-10 minutes (preferably 8 minutes) in a hydrogen atmosphere;
the substrate is subjected to a nitridation process.
The surface of the substrate is cleaned through the steps, impurities are prevented from being doped into the epitaxial wafer, and the growth quality of the epitaxial wafer is improved.
Step 202: an N-type semiconductor layer, a stress release layer, an electronic adjusting layer, an active layer and a P-type semiconductor layer are sequentially grown on a substrate.
In this embodiment, the material of the electronic adjustment layer is N-type doped aluminum gallium nitride, and the doping concentration of the N-type dopant in the electronic adjustment layer gradually decreases along the stacking direction of the gan-based led epitaxial wafer.
Alternatively, the growth conditions of the electronic adjustment layer may be the same as those of the stress relaxation layer, and the growth conditions include a growth temperature and a growth pressure. The same growth conditions are adopted, and the method is convenient to realize.
Preferably, the growth temperature of the electronic adjustment layer can be 750-900 ℃, the growth pressure of the electronic adjustment layer can be 100-300 torr, and the obtained electronic adjustment layer has better crystal quality.
Specifically, this step 202 may include:
the first step, controlling the temperature to 950 ℃ -1150 ℃ (preferably 1050 ℃), controlling the pressure to 50 torr-450 torr (preferably 250torr), and growing an N-type semiconductor layer on a substrate;
secondly, controlling the temperature to be 750-900 ℃ (preferably 820 ℃) and the pressure to be 100-300 torr (preferably 200torr), and growing a stress release layer on the N-type semiconductor layer;
thirdly, controlling the temperature to be 750-900 ℃ (preferably 820 ℃) and the pressure to be 100-300 torr (preferably 200torr), and growing an electronic adjusting layer on the stress releasing layer;
fourthly, growing an active layer on the electronic adjusting layer; the growth temperature of the quantum well is 750 ℃ -840 ℃ (800 ℃ is preferred), and the growth pressure is 50 torr-550 torr (300 torr is preferred); the growth temperature of the quantum barrier is 820 ℃ -950 ℃ (preferably 880 ℃), and the growth pressure is 50-550 torr (preferably 300 torr);
and fifthly, controlling the temperature to be 800-1100 ℃ (preferably 950 ℃) and the pressure to be 20-400 torr (preferably 210torr), and growing the P-type semiconductor layer on the active layer.
Optionally, before the first step, the growing method may further include:
a buffer layer is formed on a substrate.
Accordingly, an N-type semiconductor layer is grown on the buffer layer.
Specifically, growing a buffer layer on a substrate may include:
controlling the temperature to be 400-600 ℃ (preferably 500 ℃), and the pressure to be 400-600 torr (preferably 500torr), and growing a buffer layer on the substrate;
controlling the temperature to be 1000-1200 ℃ (preferably 1100 ℃) and the pressure to be 400-600 torr (preferably 500torr), and carrying out in-situ annealing treatment on the buffer layer for 5-10 minutes (preferably 8 minutes);
alternatively, growing a buffer layer on a substrate may include:
depositing a buffer layer on the substrate by adopting a physical deposition technology;
the high-temperature heat treatment is carried out for 10to 15 minutes in a hydrogen atmosphere.
Preferably, after forming the buffer layer on the substrate, the growing method may further include:
and growing an undoped gallium nitride layer on the buffer layer.
Accordingly, an N-type semiconductor layer is grown on the undoped gallium nitride layer.
Specifically, growing an undoped gallium nitride layer on the buffer layer may include:
the undoped gallium nitride layer is grown on the buffer layer by controlling the temperature to be 900 ℃ to 1120 ℃ (preferably 1010 ℃) and the pressure to be 150torr to 550torr (preferably 300 torr).
Optionally, before the fifth step, the growing method may further include:
an electron blocking layer is grown on the active layer.
Accordingly, a P-type semiconductor layer is grown on the electron blocking layer.
Specifically, growing an electron blocking layer on the active layer may include:
controlling the temperature to be 600-1000 ℃ (preferably 800 ℃) and the pressure to be 50-550 torr (preferably 300torr), and growing an electron blocking layer on the active layer;
preferably, before growing the electron blocking layer on the active layer, the growth method may further include:
a low temperature P-type layer is grown on the active layer.
Accordingly, an electron blocking layer is grown on the low temperature P-type layer.
Specifically, growing the low temperature P-type layer on the active layer may include:
the temperature is controlled to be 500 ℃ to 1200 ℃ (preferably 750 ℃) and the pressure is controlled to be 100torr to 550torr (preferably 300torr), and the low-temperature P type layer is grown on the active layer.
Optionally, after the fifth step, the growing method may further include:
and growing a contact layer on the P-type semiconductor layer.
Specifically, growing a contact layer on the P-type semiconductor layer may include:
the contact layer is grown on the P-type semiconductor layer at a temperature of 850 to 1050 deg.C (preferably 950 deg.C) and a pressure of 100to 300torr (preferably 200 torr).
After the completion of the epitaxial growth, the temperature is lowered to 650 to 850 ℃ (preferably 750 ℃), the epitaxial wafer is annealed in a nitrogen atmosphere for 5 to 15 minutes (preferably 10 minutes), and then the temperature of the epitaxial wafer is lowered to room temperature.
The control of the temperature and the pressure both refer to the control of the temperature and the pressure in a reaction chamber for growing the epitaxial wafer, and specifically refer to the reaction chamber of a Metal-organic Chemical Vapor Deposition (MOCVD) device. During implementation, trimethyl gallium or triethyl gallium is used as a gallium source, high-purity ammonia gas is used as a nitrogen source, trimethyl indium is used as an indium source, trimethyl aluminum is used as an aluminum source, silane is used as an N-type dopant, and magnesium diclocide is used as a P-type dopant.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (9)

1. A gallium nitride-based light emitting diode epitaxial wafer comprises a substrate, an N-type semiconductor layer, a stress release layer, an active layer and a P-type semiconductor layer, wherein the N-type semiconductor layer, the stress release layer, the active layer and the P-type semiconductor layer are sequentially stacked on the substrate; the material of the electronic adjusting layer adopts N-type doped aluminum gallium nitride, and the doping concentration of an N-type dopant in the electronic adjusting layer is 10 degrees from the lamination direction of the gallium nitride-based light emitting diode epitaxial wafer18/cm3Gradually reducing the temperature to 0 ℃, wherein the growth temperature of the electronic adjusting layer is 750-900 ℃, and the growth temperature of the N-type semiconductor layer is 950-1150 ℃.
2. The GaN-based LED epitaxial wafer according to claim 1, wherein the maximum value of the doping concentration of the N-type dopant in the electronic adjustment layer is less than the doping concentration of the N-type dopant in the N-type semiconductor layer, and the minimum value of the doping concentration of the N-type dopant in the electronic adjustment layer is 0.
3. The gallium nitride-based light emitting diode epitaxial wafer according to claim 1 or 2, wherein the number of aluminum atoms in the electron adjustment layer is smaller than the number of gallium atoms in the electron adjustment layer.
4. The GaN-based LED epitaxial wafer according to claim 3, wherein the content of the aluminum component in the electronic adjustment layer gradually increases along the stacking direction of the GaN-based LED epitaxial wafer.
5. The GaN-based LED epitaxial wafer according to claim 3, wherein the content of the aluminum component in the electronic adjustment layer gradually decreases along the stacking direction of the GaN-based LED epitaxial wafer.
6. The GaN-based LED epitaxial wafer according to claim 1 or 2, wherein the thickness of the electronic adjustment layer is 0.5 nm-10 nm.
7. A growth method of a gallium nitride-based light emitting diode epitaxial wafer is characterized by comprising the following steps:
providing a substrate;
sequentially growing an N-type semiconductor layer, a stress release layer, an electronic adjustment layer, an active layer and a P-type semiconductor layer on the substrate;
the electronic adjusting layer is made of N-type doped aluminum gallium nitride, and the doping concentration of an N-type dopant in the electronic adjusting layer is along the layer of the GaN-based light emitting diode epitaxial waferIn the stacking direction of 1018/cm3Gradually reducing the temperature to 0 ℃, wherein the growth temperature of the electronic adjusting layer is 750-900 ℃, and the growth temperature of the N-type semiconductor layer is 950-1150 ℃.
8. The growth method according to claim 7, wherein the growth conditions of the electron adjustment layer are the same as those of the stress relief layer, and the growth conditions include a growth temperature and a growth pressure.
9. The growth method according to claim 8, wherein the growth pressure of the electron adjustment layer is 100to 300 torr.
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