CN107275235B - 包括介电层和包封剂的电子器件封装件 - Google Patents

包括介电层和包封剂的电子器件封装件 Download PDF

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CN107275235B
CN107275235B CN201710217630.8A CN201710217630A CN107275235B CN 107275235 B CN107275235 B CN 107275235B CN 201710217630 A CN201710217630 A CN 201710217630A CN 107275235 B CN107275235 B CN 107275235B
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layer
dielectric layer
carrier
semiconductor
electronic device
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CN107275235A (zh
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E·富尔古特
H·德普克
O·霍尔菲尔德
M·朱尔斯
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

一种方法，包括提供载体，将至少一个半导体芯片布置到载体上，半导体芯片包括在半导体芯片的远离载体的主面上的至少一个接触焊盘，将接触元件施加到接触焊盘上，将介电层施加在载体、半导体芯片和接触元件上，并且将包封剂施加到介电层上。

Description

包括介电层和包封剂的电子器件封装件
技术领域
本公开总体上涉及一种用于制造电子器件封装件的方法、一种电子器件封装件以及一种电子电压转换器模块。本公开特别涉及一种电子器件封装件，例如包括介电层和包封剂的高功率模块，介电层和包封剂共同作用以提高性能和可靠性。
背景技术
在很多技术领域，都需要使用电压或电流转换器，如DC/DC转换器、AC/DC转换器、DC/AC转换器或降压转换器。例如，对于未来的能量供应，智能电网连接分散的可再生能源。在风能的情况下，涡轮机产生AC电力，但是对于传输，需要具有较低能量损失的DC电力。因此，智能电网实质上由具有对应的转换器站的高压直流传输单元组成，其中需要数以万计的高功率模块。同样，在其它技术领域中，使用这样的转换器来产生将要由诸如电机驱动电路等电子电路来使用的电流、电压和/或频率。转换器电路通常包括一个或多个半桥电路，其中每个半桥电路可以由两个半导体功率开关 (例如，功率MOSFET部件或功率绝缘栅双极型晶体管(IGBT)) 以及其它部件(例如，与晶体管部件并联连接的二极管，以及诸如电感和电容之类的无源部件)提供。包含这种电路的电子模块有时会暴露在非常恶劣的条件下，例如高湿度。
发明内容
根据本公开的一方面，一种用于制造电子器件封装件的方法包括提供载体，将至少一个半导体芯片布置到载体上，半导体芯片包括在半导体芯片的远离载体的主面上的至少一个接触焊盘，将接触元件施加到接触焊盘上，将介电层施加到载体、半导体芯片和接触元件上，以及将包封剂施加到介电层上。
根据本公开的一方面，一种电子器件封装件包括至少一个半导体芯片，至少一个半导体芯片包括在其主面上的至少一个接触焊盘，布置在接触焊盘上的接触元件，布置在半导体芯片和接触元件上的介电层，以及布置在介电层上的包封剂。
根据本公开的一方面，一种电子电压转换器模块包括多个半导体晶体管芯片，每个半导体晶体管芯片包括在其主面上的至少一个接触焊盘，布置在每个接触焊盘上的接触元件，布置在半导体晶体管芯片和接触元件上的介电层，以及布置在介电层上的包封剂，其中半导体晶体管芯片电互连以形成电机驱动电路、半桥电路、 AC/AC转换器电路、DC/AC转换器电路、DC/DC转换器电路和降压转换器电路中的一项或多项。
通过阅读以下详细描述并且考虑到附图，本领域技术人员可以认识到附加的特征和优点。
附图说明
附图被包括以提供对示例的进一步理解，并且附图被并入并且构成本说明书的一部分。附图示出了示例，并且与描述一起用于解释示例的原理。通过参考以下详细描述可以更好地理解其他示例和示例的很多预期优点。
附图的元件不一定相对于彼此成比例。相同的附图标记表示对应的相似部件。
图1示出了根据第一方面的用于制造电子器件封装件的方法的流程图。
图2A-2E以示意形式示出了将介电层施加到载体上的示例，特别是向载体上沉积介电层的材料，包括灌封/填充 (2A)、旋涂(2B)、喷雾/射流涂覆或静电和/或雾化涂覆(2C)、层压(2D)和浸渍(2E)。
图3A-3D示出了用于说明根据第一方面的用于制造电子器件封装件的示例性方法的示意性截面侧视图，其中使用铜板或引线框作为载体。
图4A-4D示出了用于说明根据第一方面的用于制造电子器件封装件的示例性方法的示意性截面侧视图，其中使用直接键合铜(DCB)或绝缘金属基底(IMS)作为载体。
图5A-5C示出了用于说明用于制造电子器件封装件的示例性方法的示意性截面侧视图，其中使用直接键合铜 (DCB)或绝缘金属基底(IMS)作为载体，并且使用焊线将上部接触元件与DCB或IMS连接。
图6示出了通过图3A-3D所示的方法制造的电子器件封装件的示意性截面侧视图，其中载体在包封之后被去除。
图7示出了通过图4A-4D所示的方法制造的电子器件封装件的示意性截面侧视图，其中载体在包封之后被去除。
图8示出了通过图5A-5C所示的方法制造的电子器件封装件的示意性截面侧视图，其中载体在包封之后被去除。
具体实施方式
现在参考附图描述各方面和示例，其中通常使用相同的附图标记来指代相同的元件。在下面的描述中，为了解释的目的，阐述了很多具体细节，以提供对示例的一个或多个方面的透彻理解。然而，对于本领域技术人员显而易见的是，可以以较小程度的具体细节来实践示例的一个或多个方面。在其他情况下，以示意图形式示出了已知的结构和元件，以便于描述示例的一个或多个方面。应当理解，在不脱离本公开的范围的情况下，可以利用其他示例并且可以进行结构或逻辑上的改变。还应当注意，附图不是按比例的或不必是按比例的。
在下面的详细描述中，参考形成其一部分的附图，并且其中通过示例的方式示出了可以实践本公开的具体方面。在这点上，可以参考所描述的图的取向来使用诸如“顶”、“底”、“前”、“后”等方向术语。由于所描述的装置的部件可以被定位在多个不同的取向中，所以方向术语可以用于说明的目的，而不是限制。应当理解，在不脱离本公开的范围的情况下，可以利用其他方面以及进行结构或逻辑上的改变。因此，下面的详细描述不被认为是限制性的，并且本公开的范围由所附权利要求限定。
此外，虽然可以仅针对若干实现中的一个来公开示例的特定特征或方面，但是将这样的特征或方面可以与其他实现的一个或多个其他特征或方面组合，这对于任何给定或特定应用是需要的且有利的。此外，在详细描述或权利要求书中使用术语“包含”、“具有”、“含有”或其它变体，其意图以与术语“包括”类似的方式是包括性的。可以使用术语“耦合”和“连接”以及派生词。应当理解，这些术语可以用于指示两个元件彼此协作或相互作用，而不论它们处于直接的物理或电接触，还是它们并不彼此直接接触。此外，术语“示例性”仅表示作为示例，而不是最佳或最优的。因此，下面的详细描述不被认为是限制性的，并且本公开的范围由所附权利要求限定。
用于制造电子器件封装件的方法、电子器件封装件和电子电压转换器模块的示例可以使用各种类型的半导体器件。这些示例可以使用以半导体管芯或半导体芯片实现的晶体管器件，其中半导体管芯或半导体芯片可以以由半导体晶片制造并且由半导体晶片切出的半导体材料块的形式来提供，或者以其中已经进行了进一步的工艺步骤的另一种形式来提供，例如向半导体管芯或半导体芯片施加包封层。这些示例也可以使用水平或竖直晶体管器件，其中这些结构可以以如下形式提供：其中晶体管器件的所有接触元件设置在半导体管芯的主面之一上(水平晶体管结构)，或者以如下形式提供：其中至少一个电接触元件布置在半导体管芯的第一主面上并且至少一个其它电接触元件布置在与半导体管芯的第一主面相对的第二主面上(竖直晶体管结构)，例如，MOS晶体管结构或IGBT(绝缘栅双极型晶体管)结构。只要晶体管芯片被配置为功率晶体管芯片，并且如果还将驱动器芯片集成到封装件中，则下面进一步公开的电子器件封装件的示例可以被分类为智能功率模块(IPM)。
在任何情况下，电子器件(例如，半导体管芯或半导体芯片) 可以包括在其一个或多个外表面上的接触元件或接触焊盘，其中接触元件与相应半导体管芯的电路(例如，晶体管)电连接并且用于将半导体管芯电连接到外部。接触元件可以具有任何期望的形式或形状。例如，它们可以具有在半导体管芯的外表面上的焊区的形式，即平坦的接触层。接触元件或接触焊盘可以由任何导电材料制成，例如金属，如铝、金、铜、或金属合金、或导电有机材料、或导电半导体材料。接触元件也可以形成为上述或其它材料中的一项或多项的层堆叠，以便产生例如NiPdAu的堆叠。
电子器件封装件的示例可以包括其中嵌入有半导体晶体管芯片的包封剂或包封材料。包封材料可以是任何电绝缘材料，例如任何种类的模塑材料、任何种类的树脂材料、或任何种类的环氧材料、双马来酰亚胺、或氰酸酯。包封材料也可以是聚合物材料、聚酰亚胺材料、热塑性材料、陶瓷材料和玻璃材料。包封材料还可以包括任何上述材料，并且还包括嵌入其中的填料材料，例如导热添加物。这些填料添加物可以由SiO、Al2O3、ZnO、AlN、BN、MgO、 Si3N4、或陶瓷、或诸如Cu、Al、Ag或Mo等金属材料制成。此外，填料添加物可以具有纤维的形状，并且可以由例如碳纤维或纳米管制成。
虽然用于制造电子器件封装件的方法被描述为具有特定顺序的方法步骤，但是应当提及，本领域技术人员可以采用任何其它适当的顺序的方法步骤。还应当提及，与所描述的方法有关的任何评论、附注或特征应当被理解为还公开了由这样的评论、附注或特征获得或由此产生的装置，即使这样的装置未被明确描述或在附图中图示。此外，与装置相关的任何评论、附注或特征也应当被理解为还公开了用于提供或制造相应装置特征的方法步骤。
图1示出了根据第一方面的用于制造电子器件封装件的方法的流程图。该方法包括提供载体(s1)，将至少一个半导体芯片布置到载体上，半导体芯片包括在主面上的至少一个接触焊盘(s2)，将接触元件施加到接触焊盘上(s3)，将介电层施加到载体、半导体芯片和接触元件上(s4)，以及将包封剂施加到介电层上(s5)。
根据第一方面的方法的示例，选择介电层的材料使得其可以以最佳可能的方式用作半导体芯片和包封层之间的应力缓冲区，此外，使得其可以以最佳可能的方式用作能够防止从环境渗透的湿气的屏障，并且也可以以最佳可能的方式将半导体芯片电隔离，即布置在半导体芯片中的电气装置。
根据第一方面的方法的示例，介电层是以下中的一项或多项：聚合物层、聚酰亚胺层、聚对二甲苯层、聚苯并恶唑(PBO)层、树脂层、特别是环氧树脂层、硅树脂层、旋涂玻璃层、以及混合材料，即一种或多种上述材料的复合材料，例如表现出相似、不同或重叠属性的材料的化合物，例如PBO和聚酰亚胺。特别地，可以使用这样的混合材料，其结合相对或相反的特性，例如有机和无机材料。介电层也可以是半导体氧化物或半导体氮化物或半导体氮氧化物层，如SiO、SiN或SiON层。
根据第一方面的方法的示例，介电层不包括任何填料材料或填料添加物，而是实质上是任何一种上述材料的均质层。然而，同样可能的是，介电层包括填料材料或填料添加物，其中填料添加物可以被选择为使得它们满足特定的功能，例如离子捕获、阻燃、软化或塑化。
根据第一方面的方法的示例，介电层包括以下特性中的一项或多项：在2至5的范围内的介电常数、在100至500V/μm的范围内的介电强度、在0.005至0.03的范围内的损耗因子、以及在0.1至 5.0GPa范围内的弹性模量，其中损耗因子是当用于交变场时电绝缘材料中的介电损耗的量度。
根据第一方面的方法的示例，施加介电层包括沉积介电层，其中沉积介电层包括以下中的一项或多项：旋涂、喷涂、或射流涂覆、或静电和/或雾化涂覆、波涂、灌封、填充、层压、特别是真空层压、浸渍、物理气相沉积(PVD)、化学气相沉积(CVD)、或印刷。
根据第一方面的方法的示例，施加介电层还包括加热或固化沉积的介电层。根据其另一示例，加热温度在高达500℃、特别是80 ℃至400℃、特别是150℃至280℃的范围内，加热时间在长达5h、特别是0.5h至3.0h、特别是1h至2h的范围内。根据其另一示例，在加热之前，可以执行预热或预烘烤，例如在80℃至140℃、特别是100℃至120℃的范围内的预热温度并且在长达20分钟的范围内的加热时间。预热步骤可以被证明有利于对沉积的介电层进行除湿以及蒸发溶剂。
根据第一方面的方法的示例，施加介电层包括施加具有不同材料或不同属性中的一项或多项的两个或多个介电层的堆叠。因此，两个或多个介电层的材料是不同的，或者两个或多个介电层的材料相似或相当但其属性不同。如果材料彼此不同，则一般来说，它们的属性也会不同。如果材料相似或相当，其属性也可能不同。例如，在聚酰亚胺层或其他类型的聚合物层的情况下，它们可以在沉积之后以不同的方式处理，使得形成聚合物或原子的网络的程度、特别是分子的聚合或交联的程度(在聚酰亚胺层的情况下，是聚酰亚胺层的酰亚胺化)可以彼此不同。根据其示例，该方法还可以包括沉积第一介电层并且利用第一条件集合处理所沉积的第一介电层，以及沉积第二介电层并且利用第二条件集合处理所沉积的第二介电层，其中第一条件集合不同于第二条件集合。作为其另一示例，第一条件集合包括第一加热温度和第一加热时间，第二条件集合包括第二加热温度和第二加热时间。例如，如果第一介电层由第一聚酰亚胺层构成，并且第一加热温度在300℃至350℃的范围内，则结果将是酰亚胺化程度等于或接近100％的聚酰亚胺层。例如，如果第二介电层也由聚酰亚胺层构成，并且第二加热温度在200℃至 250℃的范围内，则结果将是具有显著小于100％(即95％甚至更小)的亚胺化程度的第二聚酰亚胺层。也可以为两个不同层选择相同的加热温度，但加热时间不同。此外，沉积两个或多个介电层并且利用不同条件处理它们的所描述的变体也可以应用于用作介电层的上述其它材料。根据具体实例，第一下部层可以是硅树脂层，第二上部层可以是聚酰亚胺层。
根据第一方面的方法的示例，施加包封剂包括施加基质材料，所述基质材料包括以下中的一项或多项：树脂、特别是环氧树脂、环氧硅树脂、或环氧聚酰亚胺、双马来酰亚胺、氰酸酯、或热塑性塑料。根据其示例，基质材料包括嵌入在其中的填料添加物，其中填料添加物可以由以下各项制成：SiO、Al2O3、MgO、AlN、 Si3N4、BN、或另一陶瓷材料。也可以选择填料添加物，使得它们满足特定的功能，例如离子捕获、阻燃、软化或塑化、或应力释放。
根据第一方面的方法的示例，施加包封剂包括传递模塑、压缩模塑、真空浇铸、或层压中的至少一种。
根据第一方面的方法的示例，包封剂的厚度在0.1mm至 10mm、特别是1mm至5mm的范围内。应当注意，在这方面，在大多数情况下，包封剂被施加到不是平面、而是或多或少复杂的三维结构的表面，使得上述值可以指代在这种三维结构的任何位置上的包封剂的厚度。
根据第一方面的方法的示例，在施加介电层之后，即在沉积和固化介电层之后，可以进行后处理以提高表面纯度，并且因此增加介电层关于稍后要沉积的包封层的粘合性能。后处理可以包括例如用于增加包封层的粘附条件的等离子体处理或等离子体激活。后处理可以替代地或另外地包括沉积特殊粘合促进剂层，其可以是例如硅烷层或氧化锌铬层。
根据第一方面的方法的示例，介电层可以被构造成使得其包含任何所需横向尺寸和数目的开口或通孔。如果介电层以例如层堆叠的形式作为整体被沉积，则可以在沉积层压层之前或在沉积层压层之后进行结构化。如果通过如上所述的任何方法以顺序的方式沉积介电层，则可以通过例如使用具有开口的掩模在沉积介电层期间进行结构化，或者可以在整个区域上沉积介电层之后进行结构化，作为其另一示例，可以在固化之前或之后进行结构化。结构化可以例如通过激光烧蚀或激光直接成像或通过光刻或剥离技术来进行。
根据第一方面的方法的示例，半导体芯片均包括晶体管，晶体管包括栅极接触、发射极接触和集电极接触，并且晶体管均被配置为利用1200V以上的发射极集电极电压工作。然而，本公开不限于该电压范围，而是也可应用于低于1200V的电压等级，或者例如在汽车、航空航天或医疗领域，或者一般在可靠性是一个重要因素、甚至是最重要因素的技术领域。
根据第一方面的方法的示例，载体可以是在施加包封剂之后被去除的辅助或临时载体，使得载体不会是制造的电子器件封装件的一部分。
根据第一方面的方法的示例，载体将不被去除并且将是制造的电子器件封装件的一部分，在这种情况下载体用作芯片载体。芯片载体可以是导电载体，例如金属载体、铜板、钼板、或引线框、或直接键合铜(DCB)、或绝缘金属基底(IMS)。然而，应当提及的是，在这种情况下，也可以使用附加的辅助或临时载体，芯片载体布置在附加的辅助或临时载体上。这提供了将不同种类的芯片载体施加到辅助或临时载体上的可能性。芯片或芯片模块可以在5面包封，即在其4个侧面和上部主面上。
图2A-2E以示意形式示出了沉积介电层的不同方法。在图2A-2D中，示出了包括载体11和布置在载体11上的多个半导体芯片12的电子器件模块10。此外，电接触元件(未示出)布置到半导体芯片12上。图2A示出了将液体介电材料13灌封或填充到电子器件模块10上的过程。分配器14位于电子器件模块10上方，并且将液体材料13输送到电子器件模块10的上部主面上，其中液体材料13分布在整个上表面上。图2B示出了旋涂的过程，其中实质上除了图2A的过程之外，电子器件模块10如箭头所示围绕竖直轴旋转，以便将液体材料13最好地分配在电子器件模块10的上表面上。图2C示出了通过使用分配器24喷射或射流涂覆液体或部分干燥的材料13的过程，分配器24能够以喷射喷嘴的形式输送液体材料13，该喷射喷嘴在空间角度上延伸以覆盖电子器件模块10 的上表面的一定区域。此外，如箭头所示，分配器24或电子器件模块10可以横向移动。图2D示出了将介电层层压到电子器件模块10上的方法。在该方法中，通过使用粘合剂将预制的介电层压箔23沉积到电子器件模块10的上表面上。图2E示出了将电子器件模块10 浸入容纳要沉积的介电材料的液体33的容器中的过程。介电材料在浸入液体33的浴液中后将附着到电子器件模块10的上表面。
应当提及的是，在图2A-2E的表示中，附图标记12也可以指代均包括多个半导体芯片的半导体模块，并且附图标记10可以指代在其上沉积有多个这样的半导体模块12的芯片载体面板。在制造过程结束时或在包封芯片载体面板之后，获得包封剂面板，并且包封剂面板可以被单片化以获得多个单独的半导体模块12。也可以不包封芯片载体面板，而是在沉积介电层之后对芯片载体面板进行单片化并且此后包封各个半导体模块。这可以通过以下方式来进行：将各个半导体模块放置到临时载体上，然后将包封剂施加到临时载体和半导体模块上，从而获得包封剂面板。此后，包封剂面板可以被单片化成多个包封的半导体模块。
此外，在图2A-2E的表示中，半导体芯片12不一定相同，并且不一定是晶体管芯片。它们也可以是例如其中创建有如上所述的智能功率模块(IPM)的传感器芯片或逻辑芯片。
根据介电层的材料，也可以采用其他沉积方法，例如真空层压或印刷。在例如聚对二甲苯作为介电层的材料的情况下，可以使用物理气相沉积(PVD)或静电和/或雾化涂覆或离子雾化来沉积聚对二甲苯层。介电材料也可以以颗粒形式、特别是塑料颗粒的形式沉积。在其他情况下也可以使用化学气相沉积(CVD)作为沉积方法。
如上所述，在沉积介电层之后，其可以在例如200℃至400℃的温度范围内被固化，例如在间歇式炉中持续1h至4h的固化时间。固化气氛可以是真空度为500毫巴或甚至低于或高于该值的低真空和/或高真空的氮气(N2)。该工艺步骤通常通过酰亚胺化、聚合、 x-链的聚合物分子或原子或任何类型的化学反应来产生并且保证最终的材料属性。在这个固化工艺之前，可以预先烘烤介电层，并且可以在施加包封剂之前进行表面处理，例如等离子体活化、湿化学处理、或施加粘合促进剂。预烘烤将确保溶剂蒸发和湿气去除，并且等离子体激活将确保介电层和包封剂材料之间的充分粘附。
图3A-3D示出了用于说明第一方面的示例性方法的示意性截面侧视图。根据图3A，在该示例中提供了芯片载体30，其可以由引线框架或铜板构成。为了清楚起见，芯片载体30也可以施加到图中未示出的辅助或临时载体上。例如，在辅助载体上制造包括多个半导体模块的面板的情况下，可以在辅助载体上布置不同种类的芯片载体30。可以在制造过程中稍后去除辅助载体。通过使用中间焊料或粘合层31向芯片载体30上沉积多个半导体芯片32。芯片32可以具有在其上表面上的电接触焊盘32A，并且例如在竖直晶体管的情况下也可以具有在其下表面上的电接触焊盘。在芯片32 的上表面上，接触元件33被施加到接触焊盘32A上。接触元件33 可以具有间隔元件的形式，并且可以由以铜板的形式作为整体电镀或施加的铜来制造。接触焊盘32A可以是例如绝缘栅双极型晶体管 (IGBT)的发射极接触焊盘。也可以在半导体芯片32(未示出)的上表面上设置IGBT的栅极接触元件，并且可以施加栅极接触层，栅极接触层提供与半导体芯片32的所有栅极接触焊盘的连接。
根据图3B，通过如前所述的任何沉积方法，将介电层34沉积到如图3A所示的中间产品的上表面上，即接触元件33、半导体 32、焊料层31和载体30的上表面上。
根据图3C，在固化介电层34之后，将包封层或包封剂35沉积到如图3B所示的中间产品上。包封剂35可以通过例如传递模塑、压缩模塑、真空浇铸或层压来施加。
根据图3D，通过例如研磨部分地从上方去除包封层35以暴露接触元件33，使得它们可以连接到另外的外部电连接器。如在下面的示例中将看到的，研磨不是必需的，而是也可以采取其他措施来将接触元件33连接到外部电连接器。
图4A-4D示出了用于说明根据第一方面的用于制造电子器件封装件的示例性方法的示意性截面侧视图。根据图4A，以例如直接键合铜(DCB)40的形式提供载体40。DCB 40包括基底40A以及第一金属层40B和第二金属层40C，基底40A包括绝缘的电介质或陶瓷层或瓦片，第一金属层40B在基底40A的下表面上，第二金属层40C在基底40A的上表面上。根据示例，载体40 可以包括以下中的一项或多项：直接键合铜(DCB)基底、直接键合铝(DAB)基底、和活性金属钎焊基底，其中基底可以包括陶瓷层、特别是以下中的一项或多项：AlN、Al2O3、或介电层、特别是 Si3N4。载体40也可以指代隔离的金属基底(IMS)，其中类似于 DCB，中间绝缘层夹在两个金属层之间，其中中间绝缘层包括基质材料、特别是与填料添加物(例如，BN添加物或如上文关于包封剂所述的任何其他添加物)的复合物。基质材料可以是在本公开内容中结合包封剂提及的材料中的任何一种。DCB和IMS允许到散热器的电气隔离，同时允许到散热器的良好热传递，以及并且允许被施加到DCB或IMS上的半导体芯片之间的电隔离。
半导体芯片42以与结合图3A所描述的相同的方式通过使用中间焊料或粘合剂层41沉积在载体40的上表面上。此外，电接触元件43附接到半导体芯片42的接触焊盘42A，其也对应于先前结合图3A描述的接触元件的布置。
根据图4B，介电层44以与以上结合图3B所述的相同的方式被沉积到图4A的中间产品上。
根据图4C，包封层或包封剂45以与以上结合图3C所述的相同的方式被施加到图4B的中间产品。
根据图4D，开口45A形成在包封剂45的上表面中，开口45A 从上表面向下延伸到电接触元件43，以允许在稍后的步骤中将接触元件43连接到另外的外部电连接器。开口45A的形成可以通过激光钻孔进行，激光钻孔能够不仅去除或者消除包封剂45的材料还能够去除或者消除介电层44的材料。
图5A-5C示出了用于说明根据第一方面的用于制造电子器件封装件的示例性方法的示意性截面侧视图。根据图5A，可以提供可以与图4A-4D的载体40相似或相当的载体50，载体50因此可以具有DCB的形式。然而，载体50也可以与图3A-3D的载体30相似或相当。以与前面结合图3A或图4A所述的相同的方式通过使用中间焊料或粘合剂层51将半导体芯片52沉积到载体50的上表面上。代替仅一个半导体芯片52，也可以将多个半导体芯片52施加到载体 50的上表面上。以与前面结合图3A和4A所述的相同的方式将电接触元件53施加到半导体芯片52的接触焊盘52A。然后，键合线54 连接在接触元件53和载体50的区域的上表面之间。另一键合线54 可以连接在另一接触元件53和载体50的另一区域的上表面之间。应当提到，代替键合线54，也可以将夹具用作接触元件53和载体 50的区域的上表面之间的电连接。
根据图5B，然后以与前面结合图3B和4B所述的相同的方式将介电层55沉积到图5A的中间产品的上表面上。结果，介电层55也被施加到键合线54的上表面。
根据图5C，包封层56以与前面结合图3C和4C所述的相同的方式被施加到图5B的中间产品。
本公开还涉及根据第二方面的电子器件封装件。根据第二方面的电子器件封装件包括载体、布置在载体上的至少一个半导体芯片，半导体芯片包括在半导体芯片的远离载体的主面上的至少一个接触焊盘，布置在接触焊盘上的接触元件，布置在载体、半导体芯片和接触元件上或上方的介电层，以及布置在介电层上的包封层。
根据第二方面的电子器件封装件的其它示例可以通过并入以上结合根据第一方面的方法描述的示例或特征来形成。
根据第二方面的电子器件封装件可以例如具有如图3D、4D或 5C所示的形式，分别包括载体30、40或50、具有接触焊盘32A、42A或52A的至少一个半导体芯片32、42或52、接触元件33、43 或53、介电层34、44或55、以及包封层35、45或56。
根据第二方面的电子器件封装件也可以具有如图6、图7或图8 所示的形式，其指代如图3D、4D和5C所示的相应载体30、40或 50仅用作在包封之后去除的辅助载体的情况。图6对应于图3D，图 7对应于图4D，图8对应于图5C，其中所有附图标记被借用并且具有与之前相同的含义。
本公开还涉及根据第三方面的电子电压转换器模块。根据第三方面的电子电压转换器模块包括根据第二方面的电子器件封装件，其中半导体芯片是被电互连以形成以下中的一项或多项的半导体晶体管芯片：电机驱动电路、半桥电路、AC/AC转换器电路、DC/AC 转换器电路、DC/DC转换器电路和降压转换器电路。
根据第三方面的电子电压转换器模块的其它示例可以通过并入前面结合根据第一方面的方法或根据第二方面的电子器件封装件描述的示例和特征来形成。
虽然已经关于一个或多个实现示出和描述了本发明，但是在不脱离所附权利要求的精神和范围的情况下，可以对所示示例进行改变和/或修改。特别是关于由上述部件或结构(部件、装置、电路、系统等)执行的各种功能，用于描述这些部件的术语(包括对“装置”的引用)旨在对应于(除非另有说明)执行所述部件的规定功能的任何部件或结构(例如，功能上相同)，即使在结构上不等同于执行在本文所示的本发明的示例性实现中的功能的所公开的结构。

Claims (23)

1.一种用于制造电子器件封装件的方法，具有：
提供载体；
将至少一个半导体芯片布置到所述载体上，所述半导体芯片具有在所述半导体芯片的主面上的至少一个接触焊盘；
将接触元件施加到所述接触焊盘上；
将键合线连接在所述载体的区域的上表面与所述接触元件之间；
将介电层连续地直接施加在所述载体、所述半导体芯片、所述键合线和所述接触元件上；以及
将包封剂施加到所述介电层上。
2.根据权利要求1所述的方法，其中
所述介电层是以下中的一项或多项：聚合物层、聚酰亚胺层、聚对二甲苯层、聚苯并恶唑层、树脂层、硅树脂层、旋涂玻璃层、以及具有上述材料中的一种或多种的混合材料或复合材料的层、或者半导体氧化物层、半导体氮化物层或半导体氮氧化物层。
3.根据权利要求1或2所述的方法，其中
所述介电层具有以下属性中的一项或多项：
在2至5的范围内的介电常数，
在100V/μm至500V/μm的范围内的介电强度，
在0.005至0.03的范围内的损耗因子，以及
在0.1GPa至5.0GPa的范围内的弹性模量。
4.根据权利要求1或2所述的方法，还具有：
执行施加所述介电层，使得所述介电层具有在2μm至100μm的范围内的厚度。
5.根据权利要求4所述的方法，还具有：
施加所述介电层具有沉积所述介电层，其中沉积所述介电层具有以下中的一项或多项：旋涂、喷涂、射流涂覆、静电涂覆和/或雾化涂覆或离子雾化、波涂、灌封、填充、层压、浸渍、物理气相沉积、化学气相沉积、或印刷。
6.根据权利要求5所述的方法，还具有：
施加所述介电层还具有加热或固化所沉积的介电层。
7.根据权利要求5所述的方法，其中
施加所述介电层具有施加具有不同材料或不同属性中的一项或多项的两个或更多个介电层的堆叠。
8.根据权利要求6或7所述的方法，还具有：
沉积第一介电层并且在第一条件集合下处理所沉积的第一介电层，以及沉积第二介电层并且在第二条件集合下处理所沉积的第二介电层，其中所述第一条件集合不同于所述第二条件集合。
9.根据权利要求8所述的方法，其中
所述第一条件集合具有第一加热温度和第一加热时间，并且所述第二条件集合具有第二加热温度和第二加热时间。
10.根据权利要求1或2所述的方法，还具有：
施加所述包封剂具有施加基质材料，所述基质材料具有以下中的一项或多项：树脂、环氧硅树脂、或环氧聚酰亚胺、双马来酰亚胺、氰酸酯、或热塑性塑料。
11.根据权利要求1或2所述的方法，还具有：
施加所述包封剂具有施加基质材料，其中所述基质材料具有嵌入在所述基质材料中的填料添加物，所述填料添加物由以下各项制成：SiO、Al2O3、ZnO、MgO、AlN、Si3N4、BN、陶瓷材料、或金属材料。
12.根据权利要求1或2所述的方法，还具有：
通过传递模塑、压缩模塑、真空浇铸、或层压来施加所述包封剂。
13.一种电子器件封装件，具有：
至少一个半导体芯片，具有在所述至少一个半导体芯片的主面上的至少一个接触焊盘；
布置在所述接触焊盘上的接触元件；
被连接到所述接触元件的键合线；
连续地直接布置在所述半导体芯片、所述键合线和所述接触元件上的介电层；以及
布置到所述介电层上的包封剂。
14.根据权利要求13所述的电子器件封装件，还具有载体，其中所述至少一个半导体芯片布置到所述载体上。
15.根据权利要求14所述的电子器件封装件，其中所述载体是传导性载体、直接键合铜、或绝缘金属基底、或者辅助或临时载体。
16.根据权利要求13到15中的任一项所述的电子器件封装件，其中
所述介电层是以下中的一项或多项：聚酰亚胺层、聚对二甲苯层、聚苯并恶唑层、树脂层、硅树脂层、和旋涂玻璃层、以及具有上述材料中的一种或多种的混合材料或复合材料的层、或者半导体氧化物层、半导体氮化物层或半导体氮氧化物层。
17.根据权利要求13到15中的任一项所述的电子器件封装件，其中所述介电层具有以下属性中的一项或多项：
在2至5的范围内的介电常数，
在100V/μm至500V/μm的范围内的介电强度，
在0.005至0.03的范围内的损耗因子，以及
在0.1GPa至5.0GPa的范围内的弹性模量。
18.根据权利要求13到15中的任一项所述的电子器件封装件，其中所述介电层具有在2μm至100μm的范围内的厚度。
19.根据权利要求13到15中的任一项所述的电子器件封装件，其中所述介电层包括具有不同材料或不同属性中的一项或多项的两个或更多个介电层的堆叠。
20.根据权利要求13到15中的任一项所述的电子器件封装件，其中所述包封剂具有基质材料，所述基质材料具有以下中的一项或多项：树脂、环氧硅树脂、或环氧聚酰亚胺、双马来酰亚胺、氰酸酯、或热塑性塑料。
21.一种电子电压转换器模块，具有：
载体：
布置在所述载体上的多个半导体晶体管芯片，所述半导体晶体管芯片中的每个半导体晶体管芯片具有在所述半导体晶体管芯片的远离所述载体的主面上的至少一个接触焊盘；
布置在所述接触焊盘中的每个接触焊盘上的接触元件；
被连接在所述载体的区域的上表面与所述接触元件之间的键合线；
连续地直接布置在所述载体、所述半导体晶体管芯片、所述键合线和所述接触元件上的介电层；以及
布置在所述介电层上的包封剂；
其中所述半导体晶体管芯片电互连以形成以下中的一项或多项：电机驱动电路、半桥电路、AC/AC转换器电路、DC/AC转换器电路、DC/DC转换器电路、和降压转换器电路。
22.根据权利要求21所述的电子电压转换器模块，其中
所述半导体晶体管芯片被配置为以下中的一项或多项：功率晶体管芯片、MOSFET芯片、竖直晶体管芯片、或绝缘栅双极型晶体管芯片。
23.根据权利要求21或22所述的电子电压转换器模块，其中
所述半导体晶体管芯片均包括栅极接触、发射极接触和集电极接触，并且所述半导体晶体管芯片均被配置为利用1200V以上的发射极集电极电压工作。
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Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10897824B2 (en) * 2017-10-30 2021-01-19 Baker Hughes, A Ge Company, Llc Encapsulation of downhole microelectronics and method the same
EP3499560B1 (en) 2017-12-15 2021-08-18 Infineon Technologies AG Semiconductor module and method for producing the same
DE102018207955B4 (de) 2018-05-22 2023-05-17 Schweizer Electronic Ag Leiterplattenmodul mit integriertem leistungselektronischen Metall-Keramik-Modul sowie Verfahren zu dessen Herstellung
FR3084964A1 (fr) * 2018-08-09 2020-02-14 Universite Toulouse Iii - Paul Sabatier Dispositif electronique presentant une isolation electrique multicouche, et procede de fabrication correspondant.
US11232993B2 (en) * 2019-05-02 2022-01-25 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
EP3852132A1 (en) * 2020-01-20 2021-07-21 Infineon Technologies Austria AG Additive manufacturing of a frontside or backside interconnect of a semiconductor die
WO2021167904A1 (en) * 2020-02-17 2021-08-26 Stephen Sampayan Partial discharge suppression in high voltage solid-state devices
EP4053894A1 (en) * 2021-03-05 2022-09-07 Infineon Technologies AG A semiconductor device comprising a semiconductor die and a carrier both covered by a parylene coating
DE102021202222A1 (de) 2021-03-08 2022-09-08 Schott Ag Verbundmaterial
EP4227995A1 (en) * 2022-02-09 2023-08-16 Hitachi Energy Switzerland AG Power electronics module and method for its manufacturing
EP4280276A1 (en) * 2022-05-19 2023-11-22 Infineon Technologies Austria AG An electronic device module and a device module both with increased reliability due to an adhesion promoter layer

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1170474A (zh) * 1994-12-16 1998-01-14 西方化学公司 用丝网印刷的方法形成聚酰亚胺涂层
CN101834146A (zh) * 2009-03-13 2010-09-15 精材科技股份有限公司 电子元件封装体及其形成方法
CN104377138A (zh) * 2013-08-12 2015-02-25 英飞凌科技股份有限公司 具有背面管芯金属化的模制的半导体封装

Family Cites Families (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1982003727A1 (en) * 1981-04-21 1982-10-28 Seiichiro Aigoo Method of making a semiconductor device having a projecting,plated electrode
DE3619081A1 (de) 1986-06-06 1987-12-10 Bayer Ag Spritzgusskoerper und verfahren zu seiner herstellung
EP0342681B1 (en) * 1988-05-19 1995-08-09 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing an electrical device
US5208467A (en) * 1988-07-28 1993-05-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a film-covered packaged component
JPH0244738A (ja) * 1988-08-05 1990-02-14 Semiconductor Energy Lab Co Ltd 電子装置作製方法
US5164816A (en) 1988-12-29 1992-11-17 Hitachi Chemical Co., Ltd. Integrated circuit device produced with a resin layer produced from a heat-resistant resin paste
US5438222A (en) * 1989-08-28 1995-08-01 Semiconductor Energy Laboratory Co., Ltd. Electronic device with plural pad connection of semiconductor chip to leads
US5165956A (en) * 1991-09-27 1992-11-24 At&T Bell Laboratories Method of encapsulating an electronic device with a silicone encapsulant
US5656830A (en) * 1992-12-10 1997-08-12 International Business Machines Corp. Integrated circuit chip composite having a parylene coating
US6107690A (en) * 1995-09-26 2000-08-22 Micron Technology, Inc. Coated semiconductor die/leadframe assembly and method for coating the assembly
KR100202668B1 (ko) * 1996-07-30 1999-07-01 구본준 크랙 방지를 위한 반도체 패키지와 그 제조방법 및 제조장치
US6046507A (en) * 1997-12-08 2000-04-04 Advanced Micro Devices Electrophoretic coating methodology to improve internal package delamination and wire bond reliability
US6121130A (en) * 1998-11-16 2000-09-19 Chartered Semiconductor Manufacturing Ltd. Laser curing of spin-on dielectric thin films
US6107184A (en) * 1998-12-09 2000-08-22 Applied Materials, Inc. Nano-porous copolymer films having low dielectric constants
EP1188182B1 (en) * 1999-05-31 2012-08-22 Infineon Technologies AG A method of assembling a semiconductor device package
US6368899B1 (en) 2000-03-08 2002-04-09 Maxwell Electronic Components Group, Inc. Electronic device packaging
EP1215724B1 (en) * 2000-11-20 2012-10-31 Texas Instruments Incorporated Wire bonded semiconductor device with low capacitance coupling
DE10303449B4 (de) 2003-01-29 2007-04-26 Siemens Ag Verfahren zum Umhüllen eines elektronischen Bauelementes
DE10318078B4 (de) 2003-04-17 2007-03-08 Infineon Technologies Ag Verfahren zum Schutz einer Umverdrahtung auf Wafern/Chips
US20070262426A1 (en) * 2004-01-27 2007-11-15 Joachim Mahler Semiconductor Housings Having Coupling Coatings
CN100530714C (zh) * 2004-09-30 2009-08-19 奥斯兰姆奥普托半导体有限责任公司 具有无线接触的光电子器件
CA2539710A1 (en) 2005-03-04 2006-09-04 Zhi Yuan Wang Zwitterionic chromophores and macromolecules containing such chromophores
US7351657B2 (en) * 2005-06-10 2008-04-01 Honeywell International Inc. Method and apparatus for applying external coating to grid array packages for increased reliability and performance
US20100140778A1 (en) * 2005-07-07 2010-06-10 Koninklijke Philips Electronics N.V. Package, method of manufacturing the same and use thereof
DE102005047856B4 (de) * 2005-10-05 2007-09-06 Infineon Technologies Ag Halbleiterbauteil mit in Kunststoffgehäusemasse eingebetteten Halbleiterbauteilkomponenten, Systemträger zur Aufnahme der Halbleiterbauteilkomponenten und Verfahren zur Herstellung des Systemträgers und von Halbleiterbauteilen
DE112006003861B4 (de) * 2006-05-10 2015-09-17 Infineon Technologies Ag Halbleiterbaugruppe und Verfahren zur Herstellung einer Halbleiterbaugruppe
JP2010171271A (ja) * 2009-01-23 2010-08-05 Renesas Technology Corp 半導体装置およびその製造方法
US8313819B2 (en) * 2009-08-12 2012-11-20 Medos International S.A.R.L. Ultra-thin multi-layer packaging
JP2011171436A (ja) * 2010-02-17 2011-09-01 Tdk Corp 電子部品内蔵モジュール及び電子部品内蔵モジュールの製造方法
US8723299B2 (en) * 2010-06-01 2014-05-13 Infineon Technologies Ag Method and system for forming a thin semiconductor device
JP2012004282A (ja) * 2010-06-16 2012-01-05 Mitsubishi Electric Corp 半導体装置
US20130277816A1 (en) * 2012-04-18 2013-10-24 Texas Instruments Incorporated Plastic-packaged semiconductor device having wires with polymerized insulator skin
WO2014110039A2 (en) * 2013-01-08 2014-07-17 Hzo, Inc. Removal of selected portions of protective coatings from substrates
TWM498961U (zh) 2013-07-03 2015-04-11 Rosenberger Hochfrequenztech 高頻寬互連線的熱絕緣結構
US9099567B2 (en) * 2013-11-25 2015-08-04 Freescale Semiconductor, Inc. Packaged semiconductor devices and methods of their fabrication
US9780061B2 (en) * 2014-05-26 2017-10-03 Infineon Technologies Ag Molded chip package and method of manufacturing the same
DE102015109186A1 (de) * 2015-06-10 2016-12-15 Infineon Technologies Ag Halbleiteranordnung, Halbleitersystem und Verfahren zur Ausbildung einer Halbleiteranordnung
US9561953B1 (en) * 2015-08-24 2017-02-07 Infineon Technologies Ag Method of forming a protective coating for a packaged semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1170474A (zh) * 1994-12-16 1998-01-14 西方化学公司 用丝网印刷的方法形成聚酰亚胺涂层
CN101834146A (zh) * 2009-03-13 2010-09-15 精材科技股份有限公司 电子元件封装体及其形成方法
CN104377138A (zh) * 2013-08-12 2015-02-25 英飞凌科技股份有限公司 具有背面管芯金属化的模制的半导体封装

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