CN107154378A - 绝缘层上顶层硅衬底及其制造方法 - Google Patents
绝缘层上顶层硅衬底及其制造方法 Download PDFInfo
- Publication number
- CN107154378A CN107154378A CN201610120565.2A CN201610120565A CN107154378A CN 107154378 A CN107154378 A CN 107154378A CN 201610120565 A CN201610120565 A CN 201610120565A CN 107154378 A CN107154378 A CN 107154378A
- Authority
- CN
- China
- Prior art keywords
- insulating barrier
- semiconductor substrate
- substrate
- top layer
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 156
- 230000004888 barrier function Effects 0.000 title claims abstract description 91
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 53
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 52
- 239000010703 silicon Substances 0.000 title claims abstract description 52
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 40
- 238000000034 method Methods 0.000 title claims abstract description 36
- 239000004065 semiconductor Substances 0.000 claims abstract description 126
- UFHFLCQGNIYNRP-VVKOMZTBSA-N Dideuterium Chemical compound [2H][2H] UFHFLCQGNIYNRP-VVKOMZTBSA-N 0.000 claims abstract description 28
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 21
- 239000001257 hydrogen Substances 0.000 claims abstract description 21
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 20
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 12
- 238000010884 ion-beam technique Methods 0.000 claims abstract description 10
- 230000035772 mutation Effects 0.000 claims abstract description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 9
- 229910017464 nitrogen compound Inorganic materials 0.000 claims description 8
- 150000001875 compounds Chemical class 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 4
- 239000002019 doping agent Substances 0.000 claims description 4
- 238000002513 implantation Methods 0.000 claims description 4
- 238000009736 wetting Methods 0.000 claims description 2
- 150000002431 hydrogen Chemical class 0.000 claims 1
- 238000009413 insulation Methods 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 150000002500 ions Chemical class 0.000 description 8
- 229910052681 coesite Inorganic materials 0.000 description 5
- 229910052906 cristobalite Inorganic materials 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 229910052682 stishovite Inorganic materials 0.000 description 5
- 229910052905 tridymite Inorganic materials 0.000 description 5
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 4
- 238000000926 separation method Methods 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- RPAJSBKBKSSMLJ-DFWYDOINSA-N (2s)-2-aminopentanedioic acid;hydrochloride Chemical compound Cl.OC(=O)[C@@H](N)CCC(O)=O RPAJSBKBKSSMLJ-DFWYDOINSA-N 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000013021 overheating Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000010148 water-pollination Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26533—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/3115—Doping the insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/207—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds further characterised by the doping material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/22—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIBVI compounds
- H01L29/227—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIBVI compounds further characterised by the doping material
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Recrystallisation Techniques (AREA)
- Thin Film Transistor (AREA)
- Element Separation (AREA)
Abstract
本发明提供一种绝缘层上顶层硅衬底的制造方法,包括:提供一第一半导体衬底;在该第一半导体衬底的顶面形成一第一绝缘层;对该第一半导体衬底进行离子束注入,以便在距离该第一绝缘层的顶面的预定深度处形成一重氢与氢气掺杂层;提供一第二半导体衬底;在该第二半导体衬底的顶面形成一第二绝缘层;将该第一半导体衬底面对面地接合于该第二半导体衬底;对该第一半导体衬底以及该第二半导体衬底进行退火;以及将部分的第一半导体衬底与该第二半导体衬底分离,以便在该第二半导体衬底上形成一掺杂有重氢与氢气的半导体层。
Description
技术领域
本发明有关于一种绝缘层上顶层硅衬底及其制造方法。
背景技术
近年来,已经有业界利用绝缘材料表面形成单晶半导体层的绝缘层上顶层硅(SOI)衬底来代替使用体硅晶圆于半导体集成电路的制造之中。因为使用SOI衬底的优点在于可以减少晶体管的漏极与衬底之间的寄生电容,藉此提高半导体集成电路的效能。
关于半导体器件的制造方法,例如美国公告专利第5374564号是由离子注入法对硅晶圆进行氢离子注入,并在预定深度处形成离子注入层。接下来,将植入有氢离子的硅晶圆与另一片硅晶圆接合,且于两片硅晶圆之间插置有氧化硅膜。之后,经过热处理,以离子注入层作为分裂面,且在植入有氢离子的硅晶圆以薄膜状分离。藉此可在接合的硅晶圆之上形成单晶硅层。例如美国公告专利第5872387号是由在重氢环境下对于已经生长好栅极氧化物的衬底进行退火,以便消除栅极氧化物与衬底之间的悬挂键(dangling bond)。然而此方法必须在很高的重氢环境气压进行,因而导致制造成本的提高。
因此,目前有需要一种改良的绝缘层上顶层硅衬底的制造方法,至少可改善上述的缺失。
发明内容
本发明提供一种绝缘层上顶层硅衬底及其制造方法,可以减少晶体管的漏极与衬底之间的寄生电容,以及降低制造成本。
依据本发明一实施例,提供一种绝缘层上顶层硅衬底的制造方法,包括:提供一第一半导体衬底;在该第一半导体衬底的顶面形成一第一绝缘层;对该第一半导体衬底进行离子束注入,以便在距离该第一绝缘层的顶面的预定深度处形成一重氢与氢气掺杂层;提供一第二半导体衬底;在该第二半导体衬底的顶面形成一第二绝缘层;将该第一半导体衬底面对面地接合于该第二半导体衬底;对该第一半导体衬底以及该第二半导体衬底进行退火;以及将部分的第一半导体衬底与该第二半导体衬底分离,以便在该第二半导体衬底之上形成一掺杂有重氢与氢气的半导体层。
所述的绝缘层上顶层硅衬底的制造方法,其中该第一半导体衬底包含IV族元素、SiGe、III-V族化合物、III族-氮化合物或II-V族化合物。
所述的绝缘层上顶层硅衬底的制造方法,其中该预定深度介于0.01um至5um。
所述的绝缘层上顶层硅衬底的制造方法,其中该离子束的注入能量介于1keV至200keV,而该离子束的掺杂剂量介于1016(离子个数/cm2)至2×1017(离子个数/cm2)。
所述的绝缘层上顶层硅衬底的制造方法,其中该第二半导体衬底包含IV族元素、SiGe、III-V族化合物、III族-氮化合物或II-V族化合物。
所述的绝缘层上顶层硅衬底的制造方法,其中该第一半导体衬底以及该第二半导体于介于摄氏200度~400度进行接合。
所述的绝缘层上顶层硅衬底的制造方法,其中该第一半导体衬底以及该第二半导体衬底进行接合的步骤更包括:润湿该第一绝缘层以及该第二绝缘层;将润湿后的该第一绝缘层与该第二绝缘层相互接触;以及施压于相互接触的该第一绝缘层以及该第二绝缘层,使得该第一绝缘层接合于该第二绝缘层上。
所述的绝缘层上顶层硅衬底的制造方法,其中该退火步骤更包括:先加热该第一半导体衬底以及该第二半导体衬底至摄氏600度~900度;接着冷却该第一半导体衬底以及该第二半导体衬底至摄氏400度~600度。
所述的绝缘层上顶层硅衬底的制造方法,其中冷却该第一半导体衬底以及该第二半导体衬底的时间介于30分钟~120分钟。
所述的绝缘层上顶层硅衬底的制造方法,其中该掺杂有重氢与氢气的半导体层的厚度介于50埃~50000埃。
所述的绝缘层上顶层硅衬底的制造方法,更包括该第一半导体衬底分离于该第二半导体衬底之后,再度加热该第二半导体衬底至摄氏10000度。
所述的绝缘层上顶层硅衬底的制造方法,其中加热该第二半导体衬底的时间介于30分钟~8小时。
依据本发明一实施例,提供一种绝缘层上顶层硅衬底,包括:一半导体衬底;一绝缘层,该绝缘层接合于该半导体衬底的顶面;以及一掺杂有重氢与氢气的半导体层,该掺杂有重氢与氢气的半导体层接合于该绝缘层的顶面。
所述的绝缘层上顶层硅衬底,其中该半导体衬底包含有IV族元素、SiGe、III-V族化合物、III族-氮化合物或II-V族化合物。
所述的绝缘层上顶层硅衬底,其中该掺杂有重氢与氢气的半导体层的厚度介于50埃~50000埃。
附图说明
图1为本发明提供的绝缘层上顶层硅衬底的制造方法的流程图。
图2A-2H为制造绝缘层上顶层硅衬底的剖视图。
具体实施方式
下面结合说明书附图和优选实施例对本发明作进一步的描述,但本发明的实施方式不限于此。
参阅图1,为提供一实施例的绝缘层上顶层硅衬底的制造方法,包括下列步骤:
S101:提供一第一半导体衬底
S102:在第一半导体衬底的顶面形成一第一绝缘层;
S103:以重氢与氢气为来源气体,对第一半导体衬底注入重氢与氢气离子束,以便在距离第一绝缘层的顶面的预定深度处形成一重氢与氢气掺杂层;
S104:提供一第二半导体衬底;
S105:在第二半导体衬底的顶面形成一第二绝缘层;
S106:将第一半导体衬底面对面地接合于该第二半导体衬底;
S107:对相互接合的第一半导体衬底与第二半导体衬底进行退火;
S108:将部分的第一半导体衬底与该第二半导体衬底分离;以及
S109:在第二半导体衬底上形成一掺杂有重氢与氢气的半导体层。
S110:回收利用分离后的第一半导体衬底。
为了更具体地阐述图1的绝缘层上顶层硅衬底的制造方法,请参照图2A-2G,为提供本发明一实施例所提供的制造绝缘层上顶层硅衬底的剖视图。
首先,参照图2A,制备一第一半导体衬底100,其中第一半导体衬底100的材料可包含IV族元素、SiGe、III-V族元素、III族-氮化合物或II-V族化合物。在本实施例中,第一半导体衬底100使用单晶硅。在其他实施例中,当第一半导体衬底100的材料为SiGe时,Ge的重量百分比介于5%~90%。
接下来,参照图2B,于该第一半导体衬底100的顶面102形成一第一绝缘层104,其中第一绝缘层104的材料可包含SiO2、SiN或AlN。在本实施例中,第一绝缘层104使用SiO2,且其厚度大约介于0.1nm~500nm。
接着,参照图2C,以重氢与氢气作为来源气体,透过电场作用而产生来源气体的等离子体,并从等离子体中取出包含在等离子体中的离子来予以生成来源气体的离子束,对第一半导体衬底100照射重氢与氢气离子束108,以便于距离第一绝缘层104的顶面110的预定深度H处形成一重氢与氢气掺杂层112,该预定深度H可藉由重氢与氢气离子束108的加速能量以及入射角来控制,至于加速能量可藉由注入能量以及掺杂剂量来控制。在本实施例中,预定深度H介于0.1um~5um,注入能量介于1keV~200keV,而氢离子束的掺杂剂量介于1016(离子个数/cm2)~2x1017(离子个数/cm2)。
下面,参照图2D,制备一第二半导体衬底200,其中第二半导体衬底200的材料可包含IV族元素、SiGe、III-V族化合物、III族-氮化合物或II-V族化合物。在本实施例中,第二半导体衬底200的材料为单晶硅。
接下来,参照图2E,于该第二半导体衬底200的顶面202形成一第二绝缘层204,其中该第二绝缘层204可包含SiO2、SiN或AlN。在本实施例中,第二绝缘层204使用SiO2,且其厚度大约介于0.05nm至10nm。
接着,参照图2F,将第一半导体衬底100面对面地接合(bonding)于第二半导体衬底200。在本实施例中,采用亲水性接合(hydrophilic bonding)的方式,接合时的温度介于摄氏200度~400度,其中接合的详细步骤更包括:首先湿润第一绝缘层104与第二绝缘层204;接着将湿润后的第一绝缘层104与第二绝缘层204相互接触;以及最后施压于第一绝缘层104与第二绝缘层204,使得第一绝缘层104与第二绝缘层204紧密地相互接合。
下面,参照图2G,对相互接合的第一半导体衬底100以及该第二半导体衬底200进行退火(annealing),而退火的详细步骤包括:首先加热该第一半导体衬底100与第二半导体衬底200至摄氏600度~900度;接着,冷却第一半导体衬底100与第二半导体衬底200至摄氏400度~600度,而冷却时间大约30分钟~120分钟。经过退火后,原本相连的重氢与氢气掺杂层112会分裂为复数个相互间隔的重氢与氢气掺杂气泡区块300(Bubble formation)。
接着,参照图2H,将部分的第一半导体衬底100与该第二半导体衬底200分离,以便形成一包含有该些重氢与氢气掺杂气泡区块300的半导体层400于相互接合的第一绝缘层104与第二绝缘层204上。
值得一提的,分离后的第一半导体衬底100,更可进一步进行化学机械研磨(CMP)与清洗(clean),使得分离后的第一半导体衬底100得以回收利用,达到节省成本的效果。至于接合有半导体层400的第二半导体衬底200可进行再度加热至摄氏10000度,而再度加热时间介于30分钟~8小时。
由于悬挂键(dangling bond)含有极高的活性,容易形成陷阱中心(trap center),造成电子空穴对的再度结合,因而降低半导体器件对于热载流子效应的恢复力。藉由本发明所提供的绝缘层上顶层硅衬底来制造半导体器件,除了可以减少晶体管的漏极与衬底之间的寄生电容之外。将来于绝缘层上顶层硅衬底生长栅极氧化物时,掺杂于衬底内的重氢原子会向外扩散至栅极氧化物与该衬底之间的接口与半导体原子共价键结(covalently bound),以便消除悬挂键而有效率地提升半导体器件对于热载流子效应(hot carrier effect)载流子的恢复力(resilience)。再者,由于不需要很高的重氢气压,制造成本大大降低。
以上所揭露的仅为本发明的优选实施例而已,当然不能以此来限定本发明之权利范围,因此依本发明申请专利范围所作的等同变化,仍属本发明所涵盖的范围。
Claims (15)
1.一种绝缘层上顶层硅衬底的制造方法,包括:
提供一第一半导体衬底;
在该第一半导体衬底的顶面形成一第一绝缘层;
对该第一半导体衬底进行离子束注入,以便在距离该第一绝缘层的顶面的预定深度处形成一重氢与氢气掺杂层;
提供一第二半导体衬底;
在该第二半导体衬底的顶面形成一第二绝缘层;
将该第一半导体衬底面对面地接合于该第二半导体衬底;
对该第一半导体衬底以及该第二半导体衬底进行退火;以及
将部分的第一半导体衬底与该第二半导体衬底分离,以便在该第二半导体衬底上形成一掺杂有重氢与氢气的半导体层。
2.如权利要求1所述的绝缘层上顶层硅衬底的制造方法,其特征在于,该第一半导体衬底包含IV族元素、SiGe、III-V族化合物、III族-氮化合物或II-V族化合物。
3.如权利要求1所述的绝缘层上顶层硅衬底的制造方法,其特征在于,该预定深度介于0.1um至5um。
4.如权利要求1所述的绝缘层上顶层硅衬底的制造方法,其特征在于,该离子束的注入能量介于1keV至200keV,而该离子束之掺杂剂量介于1016(离子个数/cm2)至2x1017(离子个数/cm2)。
5.如权利要求1所述的绝缘层上顶层硅衬底的制造方法,其特征在于,该第二半导体衬底包含IV族元素、SiGe、III-V族化合物、III族-氮化合物或II-V族化合物。
6.如权利要求1所述的绝缘层上顶层硅衬底的制造方法,其特征在于,该第一半导体衬底以及该第二半导体衬底在介于摄氏200度~400度面对面地进行接合。
7.如权利要求1所述的绝缘层上顶层硅衬底的制造方法,其特征在于,该第一半导体衬底以及该第二半导体衬底面对面地接合的步骤更包括:润湿该第一绝缘层以及该第二绝缘层;将润湿后的该第一绝缘层与该第二绝缘层相互接触;以及施压于相互接触的该第一绝缘层以及该第二绝缘层,使得该第一绝缘层接合于该第二绝缘层上。
8.如权利要求1所述的绝缘层上顶层硅衬底的制造方法,其特征在于,该退火步骤更包括:先加热该第一半导体衬底以及该第二半导体衬底至摄氏600度~900度;接着冷却该第一半导体衬底以及该第二半导体衬底至摄氏400度~600度。
9.如权利要求8所述的绝缘层上顶层硅衬底的制造方法,其特征在于,冷却该第一半导体衬底以及该第二半导体衬底的时间介于30分钟~120分钟。
10.如权利要求1所述的绝缘层上顶层硅衬底的制造方法,其特征在于,该掺杂有重氢的半导体层的厚度介于50埃~50000埃。
11.如权利要求1所述的绝缘层上顶层硅衬底的制造方法,其特征在于,更包括该第一半导体衬底分离于该第二半导体衬底之后,再度加热该第二半导体衬底至摄氏10000度。
12.如权利要求11所述的绝缘层上顶层硅衬底的制造方法,其特征在于,再度加热该第二半导体衬底之时间介于30分钟~8小时。
13.一种绝缘层上顶层硅衬底,包括:
一半导体衬底;
一绝缘层,该绝缘层接合于该半导体衬底的顶面;以及
一掺杂有重氢与氢气的半导体层,该掺杂有重氢与氢气的半导体层接合于该绝缘层的顶面。
14.如权利要求13所述的绝缘层上顶层硅衬底,其特征在于,该半导体衬底包含有IV族元素、SiGe、III-V族化合物、III族-氮化合物或II-V族化合物。
15.如权利要求13所述的绝缘层上顶层硅衬底,其特征在于,该掺杂有重氢与氢气的半导体层的厚度介于50埃~50000埃。
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201610120565.2A CN107154378B (zh) | 2016-03-03 | 2016-03-03 | 绝缘层上顶层硅衬底及其制造方法 |
TW105118832A TWI592987B (zh) | 2016-03-03 | 2016-06-15 | 絕緣層上覆矽基板及其製造方法 |
US15/258,899 US20170256440A1 (en) | 2016-03-03 | 2016-09-07 | Soi substrate and manufacturing method thereof |
JP2016186873A JP2017157814A (ja) | 2016-03-03 | 2016-09-26 | Soi基板及びその製造方法 |
DE102017100054.2A DE102017100054A1 (de) | 2016-03-03 | 2017-01-03 | Soi substrat und herstellungsverfahren hierfür |
US15/415,609 US10014210B2 (en) | 2016-03-03 | 2017-01-25 | SOI substrate and manufacturing method thereof |
KR1020170023836A KR20170103651A (ko) | 2016-03-03 | 2017-02-23 | Soi 기판 및 그 제조방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201610120565.2A CN107154378B (zh) | 2016-03-03 | 2016-03-03 | 绝缘层上顶层硅衬底及其制造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN107154378A true CN107154378A (zh) | 2017-09-12 |
CN107154378B CN107154378B (zh) | 2020-11-20 |
Family
ID=59650997
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201610120565.2A Active CN107154378B (zh) | 2016-03-03 | 2016-03-03 | 绝缘层上顶层硅衬底及其制造方法 |
Country Status (6)
Country | Link |
---|---|
US (2) | US20170256440A1 (zh) |
JP (1) | JP2017157814A (zh) |
KR (1) | KR20170103651A (zh) |
CN (1) | CN107154378B (zh) |
DE (1) | DE102017100054A1 (zh) |
TW (1) | TWI592987B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102017100054A1 (de) | 2016-03-03 | 2017-09-07 | Zing Semiconductor Corporation | Soi substrat und herstellungsverfahren hierfür |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112864006B (zh) * | 2021-01-11 | 2022-11-08 | 中国科学院上海微系统与信息技术研究所 | 一种半导体衬底的制备方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5374564A (en) * | 1991-09-18 | 1994-12-20 | Commissariat A L'energie Atomique | Process for the production of thin semiconductor material films |
US5882987A (en) * | 1997-08-26 | 1999-03-16 | International Business Machines Corporation | Smart-cut process for the production of thin semiconductor material films |
CN101308782A (zh) * | 2007-05-18 | 2008-11-19 | 株式会社半导体能源研究所 | Soi衬底的制造方法、以及半导体装置的制造方法 |
CN101461055A (zh) * | 2006-05-31 | 2009-06-17 | 康宁股份有限公司 | 使用高纯度离子喷淋制造soi结构 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5872387A (en) | 1996-01-16 | 1999-02-16 | The Board Of Trustees Of The University Of Illinois | Deuterium-treated semiconductor devices |
JPH11330438A (ja) * | 1998-05-08 | 1999-11-30 | Shin Etsu Handotai Co Ltd | Soiウエーハの製造方法ならびにこの方法で製造されるsoiウエーハ |
JP2007141946A (ja) * | 2005-11-15 | 2007-06-07 | Sumco Corp | Soi基板の製造方法及びこの方法により製造されたsoi基板 |
US7378335B2 (en) * | 2005-11-29 | 2008-05-27 | Varian Semiconductor Equipment Associates, Inc. | Plasma implantation of deuterium for passivation of semiconductor-device interfaces |
US7781306B2 (en) | 2007-06-20 | 2010-08-24 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor substrate and method for manufacturing the same |
US8431451B2 (en) * | 2007-06-29 | 2013-04-30 | Semicondutor Energy Laboratory Co., Ltd. | Display device and method for manufacturing the same |
JP4636110B2 (ja) * | 2008-04-10 | 2011-02-23 | 信越半導体株式会社 | Soi基板の製造方法 |
US8329557B2 (en) * | 2009-05-13 | 2012-12-11 | Silicon Genesis Corporation | Techniques for forming thin films by implantation with reduced channeling |
KR102189611B1 (ko) * | 2014-01-23 | 2020-12-14 | 글로벌웨이퍼스 씨오., 엘티디. | 고 비저항 soi 웨이퍼 및 그 제조 방법 |
CN106601663B (zh) * | 2015-10-20 | 2019-05-31 | 上海新昇半导体科技有限公司 | Soi衬底及其制备方法 |
CN107154378B (zh) | 2016-03-03 | 2020-11-20 | 上海新昇半导体科技有限公司 | 绝缘层上顶层硅衬底及其制造方法 |
-
2016
- 2016-03-03 CN CN201610120565.2A patent/CN107154378B/zh active Active
- 2016-06-15 TW TW105118832A patent/TWI592987B/zh active
- 2016-09-07 US US15/258,899 patent/US20170256440A1/en not_active Abandoned
- 2016-09-26 JP JP2016186873A patent/JP2017157814A/ja active Pending
-
2017
- 2017-01-03 DE DE102017100054.2A patent/DE102017100054A1/de not_active Ceased
- 2017-01-25 US US15/415,609 patent/US10014210B2/en active Active
- 2017-02-23 KR KR1020170023836A patent/KR20170103651A/ko not_active Application Discontinuation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5374564A (en) * | 1991-09-18 | 1994-12-20 | Commissariat A L'energie Atomique | Process for the production of thin semiconductor material films |
US5882987A (en) * | 1997-08-26 | 1999-03-16 | International Business Machines Corporation | Smart-cut process for the production of thin semiconductor material films |
CN101461055A (zh) * | 2006-05-31 | 2009-06-17 | 康宁股份有限公司 | 使用高纯度离子喷淋制造soi结构 |
CN101308782A (zh) * | 2007-05-18 | 2008-11-19 | 株式会社半导体能源研究所 | Soi衬底的制造方法、以及半导体装置的制造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102017100054A1 (de) | 2016-03-03 | 2017-09-07 | Zing Semiconductor Corporation | Soi substrat und herstellungsverfahren hierfür |
Also Published As
Publication number | Publication date |
---|---|
DE102017100054A1 (de) | 2017-09-07 |
KR20170103651A (ko) | 2017-09-13 |
TW201732867A (zh) | 2017-09-16 |
US20170256616A1 (en) | 2017-09-07 |
US10014210B2 (en) | 2018-07-03 |
US20170256440A1 (en) | 2017-09-07 |
TWI592987B (zh) | 2017-07-21 |
JP2017157814A (ja) | 2017-09-07 |
CN107154378B (zh) | 2020-11-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR101913322B1 (ko) | 반도체 소자들을 위한 트랩 리치 층 | |
TWI379361B (en) | Formation of shallow junctions by diffusion from a dielectric doped by cluster or molecular ion beams | |
TW200816328A (en) | Use of carbon co-implantation with millisecond anneal to produce ultra-shallow junctions | |
EP1065706A2 (en) | Method for making a diffused back-side layer on a bonded-wafer with a thick bond oxide | |
CN102986011A (zh) | 半导体器件的制造方法 | |
WO2007125771A1 (ja) | Soiウエーハの製造方法 | |
CN109196622B (zh) | 深结电子器件及其制造方法 | |
CN106601663B (zh) | Soi衬底及其制备方法 | |
CN107154378A (zh) | 绝缘层上顶层硅衬底及其制造方法 | |
CN103178103B (zh) | 半导体器件及其制造方法 | |
JP5010589B2 (ja) | 半導体デバイス製造方法及びその方法により製造した半導体デバイスを備えた半導体集積回路チップ | |
CN107154347A (zh) | 绝缘层上顶层硅衬底及其制造方法 | |
CN107154379A (zh) | 绝缘层上顶层硅衬底及其制造方法 | |
US20030160233A1 (en) | Method of forming a semiconductor device having an energy absorbing layer and structure thereof | |
GB2307790A (en) | Method of removing defects from semiconductor devices. | |
US11038028B2 (en) | Semiconductor device and manufacturing method | |
TW573328B (en) | Bipolar junction transistor and manufacturing method thereof | |
KR100774818B1 (ko) | Soi기판 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |