US20170256440A1 - Soi substrate and manufacturing method thereof - Google Patents
Soi substrate and manufacturing method thereof Download PDFInfo
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- US20170256440A1 US20170256440A1 US15/258,899 US201615258899A US2017256440A1 US 20170256440 A1 US20170256440 A1 US 20170256440A1 US 201615258899 A US201615258899 A US 201615258899A US 2017256440 A1 US2017256440 A1 US 2017256440A1
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- wafer
- insulating layer
- deuterium
- hydrogen
- semiconductor substrate
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- 239000000758 substrate Substances 0.000 title claims abstract description 69
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 57
- 229910052805 deuterium Inorganic materials 0.000 claims abstract description 43
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 39
- 239000001257 hydrogen Substances 0.000 claims abstract description 39
- 238000000034 method Methods 0.000 claims abstract description 38
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 35
- YZCKVEUIGOORGS-OUBTZVSYSA-N Deuterium Chemical compound [2H] YZCKVEUIGOORGS-OUBTZVSYSA-N 0.000 claims abstract description 30
- 238000000137 annealing Methods 0.000 claims abstract description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 20
- 239000010703 silicon Substances 0.000 claims description 20
- -1 deuterium ions Chemical class 0.000 claims description 17
- 239000012212 insulator Substances 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 12
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 10
- 150000001875 compounds Chemical class 0.000 claims description 10
- 150000002500 ions Chemical class 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 6
- 229910017464 nitrogen compound Inorganic materials 0.000 claims description 5
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 4
- 238000001816 cooling Methods 0.000 claims description 4
- 230000001678 irradiating effect Effects 0.000 claims description 3
- 238000010884 ion-beam technique Methods 0.000 claims description 2
- 238000003825 pressing Methods 0.000 claims description 2
- 238000009736 wetting Methods 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 description 51
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 2
- 125000004431 deuterium atom Chemical group 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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Definitions
- the present invention relates to a semiconductor substrate and a method for manufacturing the semiconductor substrate, and particularly relates to a silicon on insulator substrate and a method for manufacturing the silicon on insulator substrate.
- SOI silicon on insulator
- a method for manufacturing a semiconductor device such as U.S. Pat. No. 5,374,564, which provides a method for doping hydrogen ions into a silicon wafer, and forming an ion doped layer at a pre-determined depth of the silicon wafer. Then the silicon wafer doped by hydrogen ions is coupled with another silicon wafer, and a silicon oxide film is formed between the two silicon wafers. Then the two silicon wafers are separated at the ion doped layer by a heat treatment, whereby a monocrystalline silicon film can be formed on the ion doped layer.
- U.S. Pat. No. 5,872,387 provides a method for annealing a substrate growth, a gate oxide layer at a deuterium atmosphere, whereby dangling bonds between the gate oxide and the substrate can be removed.
- this method should be proceeding at a very high deuterium pressure, so that a cost for manufacturing a semiconductor device is increased.
- An object of the present invention application is to provide a silicon on insulator substrate and a method thereof, wherein the SOI substrate has an advantage of reducing the parasitic capacitance between a drain and a substrate, and the cost for manufacturing the SOI substrate can be reduced.
- the present invention application provides a method for manufacturing a SOI substrate, and the method comprising: providing a first semiconductor substrate; growing a first insulating layer on a top surface of the first semiconductor substrate for forming a first wafer; irradiating the first semiconductor substrate via a ion beam for forming a deuterium and hydrogen co-doping layer to a pre-determined depth from a top surface of the first insulating layer; providing a second substrate; growing a second insulating layer on a top surface of the second semiconductor substrate for forming a second wafer; bonding the first wafer with the second wafer in a face to face manner; annealing the first wafer and second wafer; separating a part of the first wafer from the second wafer; forming a deuterium and hydrogen co-doping semiconductor layer on the second wafer.
- the present invention application further provides a SOI substrate comprising: a semiconductor substrate; an insulating layer grown on a top surface of the semiconductor substrate; and a deuterium and hydrogen co-doping semiconductor layer grown on the insulating layer.
- FIG. 1 is a flowchart of a method for manufacturing a silicon on insulator substrate according to one embodiment of the present invention.
- FIGS. 2A-2H are cross-sectional views of a process for manufacturing a silicon on insulator substrate.
- FIG. 1 provides a method for manufacturing a silicon on insulator substrate according to one embodiment of this invention, and the manufacture method comprises:
- Step 102 (S 102 ): growing a first insulating layer on a bottom surface of the first semiconductor substrate for forming a first wafer;
- Step 103 Deuterium and hydrogen being used for source gases, and irradiating the first semiconductor substrate via a deuterium and hydrogen ions co-beam for forming a deuterium and hydrogen co-doping layer to a pre-determined depth from a top surface of the first insulating layer;
- Step 104 (S 104 ): providing a second semiconductor substrate
- Step 105 (S 105 ): growing a second insulating layer on a top surface of the second semiconductor substrate for forming a second wafer;
- Step 106 bonding the first wafer with the second wafer in a face to face manner
- Step 107 annealing the first wafer and the second wafer
- Step 108 (S 108 ): separating a part of the first wafer from the second wafer.
- Step 109 (S 109 ): forming a deuterium and hydrogen co-doping semiconductor layer on the second wafer;
- FIGS. 2A-2G provide cross-sectional views of a process for manufacturing a silicon on insulator substrate.
- a first semiconductor substrate 100 is provided, wherein the material of the first semiconductor substrate 100 may be Group IV, SiGe, III-V group compound, Group III -Nitrogen compound, or II-VI group compound.
- the material of the first semiconductor substrate 100 is single crystal silicon.
- the material of the first semiconductor substrate 100 is SiGe, and the weight percent of germanium is between 5% ⁇ 90%.
- a first insulating layer 104 is grown on a top surface 102 of the first semiconductor substrate 100 for forming a first wafer 106 , wherein the material of the first insulating layer 104 may include silicon dioxide, silicon nitride, or aluminum nitride. In one embodiment, the material of the first insulating layer is silicon dioxide and the thickness of the first insulating layer 104 may be between 0.1 nm and 500 nm.
- hydrogen and deuterium can be processed by an electric field for producing a hydrogen plasma and a deuterium plasma, and a hydrogen ion and deuterium ion co-beam may be generated through taking hydrogen ions of a hydrogen plasma and deuterium ions of a deuterium plasma.
- the first wafer 106 is illuminated by a hydrogen and deuterium ions co-beam 108 for implanting a deuterium and hydrogen co-doping layer 112 at a pre-determined depth H from a top surface 110 of the first insulating layer 110 .
- the pre-determined depth H may be controlled by an accelerated energy of the hydrogen and deuterium ions co-beam 108 and an incident angle of the hydrogen and deuterium ions co-beam 108 , wherein the accelerated energy of the hydrogen and deuterium ions co-beam 108 may be controlled by an accelerated voltage and a doped concentration.
- the pre-determined depth H is between 0.1 ⁇ m and 5 ⁇ m
- an accelerated voltage of the hydrogen and deuterium ions co-beam 108 is between 1 keV and 200 keV
- a doping dosage of the hydrogen and deuterium ions co-beam 108 is between 10 16 ions/cm 2 and 2 ⁇ 10 17 ions/cm 2 .
- a second semiconductor substrate 200 is provided, wherein the material of the second semiconductor substrate 200 may include IV group element, silicon-germanium (SiGe), III-V group compound, III group-nitrogen compound, or II-VI group compound.
- the material of the second semiconductor substrate 200 is single crystal silicon.
- a second insulating layer 204 is grown on a top surface 202 of the second semiconductor substrate 200 for forming a second wafer 206 , wherein the material of the second insulating layer 204 may include silicon dioxide, silicon nitride, or aluminum nitride. In one embodiment, the material of the second insulating layer 204 is silicon dioxide and the thickness of the second insulating layer 204 may be between 0.05 nm and 10 nm.
- the first wafer 106 is bonded with the second wafer 206 face to face.
- the first wafer 106 is bonded with second wafer 206 through hydrophilic bonding process, wherein the first wafer 106 is bonded with second wafer 206 at a temperature between 200 degrees centigrade and 400 degrees centigrade.
- the detail steps of hydrophilic bonding process further comprises the steps of: wetting the first insulating layer 104 and the second insulating layer 204 ; contacting the wetted first insulating layer 104 with the wetted second insulating layer 204 ; and pressing the first insulating layer 104 and the second insulating layer 204 for closely bonding the first insulating layer 104 with the second insulating layer 204 .
- the first wafer 106 and the second wafer 206 are annealed, and the annealing process comprises the steps of: heating the first wafer 106 and the second wafer 206 to a temperature between 600 degrees centigrade and 900 degrees centigrade; cooling the first wafer 106 and the second wafer 206 to a temperature between 400 degrees centigrade and 600 degrees centigrade, wherein time for cooling the first wafer 106 and the second wafer 206 is between 30 minutes and 120 minutes.
- the deuterium and hydrogen co-doping layer 112 are transferred to a plurality of deuterium and hydrogen co-doping bubbles 300 .
- the next step is referred to FIG. 2H , a part of the first wafer 106 is separated from the second wafer 206 for forming a deuterium and hydrogen co-doping semiconductor layer 400 , wherein the deuterium and hydrogen co-doping semiconductor layer 400 is bonded with the first insulating layer 104 and a thickness of the deuterium and hydrogen co-doping semiconductor layer 400 is between 50 ⁇ and 50000 ⁇ , and the deuterium and hydrogen co-doping bubbles 300 are in the deuterium and hydrogen co-doping semiconductor layer 400 .
- the separated part of the first wafer 106 may further be proceeded with chemical-mechanical polishing (CMP) and cleaned, so that the separated part of the first wafer 106 may be reused for economizing on cost.
- CMP chemical-mechanical polishing
- the second wafer 106 bonded with the deuterium and hydrogen co-doping semiconductor layer 400 may further be heated to 10000 degrees centigrade, and time for heating the second wafer 106 is between 30 minutes and 8 hours.
- This invention provides a SOI substrate for manufacturing a semiconductor device.
- the SOI substrate can reduce a parasitic capacitance between a drain and a source of the semiconductor device, deuterium atoms (or deuterium ions) doped in the SOI substrate may be diffused into an interface between a gate oxide and the SOI substrate after growing the gate oxide on the SOI substrate, and deuterium atoms (or deuterium ions) are covalently bonded to semiconductor atoms for eliminating the dangling bond and increasing the resilience of the semiconductor device to hot carrier effects.
- the method for manufacturing the SOI substrate doesn't need a very high deuterium pressure, and the cost for manufacturing the SOI substrate can be reduced substantially.
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Abstract
The present invention application provides a method for manufacturing a SOI substrate, and the method comprising: providing a first semiconductor substrate; growing a first insulating layer on a top surface of the first semiconductor substrate for forming a first wafer; implanting a deuterium and hydrogen co-doping layer at a certain pre-determined depth of the first wafer; providing a second substrate; growing a second insulating layer on a top surface of the second semiconductor substrate for forming a second wafer; bonding the first wafer with the second wafer; annealing the first wafer and second wafer; separating a part of the first wafer from the second wafer; and forming a deuterium and hydrogen co-doping semiconductor layer on the second wafer.
Description
- This application claims priority from P.R.C. Patent Application No. 201610120565.2, filed on Mar. 3, 2016, the contents of which are hereby incorporated by reference in their entirety for all purposes.
- The present invention relates to a semiconductor substrate and a method for manufacturing the semiconductor substrate, and particularly relates to a silicon on insulator substrate and a method for manufacturing the silicon on insulator substrate.
- In recent years, many industries have used silicon on insulator (SOI) substrate to manufacture a semiconductor integrated circuit instead of using a piece of a silicon wafer. Because using an SOI substrate has an advantage of reducing the parasitic capacitance between a drain and a substrate, whereby a performance of a semiconductor integrated circuit can be promoted.
- With regard to a method for manufacturing a semiconductor device, such as U.S. Pat. No. 5,374,564, which provides a method for doping hydrogen ions into a silicon wafer, and forming an ion doped layer at a pre-determined depth of the silicon wafer. Then the silicon wafer doped by hydrogen ions is coupled with another silicon wafer, and a silicon oxide film is formed between the two silicon wafers. Then the two silicon wafers are separated at the ion doped layer by a heat treatment, whereby a monocrystalline silicon film can be formed on the ion doped layer.
- For example, U.S. Pat. No. 5,872,387 provides a method for annealing a substrate growth, a gate oxide layer at a deuterium atmosphere, whereby dangling bonds between the gate oxide and the substrate can be removed. However, this method should be proceeding at a very high deuterium pressure, so that a cost for manufacturing a semiconductor device is increased.
- In view of prior arts described above, an improved method is needed for manufacturing a SOI substrate, which at least solves drawbacks described above.
- An object of the present invention application is to provide a silicon on insulator substrate and a method thereof, wherein the SOI substrate has an advantage of reducing the parasitic capacitance between a drain and a substrate, and the cost for manufacturing the SOI substrate can be reduced.
- In order to solving the above problems, the present invention application provides a method for manufacturing a SOI substrate, and the method comprising: providing a first semiconductor substrate; growing a first insulating layer on a top surface of the first semiconductor substrate for forming a first wafer; irradiating the first semiconductor substrate via a ion beam for forming a deuterium and hydrogen co-doping layer to a pre-determined depth from a top surface of the first insulating layer; providing a second substrate; growing a second insulating layer on a top surface of the second semiconductor substrate for forming a second wafer; bonding the first wafer with the second wafer in a face to face manner; annealing the first wafer and second wafer; separating a part of the first wafer from the second wafer; forming a deuterium and hydrogen co-doping semiconductor layer on the second wafer.
- The present invention application further provides a SOI substrate comprising: a semiconductor substrate; an insulating layer grown on a top surface of the semiconductor substrate; and a deuterium and hydrogen co-doping semiconductor layer grown on the insulating layer.
- Exemplary embodiments will be more readily understood from the following detailed description when read in conjunction with the appended drawing, in which:
-
FIG. 1 is a flowchart of a method for manufacturing a silicon on insulator substrate according to one embodiment of the present invention; and -
FIGS. 2A-2H are cross-sectional views of a process for manufacturing a silicon on insulator substrate. - For a more complete understanding of the present disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which like reference numbers indicate like features. Persons having ordinary skill in the art will understand other varieties for implementing example embodiments, including those described herein.
-
FIG. 1 provides a method for manufacturing a silicon on insulator substrate according to one embodiment of this invention, and the manufacture method comprises: - Step 101 (S101): providing a first semiconductor substrate;
- Step 102 (S102): growing a first insulating layer on a bottom surface of the first semiconductor substrate for forming a first wafer;
- Step 103 (S103): Deuterium and hydrogen being used for source gases, and irradiating the first semiconductor substrate via a deuterium and hydrogen ions co-beam for forming a deuterium and hydrogen co-doping layer to a pre-determined depth from a top surface of the first insulating layer;
- Step 104 (S104): providing a second semiconductor substrate;
- Step 105 (S105): growing a second insulating layer on a top surface of the second semiconductor substrate for forming a second wafer;
- Step 106 (S106): bonding the first wafer with the second wafer in a face to face manner;
- Step 107 (S107): annealing the first wafer and the second wafer;
- Step 108 (S108): separating a part of the first wafer from the second wafer; and
- Step 109 (S109): forming a deuterium and hydrogen co-doping semiconductor layer on the second wafer;
- Step 110 (S110): reusing the separated part of the first wafer.
- In order to describe the method for manufacturing the silicon on insulator more specifically,
FIGS. 2A-2G provide cross-sectional views of a process for manufacturing a silicon on insulator substrate. - The first step is referred to
FIG. 2A , afirst semiconductor substrate 100 is provided, wherein the material of thefirst semiconductor substrate 100 may be Group IV, SiGe, III-V group compound, Group III -Nitrogen compound, or II-VI group compound. In one embodiment, the material of thefirst semiconductor substrate 100 is single crystal silicon. In another embodiment, the material of thefirst semiconductor substrate 100 is SiGe, and the weight percent of germanium is between 5%˜90%. - The next process is referred to
FIG. 2B , afirst insulating layer 104 is grown on atop surface 102 of thefirst semiconductor substrate 100 for forming afirst wafer 106, wherein the material of thefirst insulating layer 104 may include silicon dioxide, silicon nitride, or aluminum nitride. In one embodiment, the material of the first insulating layer is silicon dioxide and the thickness of the firstinsulating layer 104 may be between 0.1 nm and 500 nm. - The next process is referred to
FIG. 2C , hydrogen and deuterium can be processed by an electric field for producing a hydrogen plasma and a deuterium plasma, and a hydrogen ion and deuterium ion co-beam may be generated through taking hydrogen ions of a hydrogen plasma and deuterium ions of a deuterium plasma. Thefirst wafer 106 is illuminated by a hydrogen and deuterium ions co-beam 108 for implanting a deuterium andhydrogen co-doping layer 112 at a pre-determined depth H from atop surface 110 of the firstinsulating layer 110. The pre-determined depth H may be controlled by an accelerated energy of the hydrogen and deuterium ions co-beam 108 and an incident angle of the hydrogen and deuterium ions co-beam 108, wherein the accelerated energy of the hydrogen and deuterium ions co-beam 108 may be controlled by an accelerated voltage and a doped concentration. In one embodiment, the pre-determined depth H is between 0.1 μm and 5 μm, an accelerated voltage of the hydrogen anddeuterium ions co-beam 108 is between 1 keV and 200 keV, and a doping dosage of the hydrogen anddeuterium ions co-beam 108 is between 1016 ions/cm2 and 2×1017 ions/cm2. - The next step is referred to
FIG. 2D , asecond semiconductor substrate 200 is provided, wherein the material of thesecond semiconductor substrate 200 may include IV group element, silicon-germanium (SiGe), III-V group compound, III group-nitrogen compound, or II-VI group compound. In one embodiment, the material of thesecond semiconductor substrate 200 is single crystal silicon. - The next process is referred to
FIG. 2E , a secondinsulating layer 204 is grown on atop surface 202 of thesecond semiconductor substrate 200 for forming asecond wafer 206, wherein the material of the secondinsulating layer 204 may include silicon dioxide, silicon nitride, or aluminum nitride. In one embodiment, the material of the secondinsulating layer 204 is silicon dioxide and the thickness of the secondinsulating layer 204 may be between 0.05 nm and 10 nm. - The next step is referred to
FIG. 2F , thefirst wafer 106 is bonded with thesecond wafer 206 face to face. In one embodiment, thefirst wafer 106 is bonded withsecond wafer 206 through hydrophilic bonding process, wherein thefirst wafer 106 is bonded withsecond wafer 206 at a temperature between 200 degrees centigrade and 400 degrees centigrade. The detail steps of hydrophilic bonding process further comprises the steps of: wetting the firstinsulating layer 104 and the secondinsulating layer 204; contacting the wettedfirst insulating layer 104 with the wetted secondinsulating layer 204; and pressing thefirst insulating layer 104 and the secondinsulating layer 204 for closely bonding thefirst insulating layer 104 with thesecond insulating layer 204. - The next step is referred to
FIG. 2G , thefirst wafer 106 and thesecond wafer 206 are annealed, and the annealing process comprises the steps of: heating thefirst wafer 106 and thesecond wafer 206 to a temperature between 600 degrees centigrade and 900 degrees centigrade; cooling thefirst wafer 106 and thesecond wafer 206 to a temperature between 400 degrees centigrade and 600 degrees centigrade, wherein time for cooling thefirst wafer 106 and thesecond wafer 206 is between 30 minutes and 120 minutes. After annealing thefirst wafer 106 and thesecond wafer 206, the deuterium andhydrogen co-doping layer 112 are transferred to a plurality of deuterium and hydrogen co-doping bubbles 300. - The next step is referred to
FIG. 2H , a part of thefirst wafer 106 is separated from thesecond wafer 206 for forming a deuterium and hydrogenco-doping semiconductor layer 400, wherein the deuterium and hydrogenco-doping semiconductor layer 400 is bonded with the first insulatinglayer 104 and a thickness of the deuterium and hydrogenco-doping semiconductor layer 400 is between 50 Å and 50000 Å, and the deuterium and hydrogen co-doping bubbles 300 are in the deuterium and hydrogenco-doping semiconductor layer 400. - It is worth noting that the separated part of the
first wafer 106 may further be proceeded with chemical-mechanical polishing (CMP) and cleaned, so that the separated part of thefirst wafer 106 may be reused for economizing on cost. Thesecond wafer 106 bonded with the deuterium and hydrogenco-doping semiconductor layer 400 may further be heated to 10000 degrees centigrade, and time for heating thesecond wafer 106 is between 30 minutes and 8 hours. - Because a dangling bond has a higher activity, a trap center may be produced to cause that an electron is bonded with an electron hole once again. Consequently a resilience of a semiconductor device to hot carrier effects is decreased. This invention provides a SOI substrate for manufacturing a semiconductor device. The SOI substrate can reduce a parasitic capacitance between a drain and a source of the semiconductor device, deuterium atoms (or deuterium ions) doped in the SOI substrate may be diffused into an interface between a gate oxide and the SOI substrate after growing the gate oxide on the SOI substrate, and deuterium atoms (or deuterium ions) are covalently bonded to semiconductor atoms for eliminating the dangling bond and increasing the resilience of the semiconductor device to hot carrier effects. Moreover, the method for manufacturing the SOI substrate doesn't need a very high deuterium pressure, and the cost for manufacturing the SOI substrate can be reduced substantially.
- While various embodiments in accordance with the disclosed principles have been described above, it should be understood that they are presented by way of example only, and are not limiting. Thus, the breadth and scope of exemplary embodiment(s) should not be limited by any of the above-described embodiments, but should be defined only in accordance with the claims and their equivalents issuing from this disclosure. Furthermore, the above advantages and features are provided in described embodiments, but shall not limit the application of such issued claims to processes and structures accomplishing any or all of the above advantages.
Claims (15)
1. A manufacturing method of a silicon on insulator substrate, comprising the steps of:
providing a first semiconductor substrate;
growing a first insulating layer on a top surface of the first semiconductor substrate for forming a first wafer;
irradiating the first semiconductor substrate via a ion beam for forming a deuterium and hydrogen co-doping layer to a pre-determined depth from a top surface of the first insulating layer;
providing a second substrate;
growing a second insulating layer on a top surface of the second semiconductor substrate for forming a second wafer;
bonding the first wafer with second wafer through a hydrophilic bonding process, wherein the first wafer is bonded with second wafer at a temperature between 200 degrees centigrade and degrees centigrade, the detail steps of hydrophilic bonding process further comprises the steps of:
wetting the first insulating layer and the second insulating layer;
contacting the wetted first insulating layer with the wetted second insulating layer; and
pressing the first insulating layer and the second insulating layer for closely bonding the first insulating layer with the second insulating layer;
annealing the first wafer and second wafer;
separating a part of the first wafer from the second wafer; and
forming a deuterium and hydrogen co-doping semiconductor layer on the second wafer.
2. The method according to claim 1 , wherein a material of the first semiconductor substrate includes IV group element, silicon-germanium (SiGe), III-V group compound, III group-nitrogen compound, or II-VI group compound.
3. The method according to claim 1 , wherein the pre-determined depth is between 0.1 μm and 5 μm.
4. The method according to claim 1 , wherein the deuterium and hydrogen co-doping layer is implanted at the first semiconductor substrate through a hydrogen and deuterium ions co-beam, and an accelerated voltage of the hydrogen and deuterium ions co-beam is between 1 keV and 200 keV and a doping dosage of the hydrogen and deuterium ions co-beam is between 1016 ions/cm2 and 2×1017 ions/cm2.
5. The method according to claim 1 , wherein a material of the second semiconductor substrate includes IV group element, silicon-germanium (SiGe), III-V group compound, III group-nitrogen compound, or II-VI group compound.
6. The method according to claim 1 , wherein the first wafer is boned with the second wafer face to face at a temperature between 200 degrees centigrade and 400 degrees centigrade.
7. (canceled)
8. The method according to claim 1 , wherein the step of annealing the first wafer and second wafer further includes: heating the first wafer and the second wafer to a temperature between 600 degrees centigrade and 900 degrees centigrade; and cooling the first wafer and the second wafer to a temperature between 400 degrees centigrade and 600 degrees centigrade
9. The method according to claim 8 , wherein time for cooling the first wafer and the second wafer is between 30 minutes and 120 minutes.
10. The method according to claim 1 , wherein a thickness of the deuterium and hydrogen co-doping semiconductor layer is between 50 Å and 50000 Å.
11. The method according to claim 1 , further comprising a step of heating the second wafer to 10000 degrees centigrade once again after separating a part of the first wafer from the second wafer .
12. The method according to claim 11 , wherein time for heating the first wafer and the second wafer once again is between 30 minutes and 8 hours.
13. A silicon on insulator substrate, comprising:
a semiconductor substrate;
an insulating layer grown on a top surface of the semiconductor substrate; and
a deuterium and hydrogen co-doping semiconductor layer grown on a top surface of the insulating layer.
14. The silicon on insulator substrate according to claim 13 , wherein a material of the semiconductor substrate includes IV group element, silicon-germanium (SiGe), III-V group compound, III group-nitrogen compound, or II-VI group compound.
15. The silicon on insulator substrate according to claim 13 , wherein a thickness of the deuterium and hydrogen co-doping semiconductor layer is between 50 Å and 50000 Å.
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FR2681472B1 (en) * | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | PROCESS FOR PRODUCING THIN FILMS OF SEMICONDUCTOR MATERIAL. |
US5872387A (en) | 1996-01-16 | 1999-02-16 | The Board Of Trustees Of The University Of Illinois | Deuterium-treated semiconductor devices |
US5882987A (en) * | 1997-08-26 | 1999-03-16 | International Business Machines Corporation | Smart-cut process for the production of thin semiconductor material films |
JPH11330438A (en) * | 1998-05-08 | 1999-11-30 | Shin Etsu Handotai Co Ltd | Manufacture of soi wafer and soi wafer |
JP2007141946A (en) * | 2005-11-15 | 2007-06-07 | Sumco Corp | Method of manufacturing soi substrate, and soi substrate manufactured by same |
US7378335B2 (en) * | 2005-11-29 | 2008-05-27 | Varian Semiconductor Equipment Associates, Inc. | Plasma implantation of deuterium for passivation of semiconductor-device interfaces |
US7608521B2 (en) * | 2006-05-31 | 2009-10-27 | Corning Incorporated | Producing SOI structure using high-purity ion shower |
EP1993127B1 (en) * | 2007-05-18 | 2013-04-24 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of SOI substrate |
US7781306B2 (en) | 2007-06-20 | 2010-08-24 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor substrate and method for manufacturing the same |
US8431451B2 (en) * | 2007-06-29 | 2013-04-30 | Semicondutor Energy Laboratory Co., Ltd. | Display device and method for manufacturing the same |
JP4636110B2 (en) * | 2008-04-10 | 2011-02-23 | 信越半導体株式会社 | Manufacturing method of SOI substrate |
US8329557B2 (en) * | 2009-05-13 | 2012-12-11 | Silicon Genesis Corporation | Techniques for forming thin films by implantation with reduced channeling |
KR102189611B1 (en) * | 2014-01-23 | 2020-12-14 | 글로벌웨이퍼스 씨오., 엘티디. | High resistivity soi wafers and a method of manufacturing thereof |
CN106601663B (en) * | 2015-10-20 | 2019-05-31 | 上海新昇半导体科技有限公司 | SOI substrate and preparation method thereof |
CN107154378B (en) | 2016-03-03 | 2020-11-20 | 上海新昇半导体科技有限公司 | Silicon substrate with top layer on insulating layer and manufacturing method thereof |
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CN107154378B (en) | 2020-11-20 |
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