CN107104062B - 用于从其背面检测集成电路的半导体衬底的薄化的方法和对应的集成电路 - Google Patents

用于从其背面检测集成电路的半导体衬底的薄化的方法和对应的集成电路 Download PDF

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CN107104062B
CN107104062B CN201610579779.6A CN201610579779A CN107104062B CN 107104062 B CN107104062 B CN 107104062B CN 201610579779 A CN201610579779 A CN 201610579779A CN 107104062 B CN107104062 B CN 107104062B
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P·弗纳拉
C·里韦罗
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STMicroelectronics Rousset SAS
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Abstract

用于从其背面检测集成电路的半导体衬底的薄化的方法，包括测量表示位于绝缘区域(RIS)和下方衬底区域(CS)之间界面处两个导电接触(C1，C2)的端部(EX11，EX21)之间电阻的物理量，所述两个导电接触(C1，C2)至少部分地延伸进入所述绝缘区域(RIS)中。

Description

用于从其背面检测集成电路的半导体衬底的薄化的方法和对 应的集成电路
技术领域
本发明涉及集成电路，并且更具体地涉及从其背面检测集成电路衬底的潜在薄化。
背景技术
必须尽可能针对攻击(特别是被设计用于发现所存储的数据的攻击)保护集成电路，特别是装备具有包含敏感信息的存储器的那些集成电路。
一个可能的攻击可以由例如借由激光束而实现的聚焦的离子束(FIB－聚焦离子束)而实现。
当由犯罪者以如此方式从其背面薄化集成电路的衬底以便尽可能靠近形成在其正面上的集成电路的部件时该攻击的效率增大。
发明内容
根据一个实施例及其实施方式，因此提供了一种从其背面检测集成电路的衬底的可能薄化的方法，这是易于实施的并且在所占据表面积方面是特别紧凑小型化的。
因此，应用有利地提供了由集成电路的绝缘区域、例如“浅沟槽隔离(使用缩写STI)”类型的绝缘区域所占据的空间，以便于形成导电接触，导电接触的端部将出现在下方衬底区域中，以便于能够测量表示在这两个端部之间的电阻的量。
延伸进入绝缘区域中的这两个接触的形成对于由集成电路所占据的表面区域没有影响。此外，当薄化衬底直至其非常接近或者甚至到达时，绝缘区域将导致在这两个接触之间电阻的增大，这将是易于可测量的。
同样有利的是，由与用于制造集成电路的传统方法完美地兼容的方法而提供该接触的形成。
根据一个方面，提供了一种用于从其背面检测集成电路的半导体衬底的薄化的方法，包括测量表示在位于绝缘区域(例如浅沟槽隔离)与下方衬底区域之间的界面处的两个导电接触的端部之间电阻的物理量，两个导电接触至少部分地延伸进入所述绝缘区域中。
根据另一方面，提供了一种集成电路，包括半导体衬底，形成在衬底内的例如浅沟槽隔离类型的至少一个绝缘区域，以及包括至少部分地延伸进入所述绝缘区域中的两个导电接触的检测器，每个具有位于绝缘区域与下方衬底区域之间的界面处的第一端部，以及第二端部；两个第二端部旨在连接至集成电路，优选地被并入集成电路中，被配置用于递送表示两个第一端之间电阻值的电信号。
根据一个实施例，集成电路通常包括位于衬底顶部上的电介质层(由本领域技术人员已知为用于前金属电介质的缩写PMD)以及位于电介质层顶部上的至少第一金属化层。两个导电接触继而也延伸进入电介质层中，它们的第二端部通向第一金属化层。
通常，集成电路包括从衬底突出的数个部件。这是例如用于晶体管栅极区域的情形。这些晶体管可以是具有各种栅极氧化物厚度的单栅极晶体管，或者另外是诸如用于非易失性存储器的那些(FLASH或EEPROM存储器)的双栅极晶体管。
集成电路接着通常包括刻蚀停止层(称作CESL：接触刻蚀停止层)，显著地覆盖了部件的突出部分并且一方面位于所述介质层与所述绝缘区域之间并且另一方面位于衬底和所述绝缘区域之间。额外的导电接触随后通过刻蚀停止层与部件的一些突出部分以及与衬底的硅化区域(包括金属硅化物的区域)形成接触。
此外，用于标识可能的衬底薄化的所述两个导电接触也穿过所述刻蚀停止层。
根据另一方面，提供了一种用于形成如此前所限定的集成电路的两个导电接触的方法，其中用于形成这两个接触的刻蚀操作等同于用于形成所述额外接触的那些操作。
更具体地，根据其中半导体衬底包括硅的一个实施例，所述刻蚀操作包括相对于硅并且相对于硅化区域的金属硅化物是选择性的、被设计用于对刻蚀停止层刻蚀的最终刻蚀步骤，该最终刻蚀步骤是也允许刻蚀绝缘区域材料的定时刻蚀工艺，刻蚀时间根据所述绝缘区域深度而确定。
本发明人实际上已经观察到，为了允许未来的接触件与硅化区域形成接触，允许对刻蚀停止层刻蚀的该最终刻蚀步骤在并不具有任何特定修改的情形下也允许刻蚀绝缘区域，以便于形成被设计用于容纳允许检测衬底的可能薄化的未来接触的孔口。
为此目的，足以确定根据绝缘区域深度的刻蚀时间，以便于使得孔口出现在与下方衬底区域的界面处。此外，因为该刻蚀相对于硅并且相对于金属硅化物是选择性的，因此额外的刻蚀时间对于硅化区域将仅具有非常有限的显著影响。
因此注意在绝缘区域内这些接触的形成优选地与集成电路中现有的传统刻蚀操作兼容并且仅要求“接触”掩模的修改。
附图说明
一旦查阅了非限定性实施例及其实施方式的详细说明并且从附图将使得本发明的其他优点和特征变得明显，其中：
－图1和图2是本发明的各个实施例及其实施方式的示意说明。
具体实施方式
在图1中，参考标记IC表示集成电路，包括例如具有P型导电性的半导体衬底SB，包括例如浅沟槽隔离(STI)类型的至少一个绝缘区域RIS，其在此处所示的示例中位于具有N导电类型的阱CS的顶部上。
衬底的顶面(或正面)FS由通常为氮化硅SiN的刻蚀停止层1(CESL层)覆盖。该层1由电介质层2覆盖，通常由本领域技术人员标注为缩写PMD，PMD将刻蚀停止层1与集成电路的互连部分的第一金属化层M1分隔，集成电路的互连部分的第一金属化层M1通常由本领域技术人员标注为缩写BEOL(用于制造线后端)。
为了能够从与其顶面或正面FS相对的其背面FA检测衬底SB的潜在薄化，集成电路IC包括检测器DT，检测器DT在此包括延伸穿过介质层2、刻蚀停止层1和绝缘区域RIS的两个导电接触C1、C2。
两个接触C1和C2分别具有两个第一端部EX11和EX21，位于在绝缘区域RIS与下方衬底区域(此处为阱CS)之间的界面处。
两个接触C1和C2也分别包括两个第二端部EX12和EX22，与第一端部相对，位于在介质层2与第一金属化层M1之间的界面处。
这两个第二端部EX12和EX22与金属化层M1的两个金属迹线PST1和PST2接触，这两个接触连接至电路3。
尽管并非不可缺少，但该电路3优选地包括在集成电路IC内。
电路3在此借由非限定性示例的方式包括比较器31，其非反相输入端连接至电压分压桥30，并且其反相输入端连接至金属迹线PST2并且因此连接至接触C2。
另一金属迹线PST1以及因此另一接触C1连接至电源电压，在此为接地GND。
比较器31将存在于金属迹线PST2上的电压与由电压分压器30提供的参考电压比较，并且递送信号S，其数值表示存在于金属迹线PST2上的电压比参考电压更低或者相反的事实。
此外，电压PST2是表示在由两个接触C1和C2以及下方衬底区域CS形成的电阻性通道中流动的电流的量，并且特别地表示该下方衬底区域的电阻。
如果衬底并未薄化，对于0.8微米量级的两个接触之间的距离L以及等于0.8μm的宽度W(对于90纳米技术而言)，两个第一端部EX11和EX21之间电阻为低，例如10kΩ的量级。
相反地，如果攻击者薄化衬底SB以便于非常接近或甚至到达绝缘区域RIS，则两个第一端部EX11和EX21之间电阻显著增大(以达到例如20kΩ的数值)，这接着引起迹线PST2上电压的增大以及比较器31的切换，信号S接着代表衬底的薄化。
将明显的是，在该情形中，在此并未示出的处理机构(例如逻辑电路)可以抑制集成电路的操作。
现在更特别地参照图2以便于描述接触C1和C2的一个实施例。
图2示意性示出了集成电路的其他部件，借由非限定性示例的方式诸如两个晶体管T1和T2。
晶体管T1是具有双栅极区域P1和P2的晶体管，诸如用于例如闪存或EEPROM类型的非易失性存储器中的那些。
第一栅极区域P1由第一栅极氧化物OX1与衬底隔离，并且两个栅极区域P1和P2由第二栅极氧化物OX2相互隔离。
晶体管T2是常规的晶体管，其栅极区域P1由栅极氧化物OX3与衬底隔离。
这些晶体管的源极、漏极和栅极区域传统地包括接近它们表面的金属硅化物的区域(硅化区域)ZS1、ZS2、ZS3、ZS4和ZS5。
这些硅化区域的某些区域旨在由额外的导电接触件(例如硅化区域ZS3、ZS4和ZS5)接触。
图2示出了孔口ORD1、ORD2和ORD3，其将由一个或多个导电材料(例如钨)填充，以便于形成前述的三个额外导电接触，以及示出了两个孔口OR1和OR2，两个孔口OR1和OR2旨在由相同的导电金属填充以便于形成两个导电接触C1和C2。
这些各种孔口由刻蚀步骤得到，刻蚀步骤在此包括四个等离子刻蚀操作GV1、GV2、GV3和GV4，在所采用的处理气体方面具有显著的传统特性。
传统地，由通常本领域技术人员已知为缩写BARC的抗反射层覆盖电介质层2。该抗反射层在抗蚀剂层之下，抗蚀剂层经历光刻步骤和以如此方式暴露至光而限定各个孔口ORD1-ORD3以及OR1－OR2的位置。
随后，在抗蚀剂显影之后，执行通常是等离子刻蚀的第一刻蚀GV1以便于移除抗反射层位于抗蚀剂孔洞中的那部分。
借由非限定性示例的方式，在90纳米技术中，CF4可以在约80毫托的压力下用作处理气体。
接着，执行第二刻蚀GV2，其允许刻蚀电介质层2的第一部分。
该第二刻蚀GV2是相当激进的等离子刻蚀，其在100毫托压力下使用例如CH2F2作为处理气体。
然而，该激进刻蚀在孔口中产生“柱筒(barrel)”效应；换言之，刻蚀越多，将得到越大的孔口直径。
为此原因，在选择时间之后中断该第二刻蚀GV2以由第三刻蚀GV3替换，GV3不仅将刻蚀剩余的电介质层2，而且也以如此方式聚合了孔口的侧边以便于最终获得事实上圆柱形的孔口。
借由非限定性示例的方式，C4F6可以在约45毫托的压力下选择用于该第三等离子刻蚀GV3。
当完成了这些刻蚀操作时，各个孔口通向刻蚀停止层1。
随后执行第四等离子刻蚀GV4以便于刻蚀层1，以便于通向硅化区域ZS4、ZS5和ZS3。
借由非限定性示例的方式，此次CHF3可以在约120毫托压力下用作处理气体。
该第四刻蚀GV4是定时刻蚀，其也允许如图2中所示刻蚀绝缘区域RIS的绝缘材料(例如硅的硅化物)。
刻蚀时间取决于绝缘区域的高度h，并且本领域技术人员将知晓如何将刻蚀时间以如此方式取决于刻蚀特性而调整，以使得孔口OR1和OR2达到下方的衬底区域CS。
此外，刻蚀时间的该增长事实上对于硅化区域ZS3、ZS4和ZS5不具有影响，因为该刻蚀化学剂相对于金属硅化物并相对于硅是选择性的。
为此原因，两个接触C1和C2的形成将仅要求“接触”掩模的局部修改并且刻蚀GV4的时间相对于传统刻蚀GV4而增长。

Claims (13)

1.一种用于从其背面检测集成电路的半导体衬底的薄化的方法，包括测量表示在所述衬底内形成的、位于绝缘区域(RIS)与下方衬底区域(CS)之间的界面处的检测器的两个导电接触(C1，C2)的第一端部(EX11，EX21)之间的电阻的物理量，所述两个导电接触(C1，C2)至少部分地延伸至所述绝缘区域(RIS)中；
其中所述两个导电接触(C1，C2)中的每个导电接触包括第二端部，所述第二端部被设计用以连接至被配置用于递送表示两个第一端部之间的电阻值的电信号的电路。
2.一种集成电路，包括：
半导体衬底(SB)，
形成在所述衬底内的至少一个绝缘区域(RIS)，以及
检测器(DT)，所述检测器包括至少部分地延伸至所述绝缘区域中的两个导电接触(C1，C2)，所述两个导电接触均具有位于所述绝缘区域(RIS)与下方衬底区域(CS)之间的界面处的第一端部(EX11，EX21)，以及第二端部(EX12，EX22)，两个第二端部(EX11，EX21)被设计用以连接至被配置用于递送表示两个第一端部(EX11，EX21)之间的电阻值的电信号(S)的电路(3)。
3.根据权利要求2所述的集成电路，进一步包括位于所述衬底的顶部上的电介质层(2)，以及位于所述电介质层的顶部上的至少第一金属化层(M1)，所述两个导电接触(C1，C2)也延伸至所述电介质层中，它们的第二端部通向所述第一金属化层。
4.根据权利要求3所述的集成电路，进一步包括从所述衬底的表面突出的若干部件(T1，T2)，覆盖所述部件的突出部分并且位于所述电介质层(2)与所述衬底(SB)和所述绝缘区域(RIS)之间的刻蚀停止层(1)，额外的导电接触与所述部件的所述突出部分接触、并且通过所述刻蚀停止层(1)与所述衬底的硅化区域(ZS3，ZS4，ZS5)接触，并且所述两个导电接触(C1，C2)也穿过所述刻蚀停止层(1)。
5.根据权利要求2至4中任一项所述的集成电路，其中，所述至少一个绝缘区域(RIS)是浅沟槽隔离。
6.根据权利要求2至4中任一项所述的集成电路，其中，所述电路(3)被并入所述集成电路中。
7.根据权利要求2所述的集成电路，其中，所述半导体衬底被掺杂为第一导电类型，以及下置的半导体衬底区域被掺杂为与所述第一导电类型相反的第二导电类型。
8.一种用于形成根据权利要求5所述的集成电路的两个导电接触的方法，其中用于形成这两个接触的刻蚀操作(GV1，GV2，GV3，GV4)等同于用于形成所述额外的接触的那些操作。
9.根据权利要求8所述的方法，其中，所述半导体衬底包括硅，所述刻蚀操作包括最终刻蚀步骤(GV4)，相对于所述硅以及相对于所述硅化区域的金属硅化物是选择性的，被设计用于刻蚀所述刻蚀停止层(1)，该最终刻蚀步骤是定时刻蚀工艺，也实现刻蚀所述绝缘区域的材料，刻蚀时间根据所述绝缘区域的高度(h)而确定。
10.一种集成电路，包括：
第一导电类型的半导体衬底；
在所述半导体衬底中形成的绝缘区域；
在所述绝缘区域下方的半导体衬底的掺杂区域，所述掺杂区域被掺杂为与所述第一导电类型相反的第二导电类型；
第一金属接触，延伸穿过所述绝缘区域以形成与所述半导体衬底的掺杂区域的第一接触；
第二金属接触，延伸穿过所述绝缘区域以形成与所述半导体衬底的掺杂区域的第二接触；以及
电路，由所述半导体衬底支撑，其耦合至所述第一金属接触和所述第二金属接触中的至少一个，所述电路被配置成感测在所述第一接触和所述第二接触之间的所述半导体衬底的掺杂区域的电阻的改变。
11.根据权利要求10所述的集成电路，其中所述电路包括比较器电路，所述比较器电路具有耦合至所述第一金属接触和所述第二金属接触中的所述至少一个的第一输入。
12.根据权利要求10所述的集成电路，其中所述半导体衬底的掺杂区域被配置成响应于所述半导体衬底的背侧的减薄而呈现在所述第一接触和所述第二接触之间的电阻的改变。
13.根据权利要求10所述的集成电路，还包括在所述半导体衬底的顶部表面之上的蚀刻停止层，其中所述第一金属接触和所述第二金属接触延伸穿过所述蚀刻停止层。
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