CN105845544B - 一种半导体器件的制造方法和电子装置 - Google Patents

一种半导体器件的制造方法和电子装置 Download PDF

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CN105845544B
CN105845544B CN201510018692.7A CN201510018692A CN105845544B CN 105845544 B CN105845544 B CN 105845544B CN 201510018692 A CN201510018692 A CN 201510018692A CN 105845544 B CN105845544 B CN 105845544B
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substrate
depth
semiconductor device
capping layer
layer
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CN105845544A (zh
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黄河
李海艇
朱继光
克里夫·德劳利
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China Core Integrated Circuit Ningbo Co Ltd
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Semiconductor Manufacturing International Shanghai Corp
China Core Integrated Circuit Ningbo Co Ltd
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Priority to US14/996,091 priority patent/US9953877B2/en
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Priority to US15/922,541 priority patent/US10910274B2/en
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Abstract

本发明提供一种半导体器件的制造方法和电子装置，涉及半导体技术领域。该方法包括：提供第一衬底；在第一衬底的第一表面一侧形成至少一个晶体管，形成覆盖所述第一表面的第一介电盖帽层以及位于所述第一介电盖帽层上的互连结构；提供承载衬底，将所述第一衬底的形成有所述第一介电盖帽层的一侧与所述承载衬底相接合；从所述第一衬底的与所述第一表面相对的第二表面对所述第一衬底进行减薄处理至第二深度。该方法由于包括在第一衬底上接合承载衬底并对第一衬底进行减薄处理的步骤，因而可以用普通的体硅衬底而非薄膜绝缘体上硅衬底作为第一衬底，从而可以降低成本。本发明的电子装置，包括采用该方法制造的半导体器件，因而同样具有上述优点。

Description

一种半导体器件的制造方法和电子装置
技术领域
本发明涉及半导体技术领域，具体而言涉及一种半导体器件的制造方法和电子装置。
背景技术
在半导体技术领域中，通常需要使用薄膜绝缘体上硅(TF SOI)衬底来完成某些半导体器件(例如射频前端器件与模组)的制造。
然而，由于薄膜绝缘体上硅衬底的成本比较高，直接制约了其在半导体产业的应用。相应地，使用薄膜绝缘体上硅衬底的半导体器件(例如射频前端器件)，往往成本比较高。
因此，有必要提出一种半导体器件的制造方法，以在不使用薄膜绝缘体上硅衬底的情况下完成上述半导体器件的制造，从而降低半导体器件的成本。
发明内容
本发明提出一种半导体器件的制造方法和电子装置，可以采用体硅衬底代替薄膜绝缘体上硅衬底完成半导体器件的制造，从而降低成本。
本发明的一个实施例提供一种半导体器件的制造方法，其包括：
步骤S101：提供第一衬底，从所述第一衬底的第一表面在所述第一衬底内形成具有第一深度的浅沟槽隔离，其中所述第一深度为所述浅沟槽隔离的底部至所述第一表面的距离；
步骤S102：在所述第一衬底的第一表面一侧形成至少一个晶体管，形成覆盖所述第一表面的第一介电盖帽层以及位于所述第一介电盖帽层上的互连结构；
步骤S103：提供承载衬底，将所述第一衬底的形成有所述第一介电盖帽层的一侧与所述承载衬底相接合；
步骤S104：从与所述第一表面相对的第二表面对所述第一衬底进行减薄处理至第二深度，其中所述第二深度为减薄处理后所述第二表面至所述第一表面的距离；
步骤S105：在所述第一衬底的所述第二表面上形成第二介电盖帽层，形成贯穿所述第二介电盖帽层、所述浅沟槽隔离和所述第一介电盖帽层且与所述互连结构相连的至少一个硅通孔。
在一个示例中，在所述步骤S101中，所述第一衬底包括具有第三深度的掺杂外延层，其中，所述第三深度为所述掺杂外延层至所述第一表面的距离，所述第三深度大于等于所述第一深度。
在一个示例中，在所述步骤S101中，在形成所述浅沟槽隔离之前，从所述第一表面对所述第一衬底进行离子注入以在所述第一衬底内形成具有第四深度的第一注入掺杂层，其中，所述第四深度为所述第一注入掺杂层至所述第一表面的距离，所述第四深度大于等于所述第一深度。
在一个示例中，在所述步骤S101与所述步骤S102之间包括步骤S1012：
从所述第一表面对所述第一衬底进行离子注入以在拟形成所述晶体管的区域的下方形成具有第五深度的刻蚀停止层，其中所述第五深度为所述刻蚀停止层至所述第一表面的距离。
示例性地，所述第二深度与所述第一深度相等。
示例性地，所述第二深度与所述第三深度相等。
示例性地，所述第二深度与所述第四深度相等。
示例性地，所述第二深度与所述第五深度相等。
在一个示例中，在所述步骤S104中，所述减薄处理包括：
步骤S1041：对所述第一衬底进行背面研磨处理；
步骤S1042：对所述第一衬底进行CMP并使所述CMP停止于所述浅沟槽隔离的底部；
步骤S1043：对所述第一衬底进行湿法刻蚀至所述第二深度。
在一个示例中，在所述步骤S1041与所述步骤S1042之间还包括对所述第一衬底进行湿法刻蚀的步骤。
在一个示例中，在所述步骤S102中，所述晶体管包括源极、漏极和栅极，其中，所述源极和所述漏极位于所述第一表面的下方，所述栅极位于所述第一表面的上方。
在一个示例中，所述第一衬底包括体硅衬底。
本发明的另一个实施例提供一种电子装置，其包括电子组件以及与该电子组件相连的半导体器件，其中所述半导体器件的制造方法包括：
步骤S101：提供第一衬底，从所述第一衬底的第一表面在所述第一衬底内形成具有第一深度的浅沟槽隔离，其中所述第一深度为所述浅沟槽隔离的底部至所述第一表面的距离；
步骤S102：在所述第一衬底的第一表面一侧形成至少一个晶体管，形成覆盖所述第一表面的第一介电盖帽层以及位于所述第一介电盖帽层上的互连结构；
步骤S103：提供承载衬底，将所述第一衬底的形成有所述第一介电盖帽层的一侧与所述承载衬底相接合；
步骤S104：从所述第一衬底的与所述第一表面相对的第二表面对所述第一衬底进行减薄处理至第二深度，其中所述第二深度为减薄处理后所述第二表面至所述第一表面的距离；
步骤S105：在所述第一衬底的所述第二表面上形成第二介电盖帽层，形成贯穿所述第二介电盖帽层、所述浅沟槽隔离和所述第一介电盖帽层且与所述互连结构相连的至少一个硅通孔。
本发明的半导体器件的制造方法，通过在第一衬底上接合承载衬底并对第一衬底进行减薄处理，可以用普通的体硅衬底而非薄膜绝缘体上硅衬底作为第一衬底，因而可以降低成本。本发明的电子装置，包括采用该方法制造的半导体器件，因而同样具有上述优点。
附图说明
本发明的下列附图在此作为本发明的一部分用于理解本发明。附图中示出了本发明的实施例及其描述，用来解释本发明的原理。
附图中：
图1A、图1B、图1C、图1D、图1E和图1F为本发明的一个实施例的一种半导体器件的制造方法的相关步骤形成的结构的剖视图；
图2为本发明的一个实施例的一种半导体器件的制造方法的示意性流程图。
具体实施方式
在下文的描述中，给出了大量具体的细节以便提供对本发明更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本发明可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本发明发生混淆，对于本领域公知的一些技术特征未进行描述。
应当理解的是，本发明能够以不同形式实施，而不应当解释为局限于这里提出的实施例。相反地，提供这些实施例将使公开彻底和完全，并且将本发明的范围完全地传递给本领域技术人员。在附图中，为了清楚，层和区的尺寸以及相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本发明的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例。这样，可以预期由于例如制造技术和/或容差导致的从所示形状的变化。因此，本发明的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的注入区可导致该注入区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不意图显示器件的区的实际形状且并不意图限定本发明的范围。
为了彻底理解本发明，将在下列的描述中提出详细的步骤以及详细的结构，以便阐释本发明的技术方案。本发明的较佳实施例详细描述如下，然而除了这些详细描述外，本发明还可以具有其他实施方式。
下面，参照图1A至图1F和图2来描述本发明的一个实施例提出的一种半导体器件的制造方法。其中，图1A至图1F为本发明的一个实施例的一种半导体器件的制造方法的相关步骤形成的结构的剖视图；图2为本发明的一个实施例的一种半导体器件的制造方法的示意性流程图。
示例性地，本发明的一个实施例的半导体器件的制造方法，包括如下步骤：
步骤A1：提供第一衬底100，其中该第一衬底100包括具有第三深度D3的掺杂外延层101；从第一衬底100的第一表面(也称上表面)1001进行离子注入以在第一衬底100内形成具有第四深度D4的第一注入掺杂层102，其中第一注入掺杂层102作为刻蚀停止层；然后，从第一衬底100的第一表面1001在第一衬底100内形成具有第一深度D1的浅沟槽隔离(STI)103，如图1A所示。
其中，与第一衬底100的第一表面(也称上表面)1001相对的表面称作第二表面(也称下表面)1002，如图1A所示。
在本实施例中，如无特殊说明，“深度”一词(例如第三深度D3)是指相应的部件(例如掺杂外延层101)到第一衬底100的第一表面1001的距离。
其中，掺杂外延层101的掺杂浓度与第一衬底100的其他区域不同。
示例性地，浅沟槽隔离103包括衬垫层1031和主体结构层1032。其中，衬垫层1031可以作为后续的CMP工艺的停止层。示例性地，衬垫层1031的材料为氧化硅，主体结构层1032的材料为氮化硅。
其中，第一衬底100可以为体硅(bulk Si)衬底或其他各种合适的衬底。而不需如现有技术一样，采用薄膜绝缘体上硅衬底(TF SOI)或高阻衬底(high-resistancesubstrate)。
示例性地，D3大于等于D4，D4大于等于D1。
其中，第一衬底100也可以不包括该具有第三深度D3的掺杂外延层101。并且，本步骤中也可以省略从第一衬底100的第一表面(也称上表面)1001进行离子注入以在第一衬底100内形成具有第四深度D4的第一注入掺杂层102的步骤。
步骤A2：形成阱区(图中未示出)，通过从第一表面1001对所述第一衬底进行离子注入在拟形成晶体管的区域的下方形成具有第五深度D5的刻蚀停止层104；形成包括源极1051、漏极1052和栅极1053的晶体管105；形成覆盖第一衬底100的第一表面的介电盖帽层(dielectric capping film)106，以及位于介电盖帽层106内和表面的互连结构107，如图1B所示。
其中，第五深度D5小于第一深度D1。其中，互连结构107用于连接源极1051、漏极1052以及栅极1053中的至少一个。形成栅极1053的方法可以为先栅极工艺或后栅极工艺。
其中，晶体管105的数量为至少一个。示例性地，源极1051和漏极1052位于第一表面1001之下，栅极1053位于第一表面1001之上。
其中，在形成晶体管105的同时，还可以形成其他器件，例如二极管、电阻、电容等，在此并不进行限定。
本发明实施例的方法，直接在体硅衬底而非薄膜绝缘体上硅衬底之上形成晶体管等器件。形成晶体管等器件的工艺与在体硅衬底上形成CMOS器件的工艺完成相同。
步骤A3：提供承载衬底200，将第一衬底100的形成有介电盖帽层106的一侧与承载衬底200相接合，如图1C所示。
在一个示例中，在将第一衬底100的形成有介电盖帽层106的一侧与承载衬底200相接合之前，先第一衬底100的形成有介电盖帽层106的一侧的表面上以及承载衬底200相应的表面上分别形成键合盖帽层300，如图1C所示。示例性地，键合盖帽层300的材料可以为氧化硅或其他合适的材料。
示例性地，将第一衬底100与承载衬底200相接合的方法可以为熔融键合(fusionbonding)或其他合适的方法。
其中，承载衬底200可以为硅衬底或其他合适的衬底。在一个示例中，承载衬底200与第一衬底100具有相同的形状和尺寸。
其中，承载衬底200可以在后续对第一衬底100进行减薄处理的过程中对第一衬底100提供支撑。
步骤A4：从与第一表面1001相对的第二表面1002对第一衬底100进行减薄处理，所述减薄处理包括：对第一衬底100进行背面研磨(backside grinding)至第六深度D6(图中未示出)，然后对第一衬底100进行湿法刻蚀至第二深度D2，如图1D所示。
其中，第六深度D6大于第二深度D2。
其中，所采用的背面研磨方法可以为CMP(化学机械研磨)或其他合适的工艺。所述湿法刻蚀可以采用各种可行的刻蚀液，例如TMAH等，在此并不进行限定。
其中，在本步骤中，在对第一衬底100进行湿法刻蚀至第二深度D2之后，还可以包括对第一衬底100(包括承载衬底200)进行低温退火的步骤。
步骤A5:继续从与第一表面1001相对的第二表面1002对第一衬底100进行减薄处理，包括：对第一衬底100进行CMP并使所述CMP停止于浅沟槽隔离103的底部(示例性地，衬垫层1031作为该CMP的停止层)，然后对第一衬底100进行湿法刻蚀至第五深度D5。经过该步骤，形成的结构如图1E所示。
其中，该CMP可以采用各种可行的CMP工艺。该湿法刻蚀可以使用各种可行的刻蚀液，例如TMAH等。
其中，在本步骤中，浅沟槽隔离103的衬垫层1031可以作为该CMP的停止层。
其中，上述步骤A4和步骤A5共同实现从第二表面1002对第一衬底100进行减薄处理的过程。
本发明实施例的方法，由于包括在第一衬底上接合承载衬底并对第一衬底进行减薄处理的步骤，因此，第一衬底100可以采用普通的体硅(bulk Si)衬底作为基本的器件层衬底，而不必采用薄膜绝缘体上硅衬底(TF SOI)或高阻衬底(high-resistancesubstrate)，因此可以降低成本。
并且，本实施例的方法通过同时使用背面研磨、CMP、湿法刻蚀等方法(通过多个停止层相配合)进行减薄处理，可以对第一衬底进行精确减薄处理至希望的厚度，并保证所希望的均一性。
此外，由于硅衬底之间的键合工艺已经越来越成熟，本实施例的方法在降低成本的同时，也可以保证制得的半导体器件的良率。
步骤A6：在第一衬底100的第二表面1002形成介电盖帽层108，形成贯穿介电盖帽层108、浅沟槽隔离103、介电盖帽层106且与位于介电盖帽层106表面的互连结构107相连的至少一个硅通孔(TSV)109；在介电盖帽层108上形成与硅通孔109的另一端相连的互连结构110，如图1F所示。
示例性地，形成硅通孔(TSV)109的方法包括：刻蚀形成贯穿介电盖帽层108、浅沟槽隔离103、介电盖帽层106的过孔；
在该过孔内填充导电材料；
通过CMP去除过量的导电材料以形成硅通孔109。
其中，导电材料109可以为金属或其他合适的材料。
互连结构110的材料可以为导电金属(例如铜)或其他合适的材料。
至此，完成了本发明实施例的半导体器件的制造方法的关键步骤的介绍。本领域的技术人员可以理解，除上述的步骤A1至A6外，在相邻的步骤之间以及步骤A6之后，还可以包括其他可行的步骤，在此并不进行限定。
本发明实施例的半导体器件的制造方法，通过在第一衬底上接合承载衬底并对第一衬底进行减薄处理，可以用普通的体硅衬底而非薄膜绝缘体上硅衬底作为第一衬底，因此可以降低成本。
图2示出了本发明实施例提出的一种半导体器件的制造方法的一种示意性流程图，用于简要示出上述方法的典型流程。具体包括：
在步骤S101中，提供第一衬底，从所述第一衬底的第一表面在所述第一衬底内形成具有第一深度的浅沟槽隔离，其中所述第一深度为所述浅沟槽隔离的底部至所述第一表面的距离；
在步骤S102中，在所述第一衬底的第一表面一侧形成至少一个晶体管，形成覆盖所述第一表面的第一介电盖帽层以及位于所述第一介电盖帽层上的互连结构；
在步骤S103中，提供承载衬底，将所述第一衬底的形成有所述第一介电盖帽层的一侧与所述承载衬底相接合；
在步骤S104中，从所述第一衬底的与所述第一表面相对的第二表面对所述第一衬底进行减薄处理至第二深度，其中所述第二深度为减薄处理后所述第二表面至所述第一表面的距离；
在步骤S105中，在所述第一衬底的所述第二表面上形成第二介电盖帽层，形成贯穿所述第二介电盖帽层、所述浅沟槽隔离和所述第一介电盖帽层且与所述互连结构相连的至少一个硅通孔。
本发明的另一个实施例提供一种电子装置，其包括电子组件以及与该电子组件相连的半导体器件。其中，该半导体器件为根据如上所述的半导体器件的制造方法所制得的半导体器件。该电子组件可以为任何合适的组件。
示例性地，该半导体器件的制造方法包括：
步骤S101：提供第一衬底，从所述第一衬底的第一表面在所述第一衬底内形成具有第一深度的浅沟槽隔离，其中所述第一深度为所述浅沟槽隔离的底部至所述第一表面的距离；
步骤S102：在所述第一衬底的第一表面一侧形成至少一个晶体管，形成覆盖所述第一表面的第一介电盖帽层以及位于所述第一介电盖帽层上的互连结构；
步骤S103：提供承载衬底，将所述第一衬底的形成有所述第一介电盖帽层的一侧与所述承载衬底相接合；
步骤S104：从所述第一衬底的与所述第一表面相对的第二表面对所述第一衬底进行减薄处理至第二深度，其中所述第二深度为减薄处理后所述第二表面至所述第一表面的距离；
步骤S105：在所述第一衬底的所述第二表面上形成第二介电盖帽层，形成贯穿所述第二介电盖帽层、所述浅沟槽隔离和所述第一介电盖帽层且与所述互连结构相连的至少一个硅通孔。
本实施例的电子装置，可以是手机、平板电脑、笔记本电脑、上网本、游戏机、电视机、VCD、DVD、导航仪、照相机、摄像机、录音笔、MP3、MP4、PSP等任何电子产品或设备，也可为任何包括该半导体器件的中间产品。
本发明实施例的电子装置，由于使用了根据上述方法制得的半导体器件，因而同样具有上述优点。
本发明已经通过上述实施例进行了说明，但应当理解的是，上述实施例只是用于举例和说明的目的，而非意在将本发明限制于所描述的实施例范围内。此外本领域技术人员可以理解的是，本发明并不局限于上述实施例，根据本发明的教导还可以做出更多种的变型和修改，这些变型和修改均落在本发明所要求保护的范围以内。本发明的保护范围由附属的权利要求书及其等效范围所界定。

Claims (11)

1.一种半导体器件的制造方法，其特征在于，所述方法包括：
步骤S101：提供第一衬底(100)，从所述第一衬底的第一表面(1001)在所述第一衬底内形成具有第一深度的浅沟槽隔离(103)，其中所述第一深度为所述浅沟槽隔离的底部至所述第一表面的距离，所述第一衬底包括体硅衬底；
步骤S1012：从所述第一表面对所述第一衬底进行离子注入以在拟形成晶体管的区域的下方形成具有第五深度的刻蚀停止层(104)，其中所述第五深度为所述刻蚀停止层至所述第一表面的距离，所述第五深度小于所述第一深度；
步骤S102：在所述第一衬底的第一表面一侧形成至少一个晶体管(105)，形成覆盖所述第一表面的第一介电盖帽层(106)以及位于所述第一介电盖帽层上的互连结构(107)，所述互连结构与所述晶体管连接；
步骤S103：提供承载衬底(200)，将所述第一衬底的形成有所述第一介电盖帽层的一侧与所述承载衬底相接合；
步骤S104：从与所述第一表面相对的第二表面对所述第一衬底进行减薄处理至第二深度，其中所述第二深度为减薄处理后所述第二表面至所述第一表面的距离，所述减薄处理还包括对所述第一衬底进行刻蚀，以从所述第二深度减薄至所述第五深度；
步骤S105：在所述第一衬底的所述第二表面上形成第二介电盖帽层(108)，所述第二介电盖帽层覆盖所述第二表面，以及形成贯穿所述第二介电盖帽层、所述浅沟槽隔离和所述第一介电盖帽层且与所述互连结构相连的至少一个硅通孔(109)。
2.如权利要求1所述的半导体器件的制造方法，其特征在于，在所述步骤S101中，所述第一衬底包括具有第三深度的掺杂外延层(101)，其中，所述第三深度为所述掺杂外延层至所述第一表面的距离，所述第三深度大于等于所述第一深度。
3.如权利要求1所述的半导体器件的制造方法，其特征在于，在所述步骤S101中，在形成所述浅沟槽隔离之前，从所述第一表面对所述第一衬底进行离子注入以在所述第一衬底内形成具有第四深度的第一注入掺杂层(102)，其中，所述第四深度为所述第一注入掺杂层至所述第一表面的距离，所述第四深度大于等于所述第一深度。
4.如权利要求1所述的半导体器件的制造方法，其特征在于，所述第二深度与所述第一深度相等。
5.如权利要求2所述的半导体器件的制造方法，其特征在于，所述第二深度与所述第三深度相等。
6.如权利要求3所述的半导体器件的制造方法，其特征在于，所述第二深度与所述第四深度相等。
7.如权利要求1所述的半导体器件的制造方法，其特征在于，所述第二深度与所述第五深度相等。
8.如权利要求1所述的半导体器件的制造方法，其特征在于，在所述步骤S104中，所述减薄处理还包括：
步骤S1041：对所述第一衬底进行背面研磨处理；
步骤S1042：对所述第一衬底进行CMP并使所述CMP停止于所述浅沟槽隔离的底部；
步骤S1043：对所述第一衬底进行湿法刻蚀至所述第二深度。
9.如权利要求8所述的半导体器件的制造方法，其特征在于，在所述步骤S1041与所述步骤S1042之间还包括对所述第一衬底进行湿法刻蚀的步骤。
10.如权利要求1所述的半导体器件的制造方法，其特征在于，在所述步骤S102中，所述晶体管包括源极(1051)、漏极(1052)和栅极(1053)，其中，所述源极和所述漏极位于所述第一表面的下方，所述栅极位于所述第一表面的上方。
11.一种电子装置，其特征在于，包括电子组件以及与该电子组件相连的半导体器件，其中所述半导体器件的制造方法包括：
步骤S101：提供第一衬底，从所述第一衬底的第一表面在所述第一衬底内形成具有第一深度的浅沟槽隔离，其中所述第一深度为所述浅沟槽隔离的底部至所述第一表面的距离，所述第一衬底包括体硅衬底；
步骤S1012：从所述第一表面对所述第一衬底进行离子注入以在拟形成晶体管的区域的下方形成具有第五深度的刻蚀停止层(104)，其中所述第五深度为所述刻蚀停止层至所述第一表面的距离，所述第五深度小于所述第一深度；
步骤S102：在所述第一衬底的第一表面一侧形成至少一个晶体管，形成覆盖所述第一表面的第一介电盖帽层以及位于所述第一介电盖帽层上的互连结构，所述互连结构与所述晶体管连接；
步骤S103：提供承载衬底，将所述第一衬底的形成有所述第一介电盖帽层的一侧与所述承载衬底相接合；
步骤S104：从所述第一衬底的与所述第一表面相对的第二表面对所述第一衬底进行减薄处理至第二深度，其中所述第二深度为减薄处理后所述第二表面至所述第一表面的距离，所述减薄处理还包括对所述第一衬底进行刻蚀，以从所述第二深度减薄至所述第五深度；
步骤S105：在所述第一衬底的所述第二表面上形成第二介电盖帽层，所述第二介电盖帽层覆盖所述第二表面，以及形成贯穿所述第二介电盖帽层、所述浅沟槽隔离和所述第一介电盖帽层且与所述互连结构相连的至少一个硅通孔。
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