CN107039515A - 高电压场效应晶体管 - Google Patents

高电压场效应晶体管 Download PDF

Info

Publication number
CN107039515A
CN107039515A CN201710000739.6A CN201710000739A CN107039515A CN 107039515 A CN107039515 A CN 107039515A CN 201710000739 A CN201710000739 A CN 201710000739A CN 107039515 A CN107039515 A CN 107039515A
Authority
CN
China
Prior art keywords
cylindrical
drain region
semi
channel region
conducting material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201710000739.6A
Other languages
English (en)
Other versions
CN107039515B (zh
Inventor
H·W·田
R·周
B·舒-金
G·杜威
J·卡瓦列罗斯
M·V·梅茨
N·慕克吉
R·皮拉里塞泰
M·拉多萨夫列维奇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to CN201710000739.6A priority Critical patent/CN107039515B/zh
Publication of CN107039515A publication Critical patent/CN107039515A/zh
Application granted granted Critical
Publication of CN107039515B publication Critical patent/CN107039515B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02603—Nanowires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66469—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with one- or zero-dimensional channel, e.g. quantum wire field-effect transistors, in-plane gate transistors [IPG], single electron transistors [SET], Coulomb blockade transistors, striped channel transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0676—Nanowires or nanotubes oriented perpendicular or at an angle to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/068—Nanowires or nanotubes comprising a junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Nanotechnology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electromagnetism (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Inorganic Chemistry (AREA)
  • Materials Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

本发明描述了适合于高电压和高频率操作的晶体管，特别是高电压场效应晶体管。在衬底上垂直地或水平地设置纳米线。所述纳米线的纵向长度被限定到第一半导体材料的沟道区中，源极区与所述沟道区的第一端电耦合，漏极区与所述沟道区的第二端电耦合，并且非本征漏极区设置于所述沟道区与漏极区之间。所述非本征漏极区的带隙比所述第一半导体的带隙宽。包括栅极导体和栅极绝缘体的栅极堆叠体同轴地完全环绕所述沟道区，漏极和源极接触部类似地也同轴地完全环绕所述漏极和源极区。

Description

高电压场效应晶体管
本申请是申请日为2011年12月19日、发明名称为“高电压场效应晶体管”的专利申请201180076395.8的分案申请。
技术领域
本发明的实施例总地涉及微电子器件和制造，并且尤其涉及高电压场效应晶体管(FET)。
背景技术
在过去几十年中已经以多种容量实施了片上系统(SOC)。SOC解决方案提供了板级部件集成所比不上的缩放优势。尽管长时间以来将模拟电路和数字电路集成到同一衬底上来提供SOC(其提供混合的信号能力)的形式，但是用于诸如智能手机和平板电脑之类的移动计算平台的SOC解决方案仍然难以得到，因为这些设备通常包括利用高电压、高功率和高频率中的一个或多个来操作的部件。同样，常规的移动计算平台通常利用Ⅲ-Ⅴ族化合物半导体(例如GaAs异质结双极晶体管(HBT))来在GHz载频处产生足够的功率放大，并且利用横向扩散硅MOS(LDMOS)技术来管理电压转换和功率分配(包括升压和/或降压转换的电池电压调节，等等)。于是，实现CMOS技术的常规的硅场效应晶体管需要第三种器件技术，其用于移动计算平台内的逻辑和控制功能。
用于移动计算平台中的多种晶体管技术限制了器件作为整体的可扩展性，并且因此是更强功能、更高集成水平、更低成本、更小形状因子等的障碍。因此，尽管用于将这三种器件技术中的两种或更多器件技术集成的移动计算空间的SOC解决方案是有吸引力的，但是SOC解决方案的一个障碍是缺乏具有低特征导通电阻(Ron)、和足够高的击穿电压(BV)(即，晶体管在出现经由漏极到栅极区处的雪崩和/或能带到能带隧道的击穿之前，能够承受的最大漏极到源极电压VDS)二者的晶体管技术。
图1A中能够一般地示出高电压平面FET中的权衡，图1A绘出Ron与BV之间的关系的曲线。针对形成其上制造平面FET的平面的各种材料示出了Baliga极限。如从图1A中可以看到的，选择高迁移率材料来改进Ron通常导致减小的BV，因为大多数高载流子迁移率材料(例如InAs)具有低本征击穿场。本征击穿场是半导体的带隙的函数，以致诸如仅具有0.36eV的能带的InAs(～25000cm2/V-s)之类的高迁移率材料仅具有0.04MV/cm的本征击穿场。诸如GaN(Eg＝3.18eV)之类的高带隙半导体具有大约2000cm2/V-s或更小的较低迁移率，尽管其具有3.3MV/cm的高本征击穿场。对于给定的带隙，晶体管的击穿电压是栅极到漏极距离Lgd的函数，如示出了具有轻掺杂的漏极到栅极区Lgd的典型平面高电压FET(例如，LDMOS器件)的图1B的截面视图中所示。
进一步参考图1B，Ron极限是晶体管在给定BV下能够获得的最低的导通状态电阻，并且Ron越低，晶体管就越有利，因为功率耗散减小，可以提供更大的驱动电流和更大的Fmax(即，单位功率增益频率，或最大振荡频率)。Ron包括源极和漏极接触电阻(RCC)、沟道电阻(Rch)、以及漏极到栅极漂移电阻(Rdrift)，如图1B中所示出的。尽管在大电压下Rdrift在Ron中占主要地位，但是在较低电压(例如，<100V)下，Rcc和Rch变得更与Rdrift相当。因此，只要保留了期望的击穿特性，则对于给定的沟道长度，具有减小的Rch的器件能够更接近给定材料的Baliga极限。因此，这种器件对于许多电路应用将极为有利，尤其是集成了具有移动计算平台内的逻辑和控制功能的RF集成电路(RFIC)和/或功率管理集成电路(PMIC)的SOC解决方案。
附图说明
本发明的实施例是通过示例的方式而不是通过限制的方式示出的，并且结合附图参考下文的具体实施方式可以更充分地理解本发明的实施例，附图中：
图1A是各种半导体材料的BV与特征导通电阻之间的关系的曲线图；
图1B是具有轻掺杂的漏极到栅极区的典型的平面高电压FET的截面视图；
图2A是根据实施例的非平面高电压晶体管的等距图；
图2B是根据实施例的非平面高电压晶体管的等距图；
图3是示出根据实施例的制造非平面高电压晶体管的方法的流程图；
图4A、4B、4C、4D和4E是根据图3中示出的方法的实施例制造的非平面高电压晶体管的等距图；
图5A、5B、5C、5D、5E、5F、5G和5H是根据图3中示出的方法的实施例制造的非平面高电压晶体管的等距图；以及
图6是根据本发明的实施例的移动计算平台的SOC实施方式的功能性框图。
具体实施方式
在下文的说明书中，阐述了大量的细节，然而，对于本领域技术人员来说显而易见的是，可以在没有这些具体细节的情况下实践本发明。在一些实例中，以框图的形式、而不是以细节的形式示出公知的方法和器件，以避免使本发明难以理解。整个说明书中提及的“实施例”表示结合实施例描述的特定特征、结构、功能或特性包含在本发明的至少一个实施例中。因此，在整个说明书的各处出现的术语“在实施例中”并非必需涉及本发明的相同的实施例。此外，特定特征、结构、功能或特性可以以任何适合的方式组合在一个或多个实施例中。例如，第一实施例可以与第二实施例组合，只要这两个实施例不互相排斥。
术语“耦合”和“连接”，以及它们的衍生物，在本文中可以用于描述部件之间的结构关系。应该理解的是，这些术语并不是要作为彼此的同义词。相反，在特定实施例中，“连接”可以用于表明两个或更多元件彼此直接的物理或电接触。“耦合”可以用于表明两个或更多元件彼此直接或非直接(在它们之间有其它中间元件)的物理或电接触，和/或两个或更多元件彼此协作或相互作用(例如，构成因果关系)。
本文中使用的术语“在……之上”、“在……之下”、“在……之间”和“在……上”指的是一个材料层相对其它材料层的相对位置。像这样，例如，将一层设置在另一层之上或之下可以直接与所述另一层接触，或可以具有一个或多个中间层。此外，将一层设置在两层之间可以与两层直接接触，或可以具有一个或多个中间层。相比之下，第一层在第二层“上”是与第二层直接接触。
本文中描述的是半导体器件和制造技术的实施例，所述制造技术通过如下方式来减小沟道电阻Rch：在沟道区中采用具有高迁移率的第一半导体材料，同时通过在器件沟道与漏极接触部之间的非本征漏极区中进一步包含具有较高带隙的第二半导体材料来提供高BV。在示例性实施例中，栅极结构环绕沟道区的所有边，以形成本文中被称为纳米线的结构。水平和垂直纳米线结构二者被示出为替换的实施例，以简洁地证明本发明在非平面实施例的背景下的广泛应用。然而，还应该注意的是，平面器件可以类似地采用第一和第二半导体材料来实现Rch和BV方面的至少一些所描述的益处。因此，应该领会的是，技术人员可以容易地实现本文中在纳米线器件的背景下所描述的一种或多种技术的平面实施方式。
图2A是根据实施例的非平面高电压晶体管200的等距图。通常，高电压晶体管200可以是任何少数或多数载流子栅极电压控制的器件，例如但不限于：金属氧化物半导体场效应晶体管(MOSFET)、或高电子迁移率晶体管(HEMT)。因此，尽管图2A中所示出的示例性实施例是HEMT，但是可以对高电压晶体管200做出本领域所公知的修改，以实现与示例性HEMT实施例共享相关属性的MOSFET。类似地，还可以在不脱离本发明的范围的情况下实现其它公知的栅极电压控制的器件。
高电压晶体管200包括至少一个非平面晶体半导体主体，所述非平面晶体半导体主体在平行于衬底层205的顶表面的平面上，但通过除了形成主体的晶体半导体或形成衬底层205的材料以外的中间材料而与顶部衬底表面物理分离，以形成横向取向的纳米线210A。对于本文中描述的实施例，纳米线的横截面几何形状可以从圆形到矩形大幅变化，从而使纳米线210A的厚度(即，在z维度上)可以大约等于纳米线210A的宽度(即，在y维度上)，或者纳米线210A的厚度和宽度可以彼此明显不同(即，物理上类似于带状，等等)，以形成圆柱形和平行六面体半导体主体。对于示例性实施例而言，纳米线210A的最窄的宽度在5到50纳米(nm)之间。
如图2A中所进一步示出的，高电压晶体管200的纵向长度L在源极区220A、漏极区230A、非本征漏极区235A、以及设置于其间的沟道区245A之间被划分。沿着纵向长度L，在沟道区245A和非本征漏极区235A内使用具有不同带隙的多种半导体材料，以获得低Ron和高BV。尽管为沟道区245A和非本征漏极区235A选择的半导体材料可能随着实施方式变化，但是非本征漏极区235A将包括带隙大于沟道区245A的带隙的半导体材料。如本文中进一步描述的，在特定实施例中，纳米线架构和制造技术用来在沟道区245A内包含具有牺牲性的半导体，以选择性地增加沟道区245A中所采用的第一半导体材料的带隙，从而使非本征漏极区235A对场诱导击穿机制具有更大的电阻。在其它实施例中，纳米线架构和制造工艺用来将沟道区245A中所采用的至少第一半导体材料选择性地替换为非本征漏极区235A内的具有更大带隙的重新生长的材料。在其它实施例中，纳米线架构和制造技术用来由单独的半导体材料形成沟道区、非本征漏极区、以及甚至源极区中的每一个，所有所述单独的半导体材料都具有共同的晶体结构和取向(即，单晶)。
高电压晶体管200设置于衬底层205上。在实施例中，衬底层205是绝缘或半绝缘的，和/或具有设置于其上的绝缘或半绝缘层，纳米线210A设置在绝缘或半绝缘层之上。在一个所述实施例中，衬底层205是生长(图1A中所示)在支撑衬底上或转移到施主衬底上(未示出支撑和施主衬底)的半导体的顶层。在特定实施例中，衬底层205包括硅支撑衬底，半导体层在硅支撑衬底上外延生长，然而，所述支撑衬底还可以具有替换的材料(其可以或可以不与硅结合)，包括但不限于锗、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓、或锑化镓、碳(SiC)和蓝宝石。在其它实施例中，其上设置晶体管200的衬底层205是电介质层，因而衬底层205是掩埋氧化物(BoX)，其可以例如通过将形成纳米线210A的一个或多个半导体层转移到衬底层205上来形成。
在沟道区245A内，纳米线210A具有比多晶材料大得多的长程有序(long rangeorder)。在示例性实施例中，沟道区245A基本上是单晶，尽管低水平的晶体缺陷仍然可能作为不完美外延生长过程的工件而出现。在沟道区245A内，纳米线210A可以具有形成元素半导体或化合物半导体的一个或多个半导体元件。通常，沟道区245A中的半导体材料具有相对高的载流子迁移率。在实施例中，为使杂质散射最小，沟道区245A是基本上未掺杂的半导体(即，杂质浓度最小化)。在第一示例性HEMT实施例中，沟道区245A实质上由氮化铟(InN)构成。与GaN沟道相比，由于InN的更大的载流子迁移率(与1900cm2/Vs相比的2700cm2/Vs)，所以Ron可以足足减小～30％(其中InN还用于源极区220A和漏极区230A中)。在第二示例性HEMT实施例中，沟道区245A包括InN或GaN的任何三元合金，例如氮化铝铟(AlxIn1-xN)或氮化铝镓(AlxGa1-xN)，其中x小于1。在第三示例性HEMT实施例中，沟道区245A实质上由砷化铟(InAs)构成。在第四示例性HEMT实施例中，沟道区实质上由GaAs构成。在第一示例性MOSFET实施例中，沟道区245A实质上由硅(Si)构成。在第二示例性MOSFET实施例中，沟道区245A实质上由锗(Ge)构成。
对于HEMT实施例而言，至少在沟道区245A内，纳米线210A覆盖有晶体半导体层240，其设置于纳米线210A的侧壁、顶表面、和/或底表面中的一个或多个之上。在示例性实施例中，晶体半导体层240直接设置在纳米线210A上。晶体半导体层240是带隙比沟道区245A内的纳米线210A中所使用的第一半导体材料的带隙宽的材料，以在沟道区245A内形成异质界面。例如，在沟道区245A是GaN的实施例中，晶体半导体层240是AlN、AlInN或AlInGaN。优选地，晶体半导体层240基本上是单晶(即，厚度小于临界厚度)，并且与沟道区245A内的纳米线210A中所使用的半导体材料晶格匹配。在一个有利的实施例中，设置于纳米线210A上的晶体半导体层240是非本征漏极区235A中所使用的第二半导体材料(例如，212A)，尽管非本征漏极区235A中所使用的第二半导体材料更薄，以允许完全环绕栅极堆叠体250A。在示例性实施例中，晶体半导体层240是在纳米线210A的壁上形成的电荷感应层，从而可以在与壁相邻处形成二维电子气(2DEG)。晶体半导体层240还可以用作沉积在纳米线210A的相对壁上的背面势垒(barrier)。在替代的实施例中，在纳米线210A的顶部和底部上形成晶体半导体层240，从而可以在邻近顶表面处形成二维电子气(2DEG)，并且在邻近底表面处形成背面势垒。背面势垒和电荷感应层均可以由栅极叠置体250选通(gate)。如图2A中所进一步示出的，晶体半导体层240还覆盖了非本征漏极区235内的半导体。在非本征漏极区235内，晶体半导体层240用作电荷感应层。
如图2A中由沟道区245A内的虚线所进一步示出的，包括栅极绝缘体和栅极导体的栅极堆叠体250A同轴地完全环绕纳米线210，以调制沟道区245A。栅极堆叠体250A包括栅极导体，其通过设置于栅极导体之下的栅极电介质材料与纳米线210A电隔离，以减小栅极导体与纳米线210A之间的泄漏电流。通常，栅极电介质材料可以包括在本领域中公知的用于FET栅极电介质的任何材料中的一种或多种材料，并且优选为高K电介质(即，介电常数大于氮化硅(Si3N4)的介电常数)，例如但不限于诸如氧化钆(Gd2O3)、氧化蛤(HfO2)之类的高K氧化物；诸如HfSiO、TaSiO、AlSiO之类的高K硅酸盐；以及诸如HfON之类的高K氮化物。在实施例中，栅极堆叠体250A包括沿着沟道区245A内的纳米线210A的全部周长表面(侧壁、顶部和底部)的导电栅极(电极)材料层。通常，栅极导体可以是本领域中公知的用于晶体管栅极电极的任何材料。在实施例中，栅极导体包括功函数金属，可以选择该功函数金属来获取期望的阈值电压(Vt)(例如，大于0V，等等)。示例性导电栅极材料包括钨(W)、铝(Al)、钛(Ti)、钽(Ta)、镍(Ni)、钼(Mo)、锗(Ge)、铂(Pt)、金(Au)、钌(Ru)、钯(Pd)、铱(Ir)、它们的合金及其硅化物、碳化物、氮化物、磷化物和碳氮化物。
纳米线210A还包括嵌入在源极接触部222A内的源极区220A，源极接触部222A同轴地完全环绕源极区220A内的纳米线210A。在特定实施例中，源极区220A内的纳米线210A与沟道区245A内的纳米线210A保持相同的单晶(moncrystallinity)。在示例性实施例中，在源极区220A内，纳米线210A至少包括与沟道区245A中存在的相同的高迁移率、窄带隙半导体材料。例如，第一示例性HEMT实施例中的InN和第一示例性MOSFET实施例中的Si。然而，源极区220A内的半导体还可以包括诸如n型杂质(即，N+)之类的掺杂剂的浓度。源极接触部222A同轴环绕源极区220A内的纳米线210A，以填充纳米线210A与衬底层205之间的间隙。在实施例中，源极接触部222A包括金属化层。源极接触部222A还可以包括与纳米线210A不同成分的外延生长的半导体。这种半导体可能为了减小欧姆金属化的接触电阻，或为了提供隧道结(例如，环绕源极区220A内的纳米线210A的p+层)。可以利用这种隧道结来提供超陡峭的(ultra steep)导通和截止(即，改进的亚阈值性能)，以减小截止状态泄漏电流。
纳米线210A还包括嵌入在漏极接触部232A内的漏极区230A，漏极接触部232A同轴地完全环绕漏极区230A内的纳米线210A。在特定实施例中，漏极区230A内的纳米线210A与沟道区245A内的纳米线210A保持相同的单晶。在示例性实施例中，在漏极区230A内，纳米线210A至少包括与沟道区245A中存在的相同的高迁移率、窄带隙半导体材料(例如，第一示例性HEMT实施例中的InN和第一示例性MOSFET实施例中的Si)。然而，漏极区230A内的半导体还可以包括诸如n型杂质(即，N+)之类的高浓度掺杂剂，正如源极区220A内的一样。漏极接触部232A同轴环绕漏极区230A内的纳米线210A，以填充纳米线210A与衬底层205之间的间隙。与源极接触部222A类似，漏极接触部232A的实施例包括金属化层，并且同样还可以包括与纳米线210A不同成分的外延生长半导体。
如图2A中所示，源极接触部222A与沟道区245A间隔第一纵向长度，所述第一纵向长度与将栅极堆叠体250A中的栅极导体与源极接触部222A隔离的电介质间隔体255的厚度相对应。漏极接触部232A与沟道区245A间隔第二纵向长度，第二纵向长度与非本征漏极区235A相对应。非本征漏极区235A的纵向长度是所期望的BV的函数，因为其功能上与图1B中所示出的Lgd相对应。尽管在一些实施例中，非本征漏极区235A可以仅具有间隔体255的纵向长度，但是当非本征漏极区235A具有大于源极接触部222A与沟道区245A之间的间隔的纵向长度时，则可以有利地获得较大的BV。
非本征漏极区235A包括第二半导体材料，其具有比第一半导体材料的带隙更宽的带隙。在实施例中，至少沟道区245A不存在所述第二半导体材料，并且在示例性实施例中，源极区220A和漏极区230A也不存在所述第二半导体材料。非本征漏极区235A内的第二半导体材料可以根据沟道区245A内的纳米线210A所使用的材料而改变。对于具有InN的沟道区的示例性实施例而言，非本征漏极区235A包括GaN的第二半导体材料。利用包括GaN的非本征漏极区235A，可以在小Lgd尺寸下获得10V或更大的BV。对于具有GaAs的沟道区的示例性实施例而言，非本征漏极区235A包括AlGaAs的第二半导体材料。对于具有InAs的沟道区的示例性实施例而言，非本征漏极区235A包括InAlAs的第二半导体材料。对于具有Ge的沟道区的示例性实施例而言，非本征漏极区235A包括SiGe、Si、或Ⅲ-Ⅴ材料的第二半导体材料。对于具有Si的沟道区的示例性实施例而言，非本征漏极区235A包括SiC的第二半导体材料。利用Si沟道，可以将Ron足足减小～99％(与SiC对比)，因为载流子迁移率较大(与140cm2/Vs对比的1350cm2/Vs)，然而，仍然可以利用非本征漏极区235A中所使用的SiC来获得10V的BV。在其它实施例中，非本征漏极区235A内的一种或多种半导体材料被轻掺杂以杂质(例如，n型)。
在一个示例性实施例中，非本征漏极区235A是第一和第二半导体材料的合金，以提供介于第一与第二半导体材料的带隙之间的带隙。如图2A中的空心箭头所示出的，在非本征漏极区235A内，第一和第二半导体材料的合金是无序的多层结构的形式。多层结构包括夹置在较宽带隙的第二半导体材料212A和212B的相对的层之间的纳米线210A的窄带隙第一半导体材料，其延伸穿过非本征漏极区235A，并且将沟道区245A耦合到漏极区230A。利用与第二半导体材料212A和212B相邻的纳米线210A的相对的侧，可以在与纳米线210A的沟道区245A和漏极区230A物理耦合的非本征漏极区235A的部分内实现好的合金均匀性。值得注意的是，尽管仅需要对半导体主体进行底切来形成纳米线210A，但是为了实现所示出的非本征漏极区235A内的多层结构，第二半导体材料212B还需要仅出现在非本征漏极区235A中(即，不出现在沟道区245A中)。因此，由于半导体材料212B，非本征漏极区235A的顶表面从衬底层205提高到高于纳米线210A的顶表面的高度。
在实施例中，如图2A中所示，高电压晶体管200包括纳米线210A和210B的垂直堆叠体，以实现针对衬底层205上的给定覆盖面积(footprint)的较大的电流载流能力(例如，较大的驱动电流)。取决于制造限制，可以垂直堆叠任何数量的纳米线210，并且每个纳米线的纵轴基本上与衬底层205的顶表面平行。在示例性实施例中，纳米线210A、210B中的每一个纳米线在沟道区245A内具有相同的第一半导体材料。在其它实施例中，纳米线210A和210B中的每一个纳米线被栅极堆叠体250A同轴环绕。在示例性实施例中，至少栅极堆叠体250A的栅极电介质层将设置于纳米线210A与210B之间，但是优选地，栅极导体也出现在纳米线210A、210B中的每个纳米线的沟道区之间。
在示出的实施例中，多个纳米线210A、210B中的每个纳米线通过非本征漏极区235A中的半导体材料物理耦合在一起。在示例性实施例中，第二半导体材料212B与纳米线210A和210B物理连接，并且然后第二半导体材料212C进一步设置于第二纳米线210B之上，以保持非本征漏极区235A内的多层结构，并且非本征漏极区235A内的半导体同样具有比沟道区245A内的半导体更高的物理高度(z维度)。对于包括多个纳米线210A、210B的实施例而言，漏极区内的高电压晶体管200具有多个漏极区，纳米线的垂直堆叠体内的每个纳米线具有一个漏极区。在示例性实施例中，漏极区中的每一个包括第一半导体，并且漏极接触部232A同轴地完全环绕漏极区中的每一个，以填充纳米线210A、210B之间的间隙。源极接触部232A以基本上相同的方式同轴地完全环绕源极区。
在替换的实施例中，组成沟道区245A内的纳米线210A的第一半导体材料可以完全不出现在非本征漏极区235A中。对于这种实施例而言，并非将第二半导体材料212A、212B与纳米线210A熔合，而是在非本征漏极区235A内选择性地重新生长纳米线210A作为第三半导体材料，其在一个实施例中与第二半导体材料212A相同，并且在另一个实施例中，是完全不同的半导体材料。像这样，高带隙半导体或诸如Al、Ga、和Zn之类的扩散元素可以包含在非本征漏极区235A中，以增加该区中出现的Ⅲ族半导体材料(例如，GaAs、InN、InAs，等等)的带隙。在重新生长的材料与第二半导体材料不同的情况下，仍然可以形成多层结构(例如，在重新生长的材料所具有的带隙仍然小于第二半导体材料212A、212B的带隙的情况下)。相同晶体的第二半导体材料212A、212B可以用作晶种层，以确保重新生长的半导体材料具有足够的晶体质量。
图2B是根据实施例的非平面高电压晶体管201的等距图。对于高电压晶体管201而言，半导体纳米线相对于衬底层205是垂直取向的，从而纵向长度L沿着z维度(与衬底层205正交)并且宽度W限定了衬底层205被纳米线占用的面积。至于横向取向的晶体管200，高电压晶体管201包括沿着纵向长度L的多种不同的半导体材料层，并且沟道区245B中的第一半导体材料层211C提供高于非本征漏极区235B中的第二半导体材料层211B(其具有大于第一半导体材料层211C的带隙)的载流子迁移率。在示例性实施例中，第一和第二半导体材料层211C、211B是外延堆叠体的一部分。
对于晶体管201而言，外延技术限定了器件的各种部分。至少包括非本征漏极区235B和沟道区245B的外延堆叠体还可以包括针对漏极区230B、非本征漏极区235B、沟道区245B、和源极区220B中的每一个区具有不同成分的外延半导体层。间隔体电介质形成围绕纳米线的外延区的电绝缘带，用于在制造期间防止短路。例如，间隔体电介质256围绕源极区220B，所以重新生长的半导体211E和/或设置于其上的欧姆金属化层与沟道区245B间隔开。
利用足够小的纵向长度L，取决于由外延堆叠体中的各种材料的任何晶格失配所施加的限制，纳米线可以是沿着整个纵向长度L的单晶，或至少直到沟道区245B是单晶的。还应该注意的是，尽管所述说明性实施例在衬底层205上具有有着“在下部”的漏极区230B的纳米线，但是其它实施例可以关于沟道区245A反转纳米线，成为“源极在下部”。以这种形式，晶体管201具有由外延层厚度限定的临界尺寸，例如沟道长度和Lgd(即，纵向长度L的一部分)，所述外延层厚度可以由生长工艺极好地控制(例如，控制为)。此外，利用外延层生长限定纳米线的长度，可以容易地定制材料成分，以实现带隙和迁移率差别化。电流驱动也可以通过限定纳米线的截面的平版印刷图案化来持续地缩放。
通常，第一和第二半导体材料层211C、211B可以是所描述的分别用于晶体管200的沟道区245A和非本征漏极区235A的那些材料层中的任何材料层。在特定实施例中，非本征漏极区235B由第二半导体材料层211B(例如，SiC、SiGe、InAlAs、AlGaAs、GaN，等等)构成，而沟道区245B由第一半导体材料层211C(例如，Si、Ge、InN、GaAs、InAs)构成。对于晶体管201而言，考虑到合理匹配的晶格参数可用的宽带隙范围和迁移率，Ⅲ族氮化物是尤其有利的，所述合理匹配的晶格参数允许非本征漏极区的厚度达到100nm或更大，如给定的BV所需要的。尽管在特定实施例中，非本征漏极区235B可以包括包含第一和第二半导体材料211C、211B二者的无序的多层结构(例如，正如晶体管200的示例性实施例中所使用的)，但是利用晶体管201中所使用的垂直纳米线取向，则沿着纵向长度L的不同部分选择性地生长具有所期望的带隙的材料相对容易。就晶体管200而言，漏极区230B和源极区220B可以是与沟道区245B相同的半导体材料，或可以是不同的外延材料。同样如晶体管200所描述的，源极接触部222B可以包括设置于源极区220上的半导体210E，例如p+隧道层和/或高掺杂的(例如，n+)低带隙覆盖层。还可以在源极接触部222B中包括低电阻率欧姆接触金属。
正如晶体管200一样，晶体管201包括同轴地完全环绕沟道区245B内的纳米线的栅极堆叠体250B。类似地，源极和漏极接触部222B和232B也分别同轴环绕源极和漏极区220B、230B。在栅极堆叠体250B与漏极区230B之间，第一电介质间隔体(未示出)设置于漏极接触部232B上，并且沿着第一纵向长度同轴地完全环绕非本征漏极区235B。第二电介质间隔体设置于栅极堆叠体250B上，并且沿着第二纵向长度同轴地完全环绕源极区220B，并且源极接触部232B设置于第二电介质间隔体上。
现在提供用于晶体管200和201中的每个晶体管的制造工艺的重要部分的简要说明。图3是示出根据实施例的制造非平面高电压晶体管200和201的方法300的流程图。尽管方法300强调了重要的操作，但是应该领会的是，图3中强调的每个操作可能需要更多的工艺步骤，并且图3中的操作的序号和操作的相对位置并不暗示顺序。图4A、4B、4C、4D和4E是根据方法300的实施例制造的非平面高电压晶体管200的等距图。图5A、5B、5C、5D、5E、5F和5G是根据方法300的实施例制造的非平面高电压晶体管201的等距图。
方法300在操作301处开始，利用任何标准化学气相沉积(CVD)、分子束外延(MBE)、氢化物气相外延(HVPE)、或类似的生长技术(具有标准的前驱体、温度等等)在衬底层205上外延生长单晶半导体材料的堆叠体。至少生长第一半导体材料和具有比第一半导体材料的带隙更大的带隙的第二半导体材料作为外延堆叠体的一部分。
在操作303处，通过利用本领域中公知的用于作为外延堆叠体的一部分而生长的特定材料的任何公知的等离子体或湿法化学蚀刻技术对外延堆叠体进行蚀刻来限定纳米线(例如，至少宽度)。在操作305处，形成环绕诸如第一半导体材料之类的窄带隙半导体的漏极接触部。在操作310处，源极接触部沿着纳米线的纵向源极长度同轴地完全环绕诸如第一半导体材料之类的窄带隙半导体。在操作315处，栅极导体沿着纳米线的纵向沟道长度同轴地完全环绕第一半导体，并且通过包括第二半导体材料的非本征漏极区与漏极接触部间隔开。然后，在操作320处，例如利用常规的互连技术完成器件。
如图4A中所示，在操作303的一个实施例中，将鳍式结构410蚀刻成第一半导体层210A、210B与第二半导体层212A、212B、212C交替的外延堆叠体。如图所示，第一半导体层210A、210B中的每层既设置于第二半导体层212A、212B上方，又设置于第二半导体层212A、212B下方。层的厚度T1-T5取决于所期望的纳米线尺寸，并且还取决于利用栅极堆叠体回填厚度T1、T3的能力。在非本征漏极区235A包括重新生长的纳米线材料的情况下，回填厚度T2、T4的能力也可能是相关的。图4A中还示出，通过例如浅沟槽隔离技术在衬底层205之上的鳍式结构410的任一侧上形成绝缘层407。
如图4B中所示，操作305、310和315的实施例需要形成设置于鳍式结构410上的牺牲栅极412。在一个所述实施例中，牺牲栅极412由牺牲栅极氧化层和牺牲多晶硅栅极层构成，牺牲栅极氧化层和牺牲多晶硅栅极层是均厚沉积的，并且利用常规的平板印刷和等离子体蚀刻工艺进行构图。可以在牺牲栅极412的侧壁上形成间隔体，并且可以形成层间电介质层来覆盖牺牲栅极412。可以对层间电介质层进行抛光来为替换栅极或后栅极工艺暴露牺牲栅极412。参考图4C，已经去除了牺牲栅极412，留下了间隔体255和层间电介质层(ILD)420、421的部分。如图4C中进一步示出的，在沟道区中去除了初始由牺牲栅极412覆盖的第二半导体层212A、212B、和212C。然后保留了第一半导体材料的分立的纳米线210A和210B。
如图4D中所示，然后形成同轴环绕沟道区245A内的纳米线210A、210B的栅极堆叠体250A。图4D示出沉积栅极电介质和栅极电极材料之后的栅极堆叠体250A，沉积栅极电介质和栅极电极材料用于回填由选择性地蚀刻第二半导体材料形成的间隙。也就是，栅极堆叠体250A形成于层间电介质层420、421之间的沟槽中。另外，图4D描述了在栅极堆叠体250A形成之后，去除层间电介质层420后的结果。层间电介质层421的一部分保留(例如，利用层间电介质的平版印刷限定的掩模蚀刻)在非本征漏极区235A内。
然后相对于第一半导体材料选择性地去除第二半导体层212A和212B的没有被栅极堆叠体250A以及层间电介质层421保护的部分，以形成第一半导体与衬底层205之间的间隙。然后第一半导体的分立部分保留在源极区220和漏极区230中，如图4D中所描述的那样。然后可以通过回填源极区220和漏极区230内形成的间隙来形成源极接触部222A和漏极接触部232A(如图2A中所示)。在一个所述实施例中，通过CVD、原子层沉积(ALD)、或金属回流来对接触金属进行共形沉积。
在图4E所示出的一个实施例中，其中非本征漏极区235A内的第一和第二半导体的熔合是不期望的，相对于间隔体255A、栅极堆叠体250A、以及源极、漏极接触部222A、232A选择性地去除ILD 421的剩余部分。然后可以相对于第二半导体材料层212A、212B、212C选择性地去除第一半导体材料210A、210B，以形成第二半导体材料之上(和之下)的间隙。然后可以在间隙中重新外延生长具有至少大于第一半导体材料210A、210B(并且也许还大于第二半导体)的带隙的晶体半导体材料。替代地，或此外，在去除了ILD 421的剩余部分之后，诸如Al、Ga、或Zn之类的扩散元素可以沉积在非本征漏极区235A内的第一半导体210A、210B上，或包含在其中。
在实施例中，执行了热退火以熔合非本征漏极区235A内出现的材料。例如，可以利用足够持续时间和温度的热退火来混合第一半导体材料210A、210B和第二半导体材料212A、212B和212C。替代地，热退火可以混合具有添加的扩散元素(例如，Al、Ga、或Zn)的第一和/或第二半导体材料。在一个这种实施例中，热退火与源极和漏极接触部的生长(例如，操作305和310)同时进行。
如图5A中所示，操作301的另一个实施例需要在衬底层205上外延生长为纵向长度L的每个功能部分定制的半导体材料层，而不是图4A的交替层结构。在示例性实施例中，将具有高杂质水平(例如n型掺杂剂)的第一半导体材料的第一层211A生长到厚度T1。在第一层211A上，将具有低杂质水平(例如，n型掺杂剂)的第二半导体材料的第二层211B外延生长到厚度T2，选择该厚度来提供期望的高电压能力(例如，针对10V的BV的Lgd)。接下来，在第二层上将第三层211C外延生长到厚度T3。在示例性实施例中，第三层211C由第一半导体材料构成，但是为了最高的载流子迁移率而没有掺杂。选择厚度T3来提供期望的沟道长度(Lg)。在第三层211C上，将第四层211D外延生长到厚度T4。在实施例中，第四层211D是具有高杂质水平(例如，n型掺杂剂)的第一半导体。还可以提供轻掺杂中间层，用于非本征源极区(未示出)。在示例性实施例中，将第五层211E外延生长到厚度T5。第五层211E可以是梯度层(graded layer)，以减小接触电阻，或者在示例性实施例中，第五层211E可以是形成隧道结的第一半导体的p+杂质掺杂层。
如图5A中所进一步示出的，操作303需要将宽度W1和W2的垂直纳米线560蚀刻成外延堆叠体。宽度W1和W2与图2B明显不同，仅为了示出纳米线尺寸可以如何取决于实施方式而大幅地变化。如图所示，利用同一个掩模来蚀刻层211E、211D、211C、和211B，并且覆盖较大的第二掩模并蚀刻第一层211A，以包括接触焊盘。同样如图5B所示，在衬底层205上并围绕纳米线560形成隔离层520。如图5C中所示出的，围绕第一层211A形成漏极接触部232B。例如，可以在纳米线560之上沉积金属，并且各向异性地对金属进行蚀刻(例如，金属间隔体蚀刻)，以使金属在纳米线侧壁上凹进一定高度，该高度大致等于或略小于厚度T1。
如图5D中所示，操作305需要将电介质材料沉积在纳米线560上，并沉积在漏极接触部232B上。然后各向异性地对电介质材料进行蚀刻，以形成环绕纳米线560的第一电介质间隔体540。第一电介质间隔体540设置于漏极接触部232B上，并且具有大致等于第二外延层211B的厚度的高度。
如图5E中所示，操作315的实施例需要将栅极绝缘体沉积在纳米线560之上，并沉积在第一电介质间隔体540上。将栅极导体进一步沉积在栅极绝缘体上，并且至少各向异性地蚀刻栅极导体，以形成环绕纳米线560的栅极导体间隔体，其用作栅极堆叠体250B。栅极导体利用各向异性的蚀刻来向下凹进纵向长度L，以具有大致等于T3的高度。掩蔽的部分(未示出)可以用于在与纳米线560的纵向长度L正交的平面中提供栅极接触部。然后对没有被栅极导体间隔体保护的栅极绝缘体进行蚀刻，以暴露第四半导体层211D。
如图5F中所示，操作310的实施例需要将电介质材料沉积在纳米线560上，并沉积在栅极堆叠体250B上(即，在栅极导体间隔体上)。各向异性地蚀刻电介质材料以形成环绕纳米线560并沉积在栅极堆叠体上的第二电介质材料间隔体550。蚀刻第二电介质材料间隔体550使其凹进小于T4的高度。如图5G所示出的，然后在纳米线560上并在第二电介质材料间隔体550上形成源极接触部222B。然后，如图5H中所示，操作320以漏极和源极过孔555、556的形成开始。
图6是根据本发明的实施例的移动计算平台的SOC实施方式的功能性框图。移动计算平台700可以是被配置用于电子数据显示、电子数据处理、和无线电子数据传输中的每一个功能的任何便携设备。例如，移动计算平台700可以是平板电脑、智能手机、膝上型计算机等中的任何一个，并且包括显示屏705、SOC 710、以及电池713，其中显示屏705在示例性实施例中是允许接收用户输入的触摸屏(例如，电容性、电感性、电阻性，等等)。如所示出的，SOC 710的集成的水平越高，则移动计算平台700内的形状因子就可以越多地被电池713占用，以用于在充电之间最长的运行寿命，或越多地被诸如固态硬盘之类的存储器(未示出)占用，以实现最大的功能性。
根据其应用，移动计算平台700可以包括其它部件，包括但不限于易失性存储器(例如，DRAM)、非易失性存储器(例如，ROM)、闪速存储器、图形处理器、数字信号处理器、密码处理器、芯片集、天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编解码器、视频编解码器、功率放大器、全球定位系统(GPS)设备、罗盘、加速度计、陀螺仪、扬声器、照相机、以及大容量存储设备(例如硬盘驱动器、光盘(CD)、数字多功能盘(DVD)，等等)。
在扩展视图720中进一步示出了SOC 710。根据实施例，SoC 710包括衬底500(即，芯片)的一部分，其上制造以下部件中的两个或更多个：功率管理集成电路(PMIC)715、包括RF发送器和/或接收器的RF集成电路(RFIC)725、其控制器711，以及一个或多个中央处理器核720、730。RFIC 725可以实现多种无线标准或协议中的任何一种，所述多种无线标准或协议包括但不限于Wi-Fi(IEEE 802.11系列)、WiMAX(IEEE 802.16系列)、IEEE 802.20、长期演进(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、蓝牙、它们的衍生物、以及任何其它指定为3G、4G、5G及更高代的无线协议。平台725可以包括多个通信芯片。例如，第一个通信芯片可以专用于较短范围无线通信，例如Wi-Fi和蓝牙；并且第二个通信芯片可以专用于较长范围的无线通信，例如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO、等等。
如本领域技术人员将领会的，在这些功能不同的电路模块中，除了在PMIC 715和RFIC 725中，通常采用专用的CMOS晶体管，该PMIC 715和RFIC 725通常分别使用LDMOS和Ⅲ-ⅤHBT或HEMT技术。然而在本发明的实施例中，PMIC 715和RFIC 725采用本文描述的高电压晶体管(例如，高电压晶体管200)。在其它实施例中，采用本文描述的高电压晶体管的PMIC 715和RFIC 725与控制器711和处理器核720、730中的一个或多个集成，控制器711和处理器核720、730中的所述一个或多个在硅CMOS工艺中与PMIC 715和/或RFIC 725单片地集成到硅衬底500上。应该领会的是，在PMIC 715和/或RFIC 725内，本文描述的具有高电压、高频能力的晶体管不需要被用于将CMOS排除在外，而是相反还可以将硅CMOS包括在PMIC 715和RFIC 725中的每一个中。例如，在高电压晶体管200采用硅沟道区和SiC非本征漏极区的情况下，可以制造基本上如图4A-4E中所示的非平面CMOS晶体管，除了所有ILD421都被去除，而不是被保护(被掩蔽)。
本文描述的高电压晶体管可以特别用于出现高电压摆动的情况(例如，在PMIC715内的电池功率调节、DC到DC转换，等等)。为了说明，智能手机中的电池电压范围通常在3-5V。然而，本文中所描述的晶体管能够维持所述电压范围的2-3倍的电压(即，至少7-10V)，以在足够的余量下工作，从而确保可靠工作。如所示出的，在示例性实施例中，PMIC715具有耦合到电池713的输入端，并且具有向SOC 710中的所有其它功能模块提供电流供应的输出端。在其它实施例中，在附加的IC设置在移动计算平台700内但在SOC 710外部的情况下，PMIC 715的输出端还向SOC 710外部的所有这些附加的IC提供电流供应。如进一步示出的，在示例性实施例中，RFIC 725具有耦合到天线的输出端，并且还可以具有耦合到诸如RF模拟和数字基带模块(未示出)的SOC 710上的通信模块的输入端。替代地，可以在SOC710的片外IC上提供这种通信模块，并且将其耦合到SOC 710中用于传输。根据所使用的第一半导体材料，本文中所描述的高电压晶体管(例如，200或201)还可以提供功率放大晶体管所需要的大功率附加效率(PAE)，所述功率放大晶体管具有至少十倍的载频(例如，在为3G或GSM蜂窝通信而设计的RFIC 725中是1.9GHz)、或>20GHz的Ft(0dB电流增益下的截止频率)。利用本文中所描述的晶体管所实现的低Ron，超过20GHz的Fmax还可以与超过20GHz的Ft和至少7-10V的BV同时实现。
应该理解的是，上述描述是示例性而非限制性的。例如，尽管附图中的流程图示出了由本发明的特定实施例所执行的操作的特定顺序，但是应该理解的是，可以不需要这种顺序(例如，可选的实施例可以采用不同的顺序来执行操作、组合特定操作、重叠特定操作，等等)。此外，对于本领域技术人员来说，一经阅读并理解了上述描述后，许多其它实施例将是显而易见的。尽管已经参考特定的示例性实施例描述了本发明，但是应该认识到，本发明并不限于所描述的实施例，而是可以通过在所附权利要求的精神和范围内做出修改和变更来实现。因此，应该参考所附权利要求、以及这些权利要求所被赋予权利的等价物的完整范围来确定本发明的范围。

Claims (16)

1.一种垂直晶体管，包括：
圆柱形漏极区，所述圆柱形漏极区位于衬底的最高表面之上，所述圆柱形漏极区具有中心，所述中心具有与所述衬底的所述最高表面正交的轴；
圆柱形非本征漏极区，所述圆柱形非本征漏极区位于所述圆柱形漏极区之上，所述圆柱形非本征漏极区具有与所述轴同轴的中心；
圆柱形沟道区，所述圆柱形沟道区位于所述圆柱形非本征漏极区之上，所述圆柱形沟道区具有与所述轴同轴的中心；
圆柱形源极区，所述圆柱形源极区位于所述圆柱形沟道区之上，所述圆柱形源极区具有与所述轴同轴的中心；
包括栅极绝缘体和栅极导体的栅极堆叠体，所述栅极堆叠体被同轴地完全环绕所述圆柱形沟道区；
漏极接触部，所述漏极接触部被同轴地完全环绕所述圆柱形漏极区；以及
源极接触部，所述源极接触部被同轴地完全环绕所述圆柱形源极区的至少一部分。
2.根据权利要求1所述的晶体管，其中所述圆柱形非本征漏极区的带隙比所述圆柱形沟道区的带隙大。
3.根据权利要求1所述的晶体管，其中所述源极接触部与所述圆柱形沟道区间隔第一长度，并且其中所述漏极接触部与所述圆柱形沟道区间隔第二长度，所述第二长度大于所述第一长度。
4.根据权利要求1所述的晶体管，其中所述圆柱形漏极区、所述圆柱形沟道区和所述圆柱形源极区包括第一半导体材料，并且所述圆柱形非本征漏极区包括第二半导体材料，所述第二半导体材料不同于所述第一半导体材料。
5.根据权利要求4所述的晶体管，其中所述第一半导体材料是InN，并且所述第二半导体材料是GaN。
6.根据权利要求4所述的晶体管，其中所述第一半导体材料是GaAs，并且所述第二半导体材料是AlGaAs。
7.根据权利要求4所述的晶体管，其中所述第一半导体材料是InAs，并且所述第二半导体材料是InAlAs。
8.根据权利要求4所述的晶体管，其中所述第一半导体材料是Ge，并且所述第二半导体材料是Si。
9.一种制造垂直晶体管的方法，所述方法包括：
在衬底的最高表面之上外延地生长圆柱形漏极区，所述圆柱形漏极区具有中心，所述中心具有与所述衬底的所述最高表面正交的轴；
形成漏极接触部，所述漏极接触部被同轴地完全环绕所述圆柱形漏极区；
在所述圆柱形漏极区之上外延地生长圆柱形非本征漏极区，所述圆柱形非本征漏极区具有与所述轴同轴的中心；
在所述圆柱形非本征漏极区之上外延地生长圆柱形沟道区，所述圆柱形沟道区具有与所述轴同轴的中心；
形成包括栅极绝缘体和栅极导体的栅极堆叠体，所述栅极堆叠体被同轴地完全环绕所述圆柱形沟道区；
在所述圆柱形沟道区之上外延地生长圆柱形源极区，所述圆柱形源极区具有与所述轴同轴的中心；以及
形成源极接触部，所述源极接触部被同轴地完全环绕所述圆柱形源极区的至少一部分。
10.根据权利要求9所述的方法，其中所述圆柱形非本征漏极区的带隙比所述圆柱形沟道区的带隙大。
11.根据权利要求9所述的方法，其中所述源极接触部与所述圆柱形沟道区间隔第一长度，并且其中所述漏极接触部与所述圆柱形沟道区间隔第二长度，所述第二长度大于所述第一长度。
12.根据权利要求9所述的方法，其中所述圆柱形漏极区、所述圆柱形沟道区和所述圆柱形源极区包括第一半导体材料，并且所述圆柱形非本征漏极区包括第二半导体材料，所述第二半导体材料不同于所述第一半导体材料。
13.根据权利要求12所述的方法，其中所述第一半导体材料是InN，并且所述第二半导体材料是GaN。
14.根据权利要求12所述的方法，其中所述第一半导体材料是GaAs，并且所述第二半导体材料是AlGaAs。
15.根据权利要求12所述的方法，其中所述第一半导体材料是InAs，并且所述第二半导体材料是InAlAs。
16.根根据权利要求12所述的方法，其中所述第一半导体材料是Ge，并且所述第二半导体材料是Si。
CN201710000739.6A 2011-12-19 2011-12-19 高电压场效应晶体管 Active CN107039515B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710000739.6A CN107039515B (zh) 2011-12-19 2011-12-19 高电压场效应晶体管

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CN201180076395.8A CN104115273B (zh) 2011-12-19 2011-12-19 高电压场效应晶体管
CN201710000739.6A CN107039515B (zh) 2011-12-19 2011-12-19 高电压场效应晶体管
PCT/US2011/065916 WO2013095342A1 (en) 2011-12-19 2011-12-19 High voltage field effect transistors

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CN201180076395.8A Division CN104115273B (zh) 2011-12-19 2011-12-19 高电压场效应晶体管

Publications (2)

Publication Number Publication Date
CN107039515A true CN107039515A (zh) 2017-08-11
CN107039515B CN107039515B (zh) 2021-05-25

Family

ID=48669009

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201180076395.8A Active CN104115273B (zh) 2011-12-19 2011-12-19 高电压场效应晶体管
CN201710000739.6A Active CN107039515B (zh) 2011-12-19 2011-12-19 高电压场效应晶体管

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN201180076395.8A Active CN104115273B (zh) 2011-12-19 2011-12-19 高电压场效应晶体管

Country Status (5)

Country Link
US (3) US9245989B2 (zh)
KR (2) KR101779031B1 (zh)
CN (2) CN104115273B (zh)
TW (2) TWI595663B (zh)
WO (1) WO2013095342A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023098502A1 (en) * 2021-11-30 2023-06-08 International Business Machines Corporation Wrap-around-contact for 2d-channel gate-all-around field-effect-transistors

Families Citing this family (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013095343A1 (en) 2011-12-19 2013-06-27 Intel Corporation Group iii-n nanowire transistors
KR101779031B1 (ko) * 2011-12-19 2017-09-18 인텔 코포레이션 수직 트랜지스터와 그 제조방법, 및 고전압 트랜지스터
WO2013101004A1 (en) * 2011-12-28 2013-07-04 Intel Corporation Contact techniques and configurations for reducing parasitic resistance in nanowire transistors
US9209248B2 (en) 2013-08-07 2015-12-08 Infineon Technologies Dresden Gmbh Power transistor
US20150053929A1 (en) * 2013-08-22 2015-02-26 Board Of Regents. The University Of Texas System Vertical iii-v nanowire field-effect transistor using nanosphere lithography
KR20150028189A (ko) * 2013-09-05 2015-03-13 르네사스 일렉트로닉스 가부시키가이샤 반도체 장치 및 그 제조 방법
US9224811B2 (en) * 2014-03-17 2015-12-29 Globalfoundries Inc Stacked semiconductor device
EP3155658B1 (en) * 2014-06-16 2023-02-22 Intel Corporation Memory die with direct integration to logic die and method of manufacturing the same
US9431512B2 (en) * 2014-06-18 2016-08-30 Globalfoundries Inc. Methods of forming nanowire devices with spacers and the resulting devices
US9490340B2 (en) 2014-06-18 2016-11-08 Globalfoundries Inc. Methods of forming nanowire devices with doped extension regions and the resulting devices
CN106463534B (zh) * 2014-06-23 2020-12-11 英特尔公司 用于形成垂直晶体管架构的技术
US9219154B1 (en) * 2014-07-15 2015-12-22 International Business Machines Corporation Method of fabricating electrostatically enhanced fins and stacked nanowire field effect transistors
KR101566313B1 (ko) * 2014-09-05 2015-11-05 한국과학기술원 반도체 장치의 제조방법
KR102248478B1 (ko) 2014-09-18 2021-05-06 인텔 코포레이션 실리콘 cmos-호환가능 반도체 디바이스들에서의 결함 전파 제어를 위한 경사 측벽 패싯들을 가지는 우르자이트 이종에피택셜 구조체들
EP3198649A4 (en) 2014-09-25 2018-05-16 Intel Corporation Iii-n epitaxial device structures on free standing silicon mesas
US9425324B2 (en) * 2014-09-30 2016-08-23 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device and channel structure thereof
KR102238547B1 (ko) * 2014-10-30 2021-04-09 인텔 코포레이션 질화 갈륨 트랜지스터에서 2d 전자 가스에 대한 낮은 접촉 저항을 위한 소스/드레인 재성장
US9508858B2 (en) 2014-11-18 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Contacts for highly scaled transistors
WO2016080961A1 (en) 2014-11-18 2016-05-26 Intel Corporation Cmos circuits using n-channel and p-channel gallium nitride transistors
US9953979B2 (en) 2014-11-24 2018-04-24 Qualcomm Incorporated Contact wrap around structure
KR102423219B1 (ko) 2014-12-18 2022-07-20 인텔 코포레이션 N-채널 갈륨 질화물 트랜지스터들
KR20160116868A (ko) 2015-03-31 2016-10-10 한국전기연구원 섬유 일체형 탑 게이트 구조의 박막 트랜지스터 및 그 제조방법
US10211327B2 (en) 2015-05-19 2019-02-19 Intel Corporation Semiconductor devices with raised doped crystalline structures
US10388777B2 (en) 2015-06-26 2019-08-20 Intel Corporation Heteroepitaxial structures with high temperature stable substrate interface material
US9818872B2 (en) * 2015-06-30 2017-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device and method of fabrication thereof
US9627330B2 (en) * 2015-07-13 2017-04-18 International Business Machines Corporation Support for long channel length nanowire transistors
US9754840B2 (en) * 2015-11-16 2017-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Horizontal gate-all-around device having wrapped-around source and drain
WO2017111869A1 (en) 2015-12-24 2017-06-29 Intel Corporation Transition metal dichalcogenides (tmdcs) over iii-nitride heteroepitaxial layers
WO2017111829A1 (en) * 2015-12-26 2017-06-29 Intel Corporation Thin film switching device
KR102461174B1 (ko) 2016-02-26 2022-11-01 삼성전자주식회사 반도체 소자
KR102413782B1 (ko) * 2016-03-02 2022-06-28 삼성전자주식회사 반도체 장치
US10622448B2 (en) * 2016-03-30 2020-04-14 Intel Corproation Transistors including retracted raised source/drain to reduce parasitic capacitances
US9929144B2 (en) 2016-04-15 2018-03-27 International Business Machines Corporation Laterally diffused metal oxide semiconductor device integrated with vertical field effect transistor
US10074727B2 (en) 2016-09-29 2018-09-11 International Business Machines Corporation Low resistivity wrap-around contacts
KR101984725B1 (ko) 2016-10-21 2019-05-31 주식회사 엘지화학 아스팔트 개질제 및 이를 포함하는 아스팔트 조성물
KR102651871B1 (ko) 2016-11-29 2024-04-01 삼성전자주식회사 반도체 소자 및 그의 제조 방법
KR20180066746A (ko) 2016-12-09 2018-06-19 삼성전자주식회사 반도체 소자 및 그 제조 방법
CN108807386B (zh) * 2017-04-28 2023-04-07 三星电子株式会社 半导体器件
US10276728B2 (en) 2017-07-07 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including non-volatile memory cells
KR102314006B1 (ko) 2017-09-11 2021-10-18 삼성전자주식회사 수직 전계 트랜지스터 및 이를 포함하는 반도체 장치
WO2019066953A1 (en) 2017-09-29 2019-04-04 Intel Corporation REDUCED CONTACT RESISTANCE GROUP III (N-N) NITRIDE DEVICES AND METHODS OF MAKING SAME
KR101999902B1 (ko) * 2017-11-15 2019-10-01 도실리콘 씨오., 엘티디. 페이싱바를 가지는 낸드 플래쉬 메모리 장치 및 그의 제조 방법
US10833078B2 (en) * 2017-12-04 2020-11-10 Tokyo Electron Limited Semiconductor apparatus having stacked gates and method of manufacture thereof
US10438999B2 (en) * 2017-12-29 2019-10-08 Spin Memory, Inc. Annular vertical Si etched channel MOS devices
US10475889B1 (en) * 2018-06-05 2019-11-12 Qualcomm Incorporated Gallium nitride power amplifier integration with metal-oxide-semiconductor devices
US11049873B2 (en) * 2018-09-24 2021-06-29 Sunrise Memory Corporation Epitaxial monocrystalline channel for storage transistors in 3-dimensional memory structures and methods for formation thereof
US10665698B2 (en) * 2018-10-19 2020-05-26 International Business Machines Corporation Reducing gate-induced-drain-leakage current in a transistor by forming an enhanced band gap layer at the channel-to-drain interface
EP3653568B1 (en) 2018-11-14 2022-10-19 IMEC vzw A method for forming a semiconductor device comprising nanowire field-effect transistors
US10937479B1 (en) * 2019-08-29 2021-03-02 Spin Memory, Inc. Integration of epitaxially grown channel selector with MRAM device
US10957370B1 (en) * 2019-08-29 2021-03-23 Spin Memory, Inc. Integration of epitaxially grown channel selector with two terminal resistive switching memory element
US11094791B1 (en) * 2020-01-30 2021-08-17 Globalfoundries U.S. Inc. Vertical transistor device with source/drain regions comprising a twi-dimensional (2D) material and methods of making such vertical transistor devices
US11177182B2 (en) 2020-01-30 2021-11-16 Globalfoundries U.S. Inc. Vertical transistor device comprising a two-dimensional (2D) material positioned in a channel region of the device and methods of making such vertical transistor devices
US11450686B2 (en) * 2020-06-29 2022-09-20 Taiwan Semiconductor Manufacturing Co., Ltd. High density 3D FERAM
WO2022151044A1 (zh) * 2021-01-13 2022-07-21 华为技术有限公司 一种存储器、环栅场效应晶体管以及制备方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101273459A (zh) * 2005-06-16 2008-09-24 昆南诺股份有限公司 半导体纳米线晶体管
US20090035908A1 (en) * 2006-02-07 2009-02-05 Ecole Polytechnique Process for fabricating a nanowire-based vertical transistor structure

Family Cites Families (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10036897C1 (de) * 2000-07-28 2002-01-03 Infineon Technologies Ag Feldeffekttransistor, Schaltungsanordnung und Verfahren zum Herstellen eines Feldeffekttransistors
KR100444270B1 (ko) * 2002-07-06 2004-08-12 재단법인서울대학교산학협력재단 음 미분 전도도를 갖는 반도체 소자의 제조 방법
US7335908B2 (en) * 2002-07-08 2008-02-26 Qunano Ab Nanostructures and methods for manufacturing the same
US7135728B2 (en) * 2002-09-30 2006-11-14 Nanosys, Inc. Large-area nanoenabled macroelectronic substrates and uses therefor
US6998320B2 (en) * 2003-04-23 2006-02-14 Triquint Semiconductor, Inc. Passivation layer for group III-V semiconductor devices
US6921700B2 (en) * 2003-07-31 2005-07-26 Freescale Semiconductor, Inc. Method of forming a transistor having multiple channels
FR2861501B1 (fr) * 2003-10-22 2006-01-13 Commissariat Energie Atomique Dispositif microelectronique a effet de champ apte a former un ou plusiseurs canaux de transistors
US7361958B2 (en) * 2004-09-30 2008-04-22 Intel Corporation Nonplanar transistors with metal gate electrodes
JP2006140325A (ja) * 2004-11-12 2006-06-01 Toshiba Corp 半導体装置
US20060202266A1 (en) * 2005-03-14 2006-09-14 Marko Radosavljevic Field effect transistor with metal source/drain regions
WO2007022359A2 (en) * 2005-08-16 2007-02-22 The Regents Of The University Of California Vertical integrated silicon nanowire field effect transistors and methods of fabrication
WO2007086009A1 (en) * 2006-01-25 2007-08-02 Nxp B.V. Nanowire tunneling transistor
TWI291218B (en) * 2006-03-10 2007-12-11 Promos Technologies Inc Vertical-type surrounding gate semiconductor device
US7456068B2 (en) * 2006-06-08 2008-11-25 Intel Corporation Forming ultra-shallow junctions
US7718995B2 (en) * 2006-06-20 2010-05-18 Panasonic Corporation Nanowire, method for fabricating the same, and device having nanowires
WO2007148653A1 (ja) * 2006-06-21 2007-12-27 Panasonic Corporation 電界効果トランジスタ
US7945208B2 (en) * 2006-08-14 2011-05-17 Gct Semiconductor, Inc. Radio frequency integrated circuit
KR20090075819A (ko) * 2006-09-19 2009-07-09 큐나노 에이비 나노스케일 전계 효과 트랜지스터의 조립체
US20120119168A9 (en) * 2006-11-21 2012-05-17 Robert Fleming Voltage switchable dielectric materials with low band gap polymer binder or composite
US8120115B2 (en) * 2007-03-12 2012-02-21 Imec Tunnel field-effect transistor with gated tunnel barrier
KR101377597B1 (ko) * 2007-03-21 2014-03-27 삼성디스플레이 주식회사 트랜지스터 및 그 제조방법
JP5498161B2 (ja) * 2007-06-06 2014-05-21 パナソニック株式会社 半導体ナノワイヤの製造方法
US20090032799A1 (en) * 2007-06-12 2009-02-05 Siphoton, Inc Light emitting device
JP2009032869A (ja) * 2007-07-26 2009-02-12 Sumitomo Chemical Co Ltd ヘテロ接合バイポーラトランジスタ
US7948720B2 (en) * 2008-03-19 2011-05-24 Qualcomm Incorporated Voltage regulator with transient recovery circuit
EP2148374A1 (en) 2008-07-23 2010-01-27 University College Cork-National University of Ireland, Cork A tunnel nanowire transistor
KR101471858B1 (ko) * 2008-09-05 2014-12-12 삼성전자주식회사 바 타입의 액티브 패턴을 구비하는 반도체 장치 및 그 제조방법
US8043965B2 (en) * 2009-02-11 2011-10-25 Northrop Grumann Systems Corporation Method of forming a through substrate via in a compound semiconductor
KR101538742B1 (ko) * 2009-02-25 2015-07-30 삼성전자주식회사 나노와이어의 합성 방법
US8013324B2 (en) * 2009-04-03 2011-09-06 International Business Machines Corporation Structurally stabilized semiconductor nanowire
US8237150B2 (en) * 2009-04-03 2012-08-07 International Business Machines Corporation Nanowire devices for enhancing mobility through stress engineering
US8084308B2 (en) * 2009-05-21 2011-12-27 International Business Machines Corporation Single gate inverter nanowire mesh
EP2267782A3 (en) 2009-06-24 2013-03-13 Imec Control of tunneling junction in a hetero tunnel field effect transistor
DE112011105926T5 (de) * 2011-12-09 2014-09-18 Intel Corporation Belastungskompensation in Transistoren
WO2013095346A1 (en) * 2011-12-19 2013-06-27 Intel Corporation Non-planar iii-n transistor
KR101779031B1 (ko) * 2011-12-19 2017-09-18 인텔 코포레이션 수직 트랜지스터와 그 제조방법, 및 고전압 트랜지스터
WO2013095343A1 (en) * 2011-12-19 2013-06-27 Intel Corporation Group iii-n nanowire transistors
CN103999216B (zh) * 2011-12-19 2017-06-13 英特尔公司 用于集成有功率管理和射频电路的片上系统(soc)结构的iii族‑n晶体管
US8896066B2 (en) * 2011-12-20 2014-11-25 Intel Corporation Tin doped III-V material contacts
US8823059B2 (en) * 2012-09-27 2014-09-02 Intel Corporation Non-planar semiconductor device having group III-V material active region with multi-dielectric gate stack
US8890120B2 (en) * 2012-11-16 2014-11-18 Intel Corporation Tunneling field effect transistors (TFETs) for CMOS approaches to fabricating N-type and P-type TFETs
US8890119B2 (en) * 2012-12-18 2014-11-18 Intel Corporation Vertical nanowire transistor with axially engineered semiconductor and gate metallization
US9054215B2 (en) * 2012-12-18 2015-06-09 Intel Corporation Patterning of vertical nanowire transistor channel and gate with directed self assembly
US8896101B2 (en) * 2012-12-21 2014-11-25 Intel Corporation Nonplanar III-N transistors with compositionally graded semiconductor channels
US9484460B2 (en) * 2013-09-19 2016-11-01 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device having gate dielectric surrounding at least some of channel region and gate electrode surrounding at least some of gate dielectric
US9799776B2 (en) * 2015-06-15 2017-10-24 Stmicroelectronics, Inc. Semi-floating gate FET

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101273459A (zh) * 2005-06-16 2008-09-24 昆南诺股份有限公司 半导体纳米线晶体管
US20090035908A1 (en) * 2006-02-07 2009-02-05 Ecole Polytechnique Process for fabricating a nanowire-based vertical transistor structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023098502A1 (en) * 2021-11-30 2023-06-08 International Business Machines Corporation Wrap-around-contact for 2d-channel gate-all-around field-effect-transistors
US11935930B2 (en) 2021-11-30 2024-03-19 International Business Machines Corporation Wrap-around-contact for 2D-channel gate-all-around field-effect-transistors

Also Published As

Publication number Publication date
US10263074B2 (en) 2019-04-16
KR20160137691A (ko) 2016-11-30
US9245989B2 (en) 2016-01-26
US20170263708A1 (en) 2017-09-14
US20160079359A1 (en) 2016-03-17
US20130307513A1 (en) 2013-11-21
KR20140101820A (ko) 2014-08-20
KR101681396B1 (ko) 2016-11-30
TW201633547A (zh) 2016-09-16
TWI595663B (zh) 2017-08-11
WO2013095342A1 (en) 2013-06-27
CN104115273B (zh) 2017-10-13
KR101779031B1 (ko) 2017-09-18
TWI531065B (zh) 2016-04-21
US9685508B2 (en) 2017-06-20
TW201330271A (zh) 2013-07-16
CN107039515B (zh) 2021-05-25
CN104115273A (zh) 2014-10-22

Similar Documents

Publication Publication Date Title
CN104115273B (zh) 高电压场效应晶体管
US10541305B2 (en) Group III-N nanowire transistors
US9806203B2 (en) Nonplanar III-N transistors with compositionally graded semiconductor channels
CN103999216B (zh) 用于集成有功率管理和射频电路的片上系统(soc)结构的iii族‑n晶体管

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant