CN106971981A - 半导体封装、半导体装置及制造半导体封装的方法 - Google Patents

半导体封装、半导体装置及制造半导体封装的方法 Download PDF

Info

Publication number
CN106971981A
CN106971981A CN201611074783.3A CN201611074783A CN106971981A CN 106971981 A CN106971981 A CN 106971981A CN 201611074783 A CN201611074783 A CN 201611074783A CN 106971981 A CN106971981 A CN 106971981A
Authority
CN
China
Prior art keywords
film layer
electronic component
semiconductor packages
packaging body
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201611074783.3A
Other languages
English (en)
Other versions
CN106971981B (zh
Inventor
许文松
林世钦
熊明仁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MediaTek Inc
Original Assignee
MediaTek Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MediaTek Inc filed Critical MediaTek Inc
Publication of CN106971981A publication Critical patent/CN106971981A/zh
Application granted granted Critical
Publication of CN106971981B publication Critical patent/CN106971981B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48229—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73151—Location prior to the connecting process on different surfaces
    • H01L2224/73153—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1436—Dynamic random-access memory [DRAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明实施例提供了一种半导体封装、半导体装置及制造半导体封装的方法。其中该半导体封装包括：基底；第一电子元件，设置在该基底上；膜层，设置在该第一电子元件的上表面上；以及封装体，封装该第一电子元件与该膜层。本发明实施例，通过将膜层设置在第一电子元件的上表面与封装体之间，从而提高半导体封装的整体强度。

Description

半导体封装、半导体装置及制造半导体封装的方法
技术领域
本发明涉及半导体封装技术领域，尤其涉及一种半导体封装、半导体装置及半导体封装的制造方法。
背景技术
于电子产业中，具有高性能的高集成度与多功能性已成为新产品的基本。与此同时，由于制造成本与产品的尺寸成比例，因此高集成度会导至更高的制造成本。因此，要求集成电路(Integrated Circuit，IC)封装的小型化已变得越来越重要。由于PoP(Package-on-package，封装上封装)是解决单个封装中高密度系统集成的划算的方案，因此PoP是目前发展最快的半导体封装技术。但是，由于PoP结构具有薄的厚度，因此PoP结构容易由于加热或其他因素而破裂或损伤。
发明内容
有鉴于此，本发明提供了一种半导体封装、半导体装置及半导体封装的制造方法，可以增加半导体封装的强度。
本发明提供了一种半导体封装，包括：基底；第一电子元件，设置在该基底上，并且具有上表面；膜层，设置在该第一电子元件的该上表面上；以及封装体，封装该第一电子元件与该膜层。
其中，该膜层直接附着于该第一电子元件的该上表面上。
其中，该封装体覆盖该膜层的上表面。
其中，该膜层为通过涂布工艺形成于该第一电子元件的该上表面的薄膜。
其中，该封装体包括：用来覆盖该膜层的上表面的覆盖部分，该膜层的厚度小于该覆盖部分的厚度。
其中，进一步包括：多个导电元件，设置在该基底上并且围绕该第一电子元件；其中，该每个导电元件的一部分由该封装体封装，另一部分从该封装体中露出。
本发明提供了一种半导体装置，包括：如上所述的半导体封装；以及第二电子元件，堆叠在该半导体封装上。
本发明提供了一种半导体封装的制造方法，包括：提供具有上表面的晶圆；在该晶圆的该上表面上设置膜层；形成穿过该晶圆和该膜层的切割路径，以形成至少一个第一电子元件，其中该膜层设置于该第一电子元件上；提供基底；将该第一电子元件设置于该基底上；并且形成封装体，来封装该第一电子元件及该膜层。
其中，在该晶圆的该上表面上设置膜层之前，进一步包括：研磨该晶圆的该上表面。
其中，在该晶圆的该上表面上设置膜层之后，进一步包括：加热该膜层以固化该膜层。
本发明实施例的有益效果是：
本发明实施例在第一电子元件的上表面设置膜层，并由封装体封装该第一电子元件与该膜层，从而可以利用该膜层来增加该封装体与该第一电子元件之间的界面的强度，进而提高半导体封装的强度。
附图说明
在浏览了以下详细描述及附图之后，本发明的上述目的及优点将对本领域技术人员更显而易见，其中：
图1为根据本发明实施例的半导体封装的示意图；
图2为根据本发明另一实施例的半导体封装的示意图；
图3为根据本发明实施例的半导体装置的示意图；
图4A～4G示意了图1的半导体封装的制造过程。
具体实施方式
为了使本发明所解决的技术问题、技术方案及有益效果更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
在本申请说明书及权利要求当中使用了某些词汇来指称特定的元件。本领域技术人员应可理解，硬件制造商可能会用不同的名词来称呼同一个元件。本说明书及权利要求并不以名称的差异作为区分元件的方式，而是以元件在功能上的差异作为区分的准则。在通篇说明书及权利要求当中所提及的“包括”、“包含”为一开放式的用语，故应解释成“包括(含)但不限定于”。另外，“耦接”一词在此为包括任何直接及间接的电气连接手段。因此，若文中描述第一装置耦接于第二装置，则代表该第一装置可直接电气连接至该第二装置，或透过其它装置或连接手段间接地电气连接至该第二装置。
图1为根据本发明实施例的半导体封装100的结构示意图。该半导体封装100包括：基底110、至少一个第一电子元件120、至少一个第一导电接头(conductive contact)130、封装体140及膜层150。
该基底110例如为多层结构或者单层结构。该基底110可以为有机基底、陶瓷基底、硅基底或金属基底，等等。在另一实施例中，该基底110可以为插入层(interposer)或者晶圆，具有至少一个RDL(redistribution layer，重分布层)。
该第一电子元件120设置在该基底110上，并且具有上表面120u。在本实施例中，第一电子元件120以“正面向下”的方向来耦接至基底110的上表面110u，并且通过多个导电接头121电性连接至基底110。该配置有时也称为“倒装芯片”。导电接头121可以为焊料球、导电柱，等等。
在其他实施例中，该第一电子元件120可以采用“正面向上”的方向来耦接至基底110，并且通过多条接合线(未示出)电性连接至基底110。第一电子元件120可以为有源芯片或者无源元件，诸如电阻、电感或电容。在另一实施例中，第一电子元件120的数量可以为几个。
第一导电接头130设置在基底110的上表面110u上，并且围绕该第一电子元件120。第一导电接头130从封装体140中露出，并且用于电性连接外部的电子元件(未示出)。例如，每个第一导电接头130的一部分被封装体140封装住，并且每个第一导电接头130的另一部分从封装体140中露出，以用于电性连接外部的电子元件。另外，第一导电接头130可以为焊料球、导电柱，等等。
第二导电接头135设置在基底110的下表面110b上。该半导体封装100可以通过第二导电接头135设置在外部电路上并电性连接至该外部电路，诸如电路板。第二导电接头135可以为焊料球、导电柱，等等。
封装体140封装第一电子元件120、膜层150及每个第一导电接头130的一部分。在本实施例中，封装体140覆盖膜层150的上表面150u。在另一实施例中，封装体140可以露出膜层150的上表面150u并且覆盖膜层150的侧面。
封装体140包括：用于覆盖膜层150的上表面150u的覆盖部分141。膜层150具有第一厚度T1，大约等于或小于覆盖部分141的第二厚度T2。如此，膜层150可以增加封装体140的强度以防止封装体140在第一电子元件120与封装体140之间的界面处发生破裂。
封装体140可以由同一种材料制成。例如，封装体140可以为模塑料(moldingcompound)，该模塑料由含有酚醛基树脂(Novolac-based resin)、环氧基树脂(epoxy-based resin)、硅基树脂(silicone-based resin)或者另一合适的封装剂的材料制成。另外，封装体140也可以包含诸如SiO2等合适的填充料。
膜层150设置在第一电子元件120的上表面120u上，例如膜层150可以为附着在第一电子元件120的上表面120u上的薄膜(film)，又例如可以采用涂布(coating)工艺来于第一电子元件120的上表面120u上形成该薄膜。膜层150可以增加第一电子元件120和封装体140之间的界面强度，从而防止封装体140在第一电子元件120和封装体140之间的界面处破裂。另外，膜层150具有粘附性，以有助于将封装体140固定至第一电子元件120，从而增加膜层150与封装体140之间的附着力以及膜层150与第一电子元件120之间的附着力。另外，膜层150可以由环氧树脂、丙烯酸酯树脂或者他们的组合物制成。
在本实施例中，膜层150可以直接附着在第一电子元件120的上表面120u上。在另一实施例中，膜层150可以通过任意层结构(诸如粘附层)附着至第一电子元件120的上表面120u。
图2示意了根据本发明另一实施例的半导体封装200的结构示意图。该半导体封装200包括：上述的基底110、上述的至少一个电子元件120，上述的至少一个导电接头135、上述的封装体140和上述的膜层150。相比于半导体封装100，该半导体封装200可以省略上述的第一导电接头130。
图3示意了本发明实施例的半导体装置10的结构示意图。该半导体装置10包括：半导体封装100及至少一个第二电子元件11。
该第二电子元件11例如可以是存储器、非存储器的半导体元件、另一半导体封装、有源元件、无源元件，等等。在另一实施例中，第二电子元件11可以为含有多个晶粒的半导体封装，诸如彼此堆叠的多个DRAM(Dynamic Random Access Memory，动态随机存取存储器)。
第二电子元件11以“正面向下”的方向或者“正面向上”的方向堆叠在半导体封装100的封装体140上。第二电子元件11通过多个导电接头12电性连接至半导体封装100的第一导电接头130，使得第二电子元件11可以通过导电接头12、第一导电接头130和基底110电性连接至第一电子元件120。此种配置有时也称为“倒装芯片”。导电接头12可以为焊料球、导电柱，等等。
在其他实施例中，第二电子元件11可以采取“正面向上”的方向来堆叠至半导体封装100，并且通过多条导电接合线(未示出)来电性连接至第一导电接头130。
由于膜层150设置在第一电子元件120上以增加第一电子元件120和封装体140之间的界面的强度，因此即使通过加热来将第二电子元件11从半导体封装100移除，也不会轻易使得第一电子元件120和/或封装体140破裂或损伤。
图4A至4G示意了图1的半导体封装100的制造过程。
参考图4A，提供了晶圆120′，其中该晶圆120′具有至少一个电路(未示出)。接着，可以研磨晶圆120′的上表面120u以加强晶粒强度。
参考图4B，将膜层150附着至晶圆120′并且导电接头121设置在晶圆120′上。在实施例中，可以首先将膜层150附着(如黏附)至晶圆120′，接着将导电接头121设置在晶圆120′上。在另一实施例中，可以首先将导电接头121设置在晶圆120′上，接着将膜层150附着至晶圆120′。另外，可以加热膜层150以使其固化。
参考图4C，至少一条切割路径P1穿过晶圆120′及膜层150以形成至少一个第一电子元件120，其中膜层150设置于该第一电子元件120上。例如可以通过使用激光或者机械锯(saw)等来形成切割路径P1。
参考图4D，提供了基底110。该基底110例如为多层结构或者单层结构。该基底110可以为有机基底、陶瓷基底、硅基底、金属基底，等等。在另一实施例中，该基底110可以为插入层或者晶圆，具有至少一个RDL。
参考图4E，通过使用例如SMT(surface-mount technology，表面安装技术)等技术来在基底110的上表面110u上形成第一导电接头130。
参考图4F，将具有膜层150的第一电子元件120设置在基底110上，其中第一导电接头130围绕该第一电子元件120。
参考图4G，形成封装体140，以封装第一电子元件120、膜层150以及每个第一导电接头130的一部分，其中每个第一导电接头130的另一部分从该封装体140露出。封装体140可以由各种封装技术形成，诸如压缩成型、注射成型、转移成型(transfer molding)或者点胶技术(dispensing technology)。
接着，使用例如球安装技术等方式来将图1中的第二导电接头135形成在基底110的下表面110b上，以形成图1的半导体封装100。
在另一实施例中，可以省略第一导电接头130的形成，从而形成图2的半导体封装200。
另外，通过使用SMT来将图3的第二电子元件11设置在图1的封装体140的上方，以形成图3的半导体装置10。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (10)

1.一种半导体封装，其特征在于，包括：
基底；
第一电子元件，设置在该基底上，并且具有上表面；
膜层，设置在该第一电子元件的该上表面上；以及
封装体，封装该第一电子元件与该膜层。
2.如权利要求1所述的半导体封装，其特征在于，该膜层直接附着于该第一电子元件的该上表面上。
3.如权利要求1所述的半导体封装，其特征在于，该封装体覆盖该膜层的上表面。
4.如权利要求1所述的半导体封装，其特征在于，该膜层为通过涂布工艺形成于该第一电子元件的该上表面的薄膜。
5.如权利要求1所述的半导体封装，其特征在于，该封装体包括：用来覆盖该膜层的上表面的覆盖部分，该膜层的厚度小于该覆盖部分的厚度。
6.如权利要求1所述的半导体封装，其特征在于，进一步包括：多个导电元件，设置在该基底上并且围绕该第一电子元件；其中，该每个导电元件的一部分由该封装体封装，另一部分从该封装体中露出。
7.一种半导体装置，其特征在于，包括：如权利要求1～6任一项所述的半导体封装；以及第二电子元件，堆叠在该半导体封装上。
8.一种半导体封装的制造方法，其特征在于，包括：
提供具有上表面的晶圆；
在该晶圆的该上表面上设置膜层；
形成穿过该晶圆和该膜层的切割路径，以形成至少一个第一电子元件，其中该膜层设置于该第一电子元件上；
提供基底；
将该第一电子元件设置于该基底上；并且
形成封装体，来封装该第一电子元件及该膜层。
9.如权利要求8所述的半导体封装的制造方法，其特征在于，在该晶圆的该上表面上设置膜层之前，进一步包括：研磨该晶圆的该上表面。
10.如权利要求8所述的半导体封装的制造方法，其特征在于，在该晶圆的该上表面上设置膜层之后，进一步包括：加热该膜层以固化该膜层。
CN201611074783.3A 2015-12-31 2016-11-29 半导体封装、半导体装置及制造半导体封装的方法 Active CN106971981B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201562273478P 2015-12-31 2015-12-31
US62/273,478 2015-12-31
US15/342,138 US10242927B2 (en) 2015-12-31 2016-11-03 Semiconductor package, semiconductor device using the same and manufacturing method thereof
US15/342,138 2016-11-03

Publications (2)

Publication Number Publication Date
CN106971981A true CN106971981A (zh) 2017-07-21
CN106971981B CN106971981B (zh) 2020-12-04

Family

ID=57394484

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201611074783.3A Active CN106971981B (zh) 2015-12-31 2016-11-29 半导体封装、半导体装置及制造半导体封装的方法

Country Status (4)

Country Link
US (1) US10242927B2 (zh)
EP (1) EP3188228A1 (zh)
CN (1) CN106971981B (zh)
TW (1) TWI632603B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3486943A1 (en) * 2017-11-17 2019-05-22 MediaTek Inc Semiconductor package

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1497687A (zh) * 2002-09-26 2004-05-19 ������������ʽ���� 电路装置的制造方法
US20040201096A1 (en) * 2003-03-31 2004-10-14 Tomoo Iijima Wiring circuit board, manufacturing method for the wiring circuit board, and circuit module
US20120187568A1 (en) * 2011-01-21 2012-07-26 Stats Chippac, Ltd. Semiconductor Device and Method of Forming FO-WLCSP with Multiple Encapsulants
CN103201833A (zh) * 2010-11-05 2013-07-10 英特尔公司 密封管芯、包含该密封管芯的微电子封装以及制造所述微电子封装的方法
US20130307163A1 (en) * 2012-05-17 2013-11-21 Shinko Electric Industries Co., Ltd. Semiconductor device and method of manufacturing the same
US20140327155A1 (en) * 2013-05-02 2014-11-06 Samsung Electronics Co., Ltd. Semiconductor package and method of manufacturing the same
US20140361441A1 (en) * 2013-06-11 2014-12-11 SK Hynix Inc. Stack packages and methods of manufacturing the same

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000031343A (ja) 1998-07-09 2000-01-28 Texas Instr Japan Ltd 半導体装置
US7141452B2 (en) * 2003-12-01 2006-11-28 Intel Corporation Methods of reducing bleed-out of underfill and adhesive materials
US9318441B2 (en) * 2007-12-14 2016-04-19 Stats Chippac, Ltd. Semiconductor device and method of forming sacrificial adhesive over contact pads of semiconductor die
JP2009188392A (ja) 2008-01-08 2009-08-20 Toppan Printing Co Ltd 半導体装置及び半導体装置の製造方法
JP5379527B2 (ja) * 2009-03-19 2013-12-25 パナソニック株式会社 半導体装置
JP2012099648A (ja) * 2010-11-02 2012-05-24 Fujitsu Semiconductor Ltd 半導体装置とその製造方法
KR101817159B1 (ko) * 2011-02-17 2018-02-22 삼성전자 주식회사 Ｔｓｖ를 가지는 인터포저를 포함하는 반도체 패키지 및 그 제조 방법
JP5845152B2 (ja) * 2012-07-26 2016-01-20 ルネサスエレクトロニクス株式会社 半導体装置、携帯通信機器、及び、半導体装置の製造方法
KR101659940B1 (ko) * 2013-04-26 2016-09-27 스미토모 베이클리트 컴퍼니 리미티드 감광성 조성물 및 이의 적용
KR102317263B1 (ko) * 2014-03-11 2021-10-25 삼성전자주식회사 반도체 패키지 및 이를 포함하는 데이터 저장 장치
JP2016048756A (ja) * 2014-08-28 2016-04-07 マイクロン テクノロジー， インク． 半導体装置
KR102164545B1 (ko) * 2014-09-11 2020-10-12 삼성전자 주식회사 반도체 패키지, 및 이를 포함하는 패키지 온 패키지 장치 및 모바일 장치

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1497687A (zh) * 2002-09-26 2004-05-19 ������������ʽ���� 电路装置的制造方法
US20040201096A1 (en) * 2003-03-31 2004-10-14 Tomoo Iijima Wiring circuit board, manufacturing method for the wiring circuit board, and circuit module
CN103201833A (zh) * 2010-11-05 2013-07-10 英特尔公司 密封管芯、包含该密封管芯的微电子封装以及制造所述微电子封装的方法
US20120187568A1 (en) * 2011-01-21 2012-07-26 Stats Chippac, Ltd. Semiconductor Device and Method of Forming FO-WLCSP with Multiple Encapsulants
US20130307163A1 (en) * 2012-05-17 2013-11-21 Shinko Electric Industries Co., Ltd. Semiconductor device and method of manufacturing the same
US20140327155A1 (en) * 2013-05-02 2014-11-06 Samsung Electronics Co., Ltd. Semiconductor package and method of manufacturing the same
US20140361441A1 (en) * 2013-06-11 2014-12-11 SK Hynix Inc. Stack packages and methods of manufacturing the same

Also Published As

Publication number Publication date
TWI632603B (zh) 2018-08-11
CN106971981B (zh) 2020-12-04
EP3188228A1 (en) 2017-07-05
TW201735144A (zh) 2017-10-01
US20170194227A1 (en) 2017-07-06
US10242927B2 (en) 2019-03-26

Similar Documents

Publication Publication Date Title
US6759307B1 (en) Method to prevent die attach adhesive contamination in stacked chips
KR102649471B1 (ko) 반도체 패키지 및 그의 제조 방법
KR101749284B1 (ko) 패키지 적층의 집적 회로 패키징 시스템 및 그 제조 방법
US8772947B2 (en) Methods for packaging microelectronic devices and microelectronic devices formed using such methods
US10916533B2 (en) Semiconductor package
TWI625838B (zh) 複合焊球、半導體封裝、半導體裝置及制造方法
US9922917B2 (en) Semiconductor package including substrates spaced by at least one electrical connecting element
CN103915414A (zh) 倒装芯片晶片级封装及其方法
JP2012160707A (ja) 積層半導体チップ、半導体装置およびこれらの製造方法
TW201933573A (zh) 電子封裝件及其製法
US9147600B2 (en) Packages for multiple semiconductor chips
US20080237833A1 (en) Multi-chip semiconductor package structure
KR20120040039A (ko) 적층 반도체 패키지 및 그 제조 방법
CN106548991A (zh) 半导体封装、半导体元件及其制造方法
KR20110109616A (ko) 패키지 온 패키지
US20120146242A1 (en) Semiconductor device and method of fabricating the same
TW201707174A (zh) 電子封裝件及其製法
KR20160041581A (ko) 적층형 반도체 패키지 및 이의 제조 방법
CN108807288B (zh) 电子封装件及其制法
CN106971981A (zh) 半导体封装、半导体装置及制造半导体封装的方法
US20080237831A1 (en) Multi-chip semiconductor package structure
US11195812B2 (en) Method for fabricating an encapsulated electronic package using a supporting plate
CN104051450B (zh) 半导体封装
CN106469706B (zh) 电子封装件及其制法
TWI390704B (zh) 晶片堆疊封裝結構

Legal Events

Date Code Title Description
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant