CN106920778A - 电子封装件及封装用的基板 - Google Patents

电子封装件及封装用的基板 Download PDF

Info

Publication number
CN106920778A
CN106920778A CN201610027579.XA CN201610027579A CN106920778A CN 106920778 A CN106920778 A CN 106920778A CN 201610027579 A CN201610027579 A CN 201610027579A CN 106920778 A CN106920778 A CN 106920778A
Authority
CN
China
Prior art keywords
substrate
area
encapsulation
electric contact
material layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201610027579.XA
Other languages
English (en)
Other versions
CN106920778B (zh
Inventor
梁芳瑜
张宏宪
赖顗喆
林长甫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siliconware Precision Industries Co Ltd
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Publication of CN106920778A publication Critical patent/CN106920778A/zh
Application granted granted Critical
Publication of CN106920778B publication Critical patent/CN106920778B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/145—Organic substrates, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H01L2924/35121—Peeling or delaminating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/37—Effects of the manufacturing process
    • H01L2924/37001—Yield

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

一种电子封装件及封装用的基板，封装用的基板，包括：具有相邻接的第一区域及第二区域的基板本体、以及形成于该第二区域上的材料层，且该第一区域上具有多个电性接触垫，以通过该材料层的设计防止该基板本体翘曲。

Description

电子封装件及封装用的基板
技术领域
本发明有关一种封装结构，尤指一种电子封装件及封装用的基板。
背景技术
随着电子产业的蓬勃发展，许多高阶电子产品都逐渐朝往轻、薄、短、小等高集积度方向发展，且随着封装技术的演进，芯片的封装技术也越来越多样化，半导体封装件的尺寸或体积也随之不断缩小，藉以使该半导体封装件达到轻薄短小的目的。
图1为现有封装结构1的剖面示意图。如图1所示，该封装结构1包括：一封装基板10、一覆晶结合于该封装基板10上的半导体芯片12、以及用以包覆该半导体芯片12的封装胶体13。
所述的封装基板10具有多个电性接触垫100，各该电性接触垫100周围形成有钝化层101，且各该电性接触垫100上形成有一凸块底下金属层(Under Bump Metallurgy，简称UBM)102，如图1’及图1”所示。
所述的半导体芯片12是通过多个焊锡凸块11结合于各该电性接触垫100上的凸块底下金属层102上。
然而，现有封装结构1于封装过程中，该封装基板10为整版面(即量产尺寸)，且该封装基板10于布设该半导体芯片12的位置周围容易产生应力集中区域K(如图1A及图1A’所示的角落处，其中，参考图1A’可知，越靠近角落，应力越集中，即图中点的密度)，故于温度循环(temperature cycle)或应力变化时，如通过回焊炉、或经历落摔等制程或测试时，该封装基板10与该半导体芯片12(或封装胶体13)之间容易因热膨胀系数(Coefficient ofthermal expansion，简称CTE)差异(Mismatch)，而使该封装基板10容易发生翘曲(warpage)，进而导致发生植球(即封装基板10下侧的焊球14)掉落、焊球14不沾锡(non-wetting)或基板本体裂开等问题。
此外，翘曲的情况也会造成该半导体芯片12发生碎裂，致使产品良率降低。
因此，如何克服上述现有技术的问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的缺失，本发明提供一种电子封装件及封装用的基板，以防止基板本体翘曲。
本发明的封装用的基板，包括：基板本体，其具有相邻接的第一区域及第二区域，且该第一区域上具有多个电性接触垫；以及材料层，其形成于该第二区域上，以防止该基板本体翘曲。
本发明还提供一种电子封装件，其包括：基板本体，其具有相邻接的第一区域及第二区域，且该第一区域上具有多个电性接触垫；材料层，其形成于该第二区域上，以防止该基板本体翘曲；以及电子元件，其结合于该些电性接触垫上。
前述的电子封装件及其封装用的基板中，该基板本体为半导体板材、陶瓷材或有机材。
前述的电子封装件及其封装用的基板中，该基板本体中具有多个电性连接该些电性接触垫的导电穿孔。
前述的电子封装件及其封装用的基板中，该第二区域位于该基板本体的角落。
前述的电子封装件及其封装用的基板中，该材料层复形成于该第一区域中，使该第一区域分隔成至少二区块。
前述的电子封装件及其封装用的基板中，该材料层的布设位置为该基板的应力集中区域。
前述的电子封装件及其封装用的基板中，该电性接触垫周围形成有钝化层。例如，该钝化层的材质与该材料层的材质相同。
前述的电子封装件及其封装用的基板中，该电性接触垫上形成有凸块底下金属层。
前述的电子封装件及其封装用的基板中，该电性接触垫复形成于该第二区域上。例如，该第二区域上的电性接触垫外露或嵌埋于该材料层。
由上可知，本发明的电子封装件及封装用的基板中，主要通过该材料层形成于该电子元件的预设位置周围，以于封装过程中，防止该基板本体翘曲，故相比于现有技术，本发明的电子封装件及基板能避免该基板本体发生植球掉落或裂开等问题。
此外，因能避免该基板本体发生翘曲的情况，故相比于现有技术，本发明的电子元件不会发生碎裂，因而能提升产品良率。
附图说明
图1为现有电子封装件的剖面示意图；
图1’为图1的局部放大图；
图1A为图1的上视示意图；
图1A’为图1A的应力分布示意图；
图2A为本发明的电子封装件的第一实施例的剖面示意图；
图2A’为图2A的局部放大图；
图2A”为图2A的上视示意图；
图2B为图2A”的另一实施例；
图2B’为图2B的另一实施例；
图2B”为图2A的另一实施例的上视示意图；
图3A至图3E为本发明的电子封装件的第二实施例的制法的剖面示意图；以及
图3B’为图3B的另一实施例。
符号说明：
1 封装结构
10 封装基板
100 电性接触垫
101,201 钝化层
102,202,33 凸块底下金属层
11 焊锡凸块
12 半导体芯片
13 封装胶体
14 焊球
2,3 电子封装件
2a 基板
20,30’ 基板本体
200 第一电性接触垫
200’ 第二电性接触垫
21,21’,21” 材料层
22 电子元件
220,320,32 导电元件
23 封装层
30 承载件
300 导电穿孔
301 绝缘层
31 线路结构
310 介电层
311 线路层
312,312’ 绝缘保护层
9 封装基板
A 第一区域
B 第二区域
K 应力集中区域。
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点与功效。本发明也可通过其他不同的具体实例加以施行或应用，本说明书中的各项细节也可基于不同观点与应用，在不悖离本发明的精神下进行各种修饰与变更。
须知，本说明书所附图所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本创作所能产生的功效及所能达成的目的下，均应仍落在本创作所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“一”、“第一”、“第二”等用语，也仅为便于叙述的明了，而非用以限定本创作可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当亦视为本发明可实施的范畴。
请参阅图2A、图2A’、图2A”、图2B、图2B’及图2B”为本发明的电子封装件2的第一实施例的示意图。
如图2A所示，所述的电子封装件2包括：一封装用的基板2a、一结合于该基板2a上的电子元件22、以及一用以包覆该电子元件的封装层23，其中，该基板2a包含一基板本体20、以及一结合于该基板本体20上的材料层21。
所述的基板本体20具有一第一区域A及位于该第一区域A周围的多个第二区域B，且该第一区域A上具有多个第一电性接触垫200，而该第二区域B上具有多个第二电性接触垫200’。
于本实施例中，该基板本体20为陶瓷板材、绝缘板、金属板或有机板材，即一般封装基板。
此外，各该第一电性接触垫200周围形成有钝化层201，且各该第一电性接触垫200上形成有一凸块底下金属层(Under Bump Metallurgy，简称UBM)202。
又，该些第二区域B位于该基板本体20的角落，如图2A”所示。
所述的材料层21形成于各该第二区域B上。
于本实施例中，形成该材料层21的材质为氧化硅或氮化硅，且该材料层21未覆盖该些第二电性接触垫200’。
此外，该材料层21的材质亦可与该钝化层201的材质相同，例如，该钝化层201的材质为聚亚酰胺(Polyimide，简称PI)、苯并环丁烯(Benezocy-clobutene，简称BCB)或聚对二唑苯(Polybenzoxazole，简称PBO)、环氧树脂(epoxy)或聚合物(polymer)等，故能同时制作，以节省制作时间。
又，该材料层21的布设位置为该基板2a的应力集中区域。
所述的电子元件22通过多个导电元件220结合于该些第一电性接触垫200的凸块底下金属层202上。
于本实施例中，该导电元件220含有焊锡材料或铜凸块，且该电子元件22为主动元件、被动元件或其二者组合，其中，该主动元件为例如半导体芯片，而该被动元件为例如电阻、电容及电感。
此外，该材料层21’也可覆盖该第二区域B的第二电性接触垫200’，如图2B所示。或者，该些第二电性接触垫200’除了前述嵌埋于该材料层21’中，也可依需求外露于该材料层21’，如图2B’所示，使该电子元件22的部分结构覆盖于该第二区域B上方并电性连接部分该第二电性接触垫200’。
又，该基板2a可依需求设置多个电子元件22，如图2B”所示。具体地，于设置该些电子元件22之前，该材料层21”还可形成于该第一区域A中，使该第一区域A分隔成两个新的区块(如图2B所示)，以于各该区块上分别设有该些电子元件22，致使该材料层21’,21”的布设位置为该基板2a的应力集中区域。
另外，于图2A中，应可理解地，该电子元件22也可通过多个导电元件220结合于该些第二电性接触垫200’上。
所述的封装层23为如环氧树脂(epoxy)的封装胶体或介电材。
本发明的电子封装件2及其基板2a，是通过该材料层21,21’,21”形成于该电子元件22布设处的周围(即置晶区周围)，如图2A”所示的一个置晶区、或如图2B”所示的两个置晶区，即该材料层21,21’,21”形成于该基板2a于封装制程中的应力集中区域，以于封装过程中，防止该基板本体20翘曲，故能避免该基板本体20发生植球掉落或裂开等问题。具体地，当该基板本体20遇到温度循环或应力变化时，如通过回焊炉、或经历落摔等制程或测试，该基板本体20与该电子元件22(或封装层23)之间不会因热膨胀系数(CTE)差异而使该基板本体20发生翘曲(warpage)。
此外，因能避免该基板本体20发生翘曲的情况，故该电子元件22不会发生碎裂，因而能提升产品良率。
又，通过该材料层21,21’,21”的设计，能保护落摔或其它应力集中状况时，直接造成该基板本体20的碎裂。
另外，该基板本体20未整面铺设该材料层21,21’,21”(或钝化层201)，其原因在于若该基板本体20整面铺设该材料层21,21’,21”(或钝化层201)，会造黄光制程偏移、以及因钝化层201偏移而产生的未润湿(non-wetting)等问题。
图3A至图3E为本发明的电子封装件3的第二实施例的制法的剖面示意图。本实施例与第一实施例的差异在于该基板本体30’的实施例，其它结构大致相同，故以下详细说明相异处，而不再赘述相同处。
如图3A所示，提供一承载件30，且自其表面向内延伸形成有多个导电柱以作为导电穿孔300。
于本实施例中，该承载件30为如硅材、玻璃等的半导体板材，且该导电柱为金属柱，如铜柱。
此外，于制作该导电穿孔300时，先于该承载件30的表面上形成多个通孔，再形成一绝缘层301于该承载件30与该通孔的孔壁上，之后将导电材(如铜材)填入该通孔中，以令该导电材形成该导电柱，且经由整平制程，使该导电柱的上端面齐平该绝缘层301的表面。
又，可依需求采用不同的制程制作该导电穿孔300，并不限于上述。
如图3B所示，形成一线路结构31于该承载件30的表面上。
于本实施例中，该线路结构31包含多个介电层310、多个形成于该介电层310上的线路层311、以及一形成于最外层介电层310上的绝缘保护层312。
此外，最外层的该线路层311具有多个外露于该绝缘保护层312的第一电性接触垫200及第二电性接触垫200’，以于各该第一电性接触垫200上结合如焊锡材料或铜凸块的导电元件320，且可选择性形成凸块底下金属层(UBM)202于各该第一电性接触垫200上，以利于结合该导电元件320。
又，于对应各该第一电性接触垫200周围形成有钝化层201，且于该承载件30角落的绝缘保护层312上形成有材料层21。
另外，于另一实施例中，如图3B’所示，该材料层21的材质与该钝化层201的材质相同，故能同时制作，以节省制作时间。
如图3C所示，至少一电子元件22通过该导电元件220,320设于该些第一电性接触垫200上，使该电子元件22电性连接该些第一电性接触垫200。接着，形成一封装层23于该绝缘保护层312上，以令该封装层23包覆该电子元件22。
如图3D所示，研磨该承载件30的部分材质，以外露该绝缘层301与该导电穿孔300，以令该承载件30成为硅中介板(Through Silicon interposer，简称TSI)，以令该承载件30与线路结构31作为基板本体30’。
接着，形成另一绝缘保护层312’于该基板本体30’下侧，且该绝缘保护层312’外露该些导电穿孔300的下端面。之后，结合多个导电元件32于该些导电穿孔300的下端面上，且该些导电元件32电性连接各该导电穿孔300。
于本实施例中，该导电元件32含有焊锡材料或铜凸块，且可选择性于该导电元件32下方形成有凸块底下金属层(UBM)33。
如图3E所示，后续即可将该电子封装件3以其导电元件32设于一封装基板9上。
本发明的电子封装件3通过该材料层21的设计，以防止该基板本体30’翘曲，故能避免该基板本体30’发生植球掉落或裂开等问题，且能避免该电子元件22发生碎裂，因而能提升产品良率。
综上所述，本发明的电子封装件及封装用的基板，主要通过该材料层形成于该基板的置晶区周围，以防止该基板本体翘曲，故能避免因基板本体翘曲所衍生的问题。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修饰与改变。因此，本发明的权利保护范围，应如权利要求书所列。

Claims (16)

1.一种封装用的基板，其特征为，该基板包括：
基板本体，其具有相邻接的第一区域及第二区域，且该第一区域上具有多个电性接触垫；以及
材料层，其形成于该第二区域上，以防止该基板本体翘曲。
2.如权利要求1所述的封装用的基板，其特征为，该基板本体为半导体板材、陶瓷材或有机材。
3.如权利要求1所述的封装用的基板，其特征为，该基板本体中具有多个电性连接该些电性接触垫的导电穿孔。
4.如权利要求1所述的封装用的基板，其特征为，该第二区域位于该基板本体的角落。
5.如权利要求1所述的封装用的基板，其特征为，该材料层复形成于该第一区域中，使该第一区域分隔成至少二区块。
6.如权利要求1或5所述的封装用的基板，其特征为，该材料层的布设位置为该基板的应力集中区域。
7.如权利要求1所述的封装用的基板，其特征为，该电性接触垫周围形成有钝化层。
8.如权利要求7所述的封装用的基板，其特征为，该钝化层的材质与该材料层的材质相同。
9.如权利要求1所述的封装用的基板，其特征为，该电性接触垫上形成有凸块底下金属层。
10.如权利要求1所述的封装用的基板，其特征为，该电性接触垫复形成于该第二区域上。
11.如权利要求10所述的封装用的基板，其特征为，该第二区域上的电性接触垫外露或嵌埋于该材料层。
12.一种电子封装件，其特征为，该电子封装件包括：
基板本体，其具有相邻接的第一区域及第二区域，且该第一区域上具有多个电性接触垫；
材料层，其形成于该第二区域上，以防止该基板本体翘曲；以及
电子元件，其结合于该些电性接触垫上。
13.如权利要求12所述的电子封装件，其特征为，该材料层复形成于该第一区域中，使该第一区域分隔成至少二区块。
14.如权利要求12或13所述的电子封装件，其特征为，该材料层的布设位置为该基板的应力集中区域。
15.如权利要求12所述的电子封装件，其特征为，该电性接触垫周围形成有钝化层，该钝化层的材质与该材料层的材质相同。
16.如权利要求12所述的电子封装件，其特征为，该电性接触垫上形成有凸块底下金属层。
CN201610027579.XA 2015-12-28 2016-01-15 电子封装件及封装用的基板 Active CN106920778B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW104144006A TWI641087B (zh) 2015-12-28 2015-12-28 電子封裝件及封裝用之基板
TW104144006 2015-12-28

Publications (2)

Publication Number Publication Date
CN106920778A true CN106920778A (zh) 2017-07-04
CN106920778B CN106920778B (zh) 2019-09-03

Family

ID=59087383

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610027579.XA Active CN106920778B (zh) 2015-12-28 2016-01-15 电子封装件及封装用的基板

Country Status (3)

Country Link
US (1) US10062651B2 (zh)
CN (1) CN106920778B (zh)
TW (1) TWI641087B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109904126A (zh) * 2017-12-07 2019-06-18 晨星半导体股份有限公司 芯片封装结构

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109075151B (zh) 2016-04-26 2023-06-27 亚德诺半导体国际无限责任公司 用于组件封装电路的机械配合、和电及热传导的引线框架
TW202404049A (zh) 2016-12-14 2024-01-16 成真股份有限公司 標準大宗商品化現場可編程邏輯閘陣列(fpga)積體電路晶片組成之邏輯驅動器
US11625523B2 (en) 2016-12-14 2023-04-11 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips
JP2018113414A (ja) * 2017-01-13 2018-07-19 新光電気工業株式会社 半導体装置とその製造方法
US10447274B2 (en) 2017-07-11 2019-10-15 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells
US10957679B2 (en) 2017-08-08 2021-03-23 iCometrue Company Ltd. Logic drive based on standardized commodity programmable logic semiconductor IC chips
US10630296B2 (en) 2017-09-12 2020-04-21 iCometrue Company Ltd. Logic drive with brain-like elasticity and integrality based on standard commodity FPGA IC chips using non-volatile memory cells
US10608642B2 (en) 2018-02-01 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile radom access memory cells
US10623000B2 (en) 2018-02-14 2020-04-14 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
US10497635B2 (en) 2018-03-27 2019-12-03 Linear Technology Holding Llc Stacked circuit package with molded base having laser drilled openings for upper package
US10608638B2 (en) 2018-05-24 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
US11309334B2 (en) 2018-09-11 2022-04-19 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
US10892011B2 (en) 2018-09-11 2021-01-12 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
US10937762B2 (en) 2018-10-04 2021-03-02 iCometrue Company Ltd. Logic drive based on multichip package using interconnection bridge
US11616046B2 (en) 2018-11-02 2023-03-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
US11410977B2 (en) 2018-11-13 2022-08-09 Analog Devices International Unlimited Company Electronic module for high power applications
US11211334B2 (en) 2018-11-18 2021-12-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
US11227838B2 (en) 2019-07-02 2022-01-18 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cooperating or supporting circuits
US10985154B2 (en) 2019-07-02 2021-04-20 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cryptography circuits
US11887930B2 (en) 2019-08-05 2024-01-30 iCometrue Company Ltd. Vertical interconnect elevator based on through silicon vias
US11637056B2 (en) 2019-09-20 2023-04-25 iCometrue Company Ltd. 3D chip package based on through-silicon-via interconnection elevator
US11600526B2 (en) 2020-01-22 2023-03-07 iCometrue Company Ltd. Chip package based on through-silicon-via connector and silicon interconnection bridge
US11844178B2 (en) 2020-06-02 2023-12-12 Analog Devices International Unlimited Company Electronic component

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1282982A (zh) * 1997-07-30 2001-02-07 株式会社日立制作所 半导体器件的制造方法
US20060207088A1 (en) * 2005-03-15 2006-09-21 Shinko Electric Industries Co., Ltd Wiring board manufacturing method
CN101066001A (zh) * 2004-11-18 2007-10-31 松下电器产业株式会社 布线基板及其制造方法以及半导体器件
US20090145635A1 (en) * 2007-12-06 2009-06-11 Shinko Electric Industries Co., Ltd. Wiring substrate, manufacturing method of the same, and electronic component device
CN103426835A (zh) * 2012-05-14 2013-12-04 新科金朋有限公司 控制半导体封装中的翘曲的半导体器件和方法
TW201409633A (zh) * 2012-08-24 2014-03-01 Kinsus Interconnect Tech Corp 晶片及載板的封裝結構

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4265997B2 (ja) * 2004-07-14 2009-05-20 富士通マイクロエレクトロニクス株式会社 半導体装置及びその製造方法
US9275924B2 (en) * 2012-08-14 2016-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package having a recess filled with a molding compound
TWI517328B (zh) * 2013-03-07 2016-01-11 矽品精密工業股份有限公司 半導體裝置
TWI566364B (zh) * 2014-01-03 2017-01-11 矽品精密工業股份有限公司 半導體封裝件及其製法
KR101647559B1 (ko) * 2014-11-07 2016-08-10 앰코 테크놀로지 코리아 주식회사 반도체 패키지의 제조 방법 및 반도체 패키지
KR20160139815A (ko) * 2015-05-28 2016-12-07 삼성전자주식회사 집적회로 소자 및 이의 제조 방법
CN105493204A (zh) * 2015-10-29 2016-04-13 京东方科技集团股份有限公司 各向异性导电胶、绑定结构显示面板及其制备方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1282982A (zh) * 1997-07-30 2001-02-07 株式会社日立制作所 半导体器件的制造方法
CN101066001A (zh) * 2004-11-18 2007-10-31 松下电器产业株式会社 布线基板及其制造方法以及半导体器件
US20060207088A1 (en) * 2005-03-15 2006-09-21 Shinko Electric Industries Co., Ltd Wiring board manufacturing method
US20090145635A1 (en) * 2007-12-06 2009-06-11 Shinko Electric Industries Co., Ltd. Wiring substrate, manufacturing method of the same, and electronic component device
CN103426835A (zh) * 2012-05-14 2013-12-04 新科金朋有限公司 控制半导体封装中的翘曲的半导体器件和方法
TW201409633A (zh) * 2012-08-24 2014-03-01 Kinsus Interconnect Tech Corp 晶片及載板的封裝結構

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109904126A (zh) * 2017-12-07 2019-06-18 晨星半导体股份有限公司 芯片封装结构

Also Published As

Publication number Publication date
TW201724380A (zh) 2017-07-01
CN106920778B (zh) 2019-09-03
TWI641087B (zh) 2018-11-11
US20170186702A1 (en) 2017-06-29
US10062651B2 (en) 2018-08-28

Similar Documents

Publication Publication Date Title
CN106920778B (zh) 电子封装件及封装用的基板
US11164817B2 (en) Multi-chip package structures with discrete redistribution layers
US10879194B2 (en) Semiconductor device package and method of manufacturing the same
TWI499023B (zh) 封裝基板及其製法
TWI582928B (zh) 基板結構及其製法
US9502360B2 (en) Stress compensation layer for 3D packaging
TWI698966B (zh) 電子封裝件及其製法
US20140264813A1 (en) Semiconductor Device Package and Method
US20170236797A1 (en) Ball Height Control in Bonding Process
US20180233440A1 (en) Reconstituted interposer semiconductor package
TWI649839B (zh) 電子封裝件及其基板構造
TW201911508A (zh) 電子封裝件
CN107403785B (zh) 电子封装件及其制法
TW202209582A (zh) 電子封裝件及其製法
CN103839897B (zh) 集成电路封装及制造方法
TWI436461B (zh) 封裝基板結構及其製法暨覆晶封裝結構及其製法
TWI601259B (zh) 電子封裝件及其半導體基板與製法
TWI669793B (zh) 基板結構
TWI802726B (zh) 電子封裝件及其承載基板與製法
CN110164781A (zh) 电子封装件的制法
KR20120132511A (ko) 임베딩된 다이를 갖는 집적 회로 패키지 내의 열 비아들
TWI585925B (zh) 基板結構
TWI613729B (zh) 基板結構及其製法
TWI836979B (zh) 電子封裝件及其製法
KR102723551B1 (ko) 반도체 패키지

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant