CN106816359B - Wafer processing method - Google Patents
Wafer processing method Download PDFInfo
- Publication number
- CN106816359B CN106816359B CN201510870094.2A CN201510870094A CN106816359B CN 106816359 B CN106816359 B CN 106816359B CN 201510870094 A CN201510870094 A CN 201510870094A CN 106816359 B CN106816359 B CN 106816359B
- Authority
- CN
- China
- Prior art keywords
- wafer
- gas
- processing method
- reaction chamber
- channel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
- H01L21/02046—Dry cleaning only
Abstract
The invention provides a wafer processing method, which uses semiconductor processing equipment with a double-channel air inlet nozzle to process a wafer, wherein the semiconductor processing equipment comprises a reaction chamber, and a bearing device for bearing the wafer is arranged in the reaction chamber; the double-channel gas inlet nozzle is arranged at the top of the reaction chamber and is positioned above the bearing device, the double-channel gas inlet nozzle comprises a central channel and an annular channel surrounding the central channel, and the wafer processing method comprises the following steps: a processing step, namely processing the wafer, and conveying process gas into the reaction chamber through the annular channel during the processing; a purge step, before and/or after the process step, delivering a purge gas through the central passage toward the wafer surface. The wafer processing method provided by the invention not only can effectively remove the residual condensation particles on the surface of the wafer, but also can remove the process residual gas such as halogen acid and the like generated in the reaction chamber.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a wafer processing method.
Background
Plasma processing equipment is widely used in the manufacturing process of Integrated Circuits (ICs) or MEMS devices, which uses a radio frequency power supply to excite a process gas into a high energy plasma, which reacts with the wafer surface to complete the etching process.
Fig. 1 is a schematic configuration diagram of a conventional plasma processing apparatus. Referring to fig. 1, the plasma processing apparatus includes four reaction chambers (PM1 to PM4), a transfer chamber TM, two transition chambers (LLA and LLB), and an EFEM chamber. Wherein, the four reaction chambers (PM 1-PM 4) are used for finishing the plasma etching process sequentially or simultaneously; the transfer chamber TM is used to transfer the wafer between the respective chambers; two transition chambers (LLA and LLB) are used to complete the transition between atmospheric and vacuum states of the wafers, and the EFEM chamber is used to store the wafers while providing a microenvironment for the wafers, so that a uniform air flow from top to bottom is generated inside the EFEM, thereby preventing the wafers from being contaminated by particles. However, since the four reaction chambers (PM1 to PM4) are in the atmospheric environment, the atmospheric components thereof are corroded by the halogen acid under the action of the process gas and generate particles, and the particles can cause the defects of the wafer if falling on the surface of the wafer. In addition, after the etching process is finished, halogen gas or compounds may remain on the surface of the wafer and undergo Condensation reaction in the atmosphere to form droplet-shaped Condensation particles (Condensation defects) which are irregularly distributed on the surface of the wafer, thereby seriously affecting the yield of the etching product.
For this reason, one conventional method for removing particles is to introduce N into the reaction chamber before and after the etching process2Or Ar or the like, to remove particles (dust or etching by-products) falling on the wafer surface during the transfer or etching process, thereby avoiding the influence of the particles on the product yield.
However, in practical applications, the above method still has the following problems:
firstly, when the surface of the wafer is purged, N is introduced into the reaction chamber2Or Ar and other gases can randomly float under the influence of the airflow, and the process residual gas such as halogen acid and the like generated in the reaction chamber can not be effectively removed, so that the problem that parts at the atmosphere end are corroded and polluted by the halogen acid still exists, and the defects of the wafer caused by the problems can be reduced only by frequent cleaning and maintenance, so that the maintenance period of the equipment is short.
Secondly, the above method cannot effectively remove the condensation particles on the wafer surface, and thus the yield of the etching product cannot be ensured.
Disclosure of Invention
The invention aims to solve at least one technical problem in the prior art, and provides a wafer processing method which not only can effectively remove residual condensation particles on the surface of a wafer, but also can remove process residual gas such as halogen acid and the like generated in a reaction chamber, thereby reducing the defects of the wafer, improving the yield of products and prolonging the maintenance period of semiconductor processing equipment.
The wafer processing method is used for processing a wafer by using semiconductor processing equipment with a double-channel gas inlet nozzle, and the semiconductor processing equipment comprises a reaction chamber, wherein a bearing device for bearing the wafer is arranged in the reaction chamber; the double-channel gas inlet nozzle is arranged at the top of the reaction chamber and is positioned above the bearing device, the double-channel gas inlet nozzle comprises a central channel and an annular channel surrounding the central channel, and the wafer processing method comprises the following steps:
a processing step of processing a wafer and conveying a process gas into the reaction chamber through the annular channel during the processing;
a purge step of delivering a purge gas through the central passage toward the wafer surface before and/or after the process step.
Preferably, said central passage comprises one or more air inlet holes; the flow rate of the purge gas flowing into the reaction chamber through the gas inlet hole is made to satisfy the requirement of removing particles on the wafer surface by setting the aperture of the gas inlet hole.
Preferably, the aperture of the air inlet hole ranges from 1 mm to 3 mm.
Preferably, the semiconductor processing equipment further comprises at least three ejector pins and an ejector pin lifting mechanism, wherein the at least three ejector pins are used for supporting the wafer; the thimble lifting mechanism is used for driving the at least three thimbles to ascend to a first position or descend to a second position, and the first position is a position where the top ends of the thimbles are higher than the bearing surface of the bearing device for bearing the wafer; the second position is a position where the top end of the thimble is lower than the bearing surface of the bearing device for bearing the wafer; the wafer processing method comprises the following steps:
and a wafer lifting step, before and/or after the process step and before the purging step, driving the thimble to lift to the first position by using the thimble lifting mechanism so as to lift the wafer placed on the bearing device.
Preferably, in the purging step, at least one of a combination of a gas species of the purge gas, a gas flow rate, a pressure of the reaction chamber, and a purge time is set according to different processes to effectively remove particles on the wafer surface.
Preferably, the combination of gas species of the purge gas comprises one inert gas or a combination of different inert gases.
Preferably, the inert gas comprises nitrogen or argon.
Preferably, the gas flow rate ranges from 100 sccm to 200 sccm.
Preferably, the pressure of the reaction chamber ranges from 40 mT to 150 mT.
Preferably, the value range of the purging time is 4-10 s.
The invention has the following beneficial effects:
the invention provides a wafer processing method, which uses semiconductor processing equipment with a double-channel gas inlet nozzle to process a wafer, and performs a purging step before and/or after a process step, wherein the purging step is to enable a central channel of the double-channel gas inlet nozzle to convey purging gas to the surface of the wafer. Due to the special structure of the central channel of the double-channel air inlet nozzle, the flow velocity of the purging gas can be improved, so that the residual condensation particles on the surface of the wafer can be effectively removed, and the product yield can be improved. Moreover, as the purging gas entering the reaction chamber does not flow randomly, the process residual gas such as halogen acid generated in the reaction chamber can be removed efficiently, and the problem that parts at the atmosphere end are corroded and polluted by the halogen acid can be further relieved, so that the defects of wafers can be reduced, the yield of products can be improved, and the maintenance period of semiconductor processing equipment can be prolonged.
Drawings
FIG. 1 is a schematic structural view of a conventional plasma processing apparatus;
FIG. 2 is a cross-sectional view of a semiconductor processing apparatus used in a wafer processing method according to an embodiment of the present invention;
FIG. 3 is a cross-sectional view of a dual channel gas inlet nozzle of the semiconductor processing apparatus of FIG. 2; and
fig. 4 is a flow chart of a wafer processing method according to an embodiment of the invention.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the following describes the wafer processing method provided by the present invention in detail with reference to the accompanying drawings.
The wafer processing method provided by the embodiment of the invention is used for processing the wafer by using the semiconductor processing equipment with the double-channel air inlet nozzle. Fig. 2 is a cross-sectional view of a semiconductor processing apparatus used in a wafer processing method according to an embodiment of the present invention. Referring to fig. 2, the semiconductor processing apparatus includes a reaction chamber 1, and a carrier 2, such as an electrostatic chuck, a mechanical chuck, a susceptor, or the like, for carrying a wafer 4 is disposed in the reaction chamber 1. The double channel gas inlet nozzle is disposed at the top of the reaction chamber 1 above the carrier 2, and fig. 3 is a cross-sectional view of the double channel gas inlet nozzle of the semiconductor processing apparatus of fig. 2, which includes a central channel 6 and an annular channel 5 surrounding the central channel 6, as shown in fig. 3. The central channel 6 and the annular channel 5 are spaced apart from each other and can independently supply gas into the reaction chamber 1.
Fig. 4 is a flow chart of a wafer processing method according to an embodiment of the invention. Referring to fig. 4, in the premise of using the semiconductor processing apparatus, the method for processing a wafer according to the embodiment of the present invention includes:
a process step of processing the wafer and supplying a process gas into the reaction chamber 1 through the annular channel 5 and/or the central channel 6 during the processing.
A purge step, after completion of the process step, of delivering a purge gas through the central passage 6 towards the wafer surface.
In the process step, the annular channel 5 is independently utilized to convey the process gas into the reaction chamber 1, so that not only can more uniform plasma distribution be obtained, but also different channels can be respectively used for conveying the gas into the reaction chamber 1 in the process step and the purging step, the switching process is simple, and the switching efficiency is high. In practical application, the on-off of the annular channel 5 and the central channel 6 can be controlled independently through on-off switches of two pneumatic diaphragm valves and the like.
As can be seen from fig. 3, the central channel 6 has a structure of elongated holes, which can make the gas flowing out of the central channel have a high flow rate, and the gas outlet end of the central channel 6 is located above the wafer 4, which can eject the gas from top to bottom, so that the gas entering the reaction chamber 1 has the characteristics of high speed and directionality by means of the central channel 6. Therefore, the central channel 6 is used in the purging step, so that a good purging effect can be achieved, the residual condensation particles on the surface of the wafer can be effectively removed, and the product yield can be improved. Moreover, as the purging gas entering the reaction chamber 1 does not flow randomly, the process residual gas such as halogen acid generated in the reaction chamber 1 can be removed efficiently, and the problem that parts at the atmosphere end are corroded and polluted by the halogen acid can be further relieved, so that the defects of wafers can be reduced, the yield of products can be improved, and the maintenance period of semiconductor processing equipment can be prolonged. The gas species combination of the purge gas includes one kind of inert gas or a combination of different kinds of inert gases. The inert gas includes nitrogen, argon, etc.
In the present embodiment, the central passage 6 is formed by a single gas inlet, but the present invention is not limited thereto, and in practical applications, the central passage 6 may be formed by a plurality of gas inlets for supplying the purge gas into the reaction chamber simultaneously during the purge step. Further, by setting the hole diameters of the above-mentioned gas inlet holes, the gas flow rate of the purge gas can be adjusted so that the gas flow rate of the purge gas flowing into the reaction chamber 1 through each gas inlet hole satisfies the requirement of removing particles on the wafer surface. Preferably, the aperture of the air inlet hole ranges from 1 mm to 3 mm. In addition, in practical applications, the gas flow rate of the purge gas flowing into the center passage 6 may be controlled by providing an MFC (mass flow controller) on a gas pipe connected to the two-passage gas inlet nozzle.
In the purge step, at least one of a combination of a gas type of the purge gas, a gas flow rate, a pressure of the reaction chamber, and a purge time may be set according to different processes, so that particles remaining on the wafer surface after the completion of the different processes may be removed in a targeted manner. For example, in the case of an etching process, Condensation particles (Condensation defects) are formed on the wafer surface in the form of droplets, and halogen acid particles are formed on the wafer surface due to the corrosive contamination of atmospheric components with halogen acid. Preferably, the gas flow of the purge gas is in the range of 100-200 sccm. The value range of the pressure of the reaction chamber is 40-150 mT. Under the conditions of the gas flow rate and the chamber pressure, the wafer is not affected. The value range of the purging time is 4-10 s, and particles on the surface of the wafer can be effectively removed in the range on the premise of ensuring the production performance.
Preferably, in the wafer processing method according to the embodiment of the present invention, the ejector pin and the ejector pin lifting mechanism in the semiconductor processing apparatus may be further used to purge the lower surface of the wafer 4. Specifically, as shown in fig. 2, the semiconductor processing apparatus further includes at least three pins 3 and a pin lifting mechanism (not shown), wherein the at least three pins 3 are used for supporting the wafer 4; the pin lifting mechanism is configured to drive at least three pins 3 to ascend to a first position or descend to a second position, where the first position is a position where the top ends of the pins 3 are higher than a carrying surface of the carrying device 2 for carrying a wafer, such as the position of the pins 3 in fig. 2. The second position is the position where the top end of the thimble 3 is lower than the carrying surface of the carrying device for carrying the wafer.
By using the thimble and the thimble lifting mechanism, the wafer processing method provided by the embodiment of the invention further comprises the following steps:
in the wafer lifting step, i.e., after the process step and before the purging step, the lift pin 3 is driven to lift up to the first position by the lift pin mechanism to lift up the wafer 4 placed on the carrier 2.
Thus, when the subsequent purging step is performed, since the lower surface of the wafer 4 is exposed to the environment of the reaction chamber 1, the gas flow in the reaction chamber 1 purges the lower surface of the wafer 4, so that the particles adhered to the lower surface of the wafer 4 can be removed.
It should be noted that, in this embodiment, the purging step is performed only after the process step is completed, or the wafer lifting step and the purging step are performed sequentially. However, the present invention is not limited thereto, and in practical applications, the purging step may be performed only before the process step, or the wafer raising step and the purging step may be performed sequentially. Alternatively, the purging step may be performed both before and after the process step, or both the wafer raising step and the purging step may be performed sequentially.
It should be noted that the wafer processing method provided by the present invention is to process a wafer by using the existing semiconductor processing equipment with a dual-channel air inlet nozzle, and besides the number and the aperture of the air inlet holes of the central channel 6 can be adjusted according to the requirements of different processing technologies, the hardware upgrading and modification of the equipment is not performed, so that the cost of hardware upgrading and modification can be saved while the particles on the surface of the wafer can be effectively removed.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.
Claims (9)
1. The wafer processing method is characterized in that a semiconductor processing device with a double-channel air inlet nozzle is used for processing a wafer, the semiconductor processing device comprises a reaction chamber, and a bearing device used for bearing the wafer is arranged in the reaction chamber; the double-channel gas inlet nozzle is arranged at the top of the reaction chamber and is positioned above the bearing device, the double-channel gas inlet nozzle comprises a central channel and an annular channel surrounding the central channel, and the wafer processing method comprises the following steps:
a processing step of processing a wafer and conveying a process gas into the reaction chamber through the annular channel during the processing;
a purge step of delivering a purge gas through the central passage toward the wafer surface before and/or after the process step; wherein the content of the first and second substances,
the central passage comprises one or more inlet apertures; the flow rate of the purge gas flowing into the reaction chamber through the gas inlet hole is made to satisfy the requirement of removing particles on the wafer surface by setting the aperture of the gas inlet hole.
2. The wafer processing method as set forth in claim 1, wherein the aperture of the gas inlet hole has a value ranging from 1 to 3 mm.
3. The wafer processing method of claim 1, wherein the semiconductor processing equipment further comprises at least three pins and a pin lifting mechanism, wherein the at least three pins are used for supporting the wafer; the thimble lifting mechanism is used for driving the at least three thimbles to ascend to a first position or descend to a second position, and the first position is a position where the top ends of the thimbles are higher than the bearing surface of the bearing device for bearing the wafer; the second position is a position where the top end of the thimble is lower than the bearing surface of the bearing device for bearing the wafer;
the wafer processing method comprises the following steps:
and a wafer lifting step, before and/or after the process step and before the purging step, driving the thimble to lift to the first position by using the thimble lifting mechanism so as to lift the wafer placed on the bearing device.
4. The wafer processing method as set forth in claim 1, wherein in the purge step, at least one of a combination of a gas species of the purge gas, a gas flow rate, a pressure of the reaction chamber and a purge time is set according to different processes to effectively remove particles on the wafer surface.
5. The wafer processing method of claim 4, wherein the combination of gas species of the purge gas comprises one inert gas or a combination of different inert gases.
6. The wafer processing method of claim 5, wherein the inert gas comprises nitrogen or argon.
7. The wafer processing method of claim 4, wherein the gas flow rate is in a range of 100 to 200 sccm.
8. The wafer processing method of claim 4, wherein the pressure of the reaction chamber is in a range of 40 mT to 150 mT.
9. The wafer processing method of claim 4, wherein the purge time is in a range of 4-10 s.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510870094.2A CN106816359B (en) | 2015-12-02 | 2015-12-02 | Wafer processing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510870094.2A CN106816359B (en) | 2015-12-02 | 2015-12-02 | Wafer processing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106816359A CN106816359A (en) | 2017-06-09 |
| CN106816359B true CN106816359B (en) | 2020-06-19 |
Family
ID=59107486
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510870094.2A Active CN106816359B (en) | 2015-12-02 | 2015-12-02 | Wafer processing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106816359B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109107987A (en) * | 2017-06-22 | 2019-01-01 | 北京北方华创微电子装备有限公司 | A kind of blowing method |
| KR102126466B1 (en) * | 2018-09-27 | 2020-06-24 | 크린팩토메이션 주식회사 | Eqipment front end module |
| CN111952139B (en) * | 2019-05-16 | 2023-11-14 | 北京北方华创微电子装备有限公司 | Semiconductor manufacturing apparatus and semiconductor manufacturing method |
| CN112885745B (en) * | 2021-01-19 | 2022-04-26 | 长鑫存储技术有限公司 | Processing equipment and processing method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101261929A (en) * | 2007-01-30 | 2008-09-10 | 应用材料股份有限公司 | Process for wafer backside polymer removal by front side gas purge |
| CN101728230A (en) * | 2008-10-17 | 2010-06-09 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Method for processing semiconductor substrate |
| JP2013207272A (en) * | 2012-03-29 | 2013-10-07 | Dainippon Screen Mfg Co Ltd | Substrate processing apparatus |
| CN106133880A (en) * | 2014-03-28 | 2016-11-16 | 株式会社斯库林集团 | Substrate board treatment and substrate processing method using same |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8100081B1 (en) * | 2006-06-30 | 2012-01-24 | Novellus Systems, Inc. | Edge removal of films using externally generated plasma species |
| CN101623680A (en) * | 2008-07-09 | 2010-01-13 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Air inlet device and semiconductor processing equipment using same |
-
2015
- 2015-12-02 CN CN201510870094.2A patent/CN106816359B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101261929A (en) * | 2007-01-30 | 2008-09-10 | 应用材料股份有限公司 | Process for wafer backside polymer removal by front side gas purge |
| CN101728230A (en) * | 2008-10-17 | 2010-06-09 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Method for processing semiconductor substrate |
| JP2013207272A (en) * | 2012-03-29 | 2013-10-07 | Dainippon Screen Mfg Co Ltd | Substrate processing apparatus |
| CN106133880A (en) * | 2014-03-28 | 2016-11-16 | 株式会社斯库林集团 | Substrate board treatment and substrate processing method using same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106816359A (en) | 2017-06-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106816359B (en) | Wafer processing method | |
| KR101579507B1 (en) | Apparatus for Processing Substrate | |
| CN105695936A (en) | Pre-cleaning chamber and plasma processing apparatus | |
| WO2015093226A1 (en) | Substrate processing apparatus, control method for substrate processing apparatus, and recording medium | |
| JP2014197592A (en) | Substrate processor | |
| JP5329099B2 (en) | Plasma processing apparatus and operation method thereof | |
| CN107424895B (en) | Front-end processing device of semiconductor equipment | |
| CN106191990B (en) | A kind of inlet duct of boiler tube | |
| CN109817545B (en) | Semiconductor wafer processing system and method for processing semiconductor wafer | |
| KR20100046798A (en) | Single type substrate treating apparatus and method for controlling presure of substrate treating apparatus | |
| JP2005209668A (en) | Substrate treatment equipment | |
| KR100442580B1 (en) | air exhaust system of chamber for semiconductor manufacture | |
| KR102119690B1 (en) | Substrate heating unit | |
| JP2012138540A (en) | Vacuum processing apparatus | |
| KR101395248B1 (en) | nozzle unit | |
| US20060137711A1 (en) | Single-wafer cleaning procedure | |
| KR102030038B1 (en) | Apparatus for Processing Substrate | |
| JP2012169504A (en) | Liquid processing apparatus and liquid processing method | |
| KR101019843B1 (en) | Airtight module and method of exhausting the same | |
| KR101817217B1 (en) | Chuck pin, Method for manufacturing a chuck pin, Apparatus for treating a substrate | |
| JP4987219B2 (en) | Etching equipment | |
| JP2003158081A (en) | Substrate processor | |
| CN111607783B (en) | Semiconductor carrier, semiconductor processing equipment and purging method | |
| CN108847390A (en) | A kind of method of plasma etching | |
| JP5824225B2 (en) | Substrate processing equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Address after: 100176 No. 8 Wenchang Avenue, Beijing economic and Technological Development Zone Applicant after: Beijing North China microelectronics equipment Co Ltd Address before: 100176 Beijing economic and Technological Development Zone, Wenchang Road, No. 8, No. Applicant before: Beifang Microelectronic Base Equipment Proces Research Center Co., Ltd., Beijing |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant |