CN106783764A - 一种固定顶针内绝缘封装结构及其工艺方法 - Google Patents
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Abstract
本发明涉及一种固定顶针内绝缘封装结构的工艺方法,所述结构包括引线框架(1),所述引线框架(1)包括载片台(1.2)和引脚(1.1),所述载片台(1.2)上设置有芯片(2),所述芯片(2)与引线框架(1)的引脚(1.2)电性连接,所述引线框架(1)下方设置有散热片(5),所述引线框架(1)、芯片(2)、焊线(4)和散热片(5)外围均包封有塑封料(11),所述散热片(5)背面露出于塑封料(11)之外,所述散热片(5)中间设置有一开孔(8),所述载片台(1.2)背面正对散热片(5)的开孔(8)位置暴露于塑封料(11)之外。本发明一种固定顶针内绝缘封装结构及其工艺方法,它能够解决传统通过陶瓷片绝缘的价格昂贵和绝缘性不可控的限制。
Description
技术领域
本发明涉及一种固定顶针内绝缘封装结构及其工艺方法,属于半导体封装技术领域。
背景技术
由于大功率MOS管发热量较大,而散热效果的优劣可以直接影响MOS管及设备的稳定性,因此通常会在大功率MOS管背面贴装散热器以提高大功率三极管的散热效率。然而,为保证其应用于高压环境中的大功率MOS管的绝缘性能,需要在制造的过程中采用绝缘措施将引线框架与散热器隔开。最常见的方法是把陶瓷片贴装于引线框架与散热器之间。这种绝缘措施有以下缺点:
1、陶瓷片的绝缘的绝缘性市场上优劣不等,需要繁琐的检验流程确定其绝缘性;
2、陶瓷片装片时如发生斜管将直接导致,芯片离载片台的距离不等,绝缘效果也不等;
3、陶瓷片的制作流程繁琐,市场价格昂贵。
发明内容
本发明所要解决的技术问题是针对上述现有技术提供一种固定顶针内绝缘封装结构及其工艺方法,它能够解决传统通过陶瓷片绝缘的价格昂贵和绝缘性的限制。
本发明解决上述问题所采用的技术方案为:一种固定顶针内绝缘封装结构,它包括引线框架,所述引线框架包括载片台和引脚,所述载片台上通过焊料设置有芯片,所述芯片通过焊线与引线框架的引脚电性连接,所述引线框架下方设置有散热片,所述引线框架、芯片、焊线和散热片外围均包封有塑封料,所述散热片背面露出于塑封料之外,所述散热片中间设置有一开孔,所述载片台背面正对散热片的开孔位置暴露于塑封料之外。
所述载片台上设置有V形槽,所述V形槽位于芯片外围。
所述散热片背面四周边缘处设置有锁胶台阶。
一种固定顶针内绝缘封装结构的工艺方法,所述方法包括以下步骤:
步骤一、取一引线框架,引线框架包含载片台和引脚;
步骤二,在步骤一引线框架的载片台上涂覆导电或不导电粘结物质,然后在粘结物质上植入芯片;
步骤三,在芯片正面与引脚正面之间进行键合金属线作业;
步骤四,提供一散热片,散热片中间具有一开孔,散热片背面设有锁胶台阶;
步骤五,预置散热片至模具内,模具上对应散热片开孔位置具有一顶针,顶针穿过散热片的开孔并露出散热片上表面;
步骤六、将步骤三完成键合金属线作业的引线框架放入模具中,模具的顶针向上顶起载片台,使载片台下表面距离散热片上表面有一定距离;
步骤七、向模具内注入塑封料,注入塑封料后,散热片和载片台之间的间隙中会填充进塑封料,使散热片和载片台之间绝缘;
步骤八、将步骤七完成塑封的半成品进行切割或是冲切作业,使原本阵列式的塑封体切割或是冲切独立开来,制得一种固定顶针内绝缘封装结构。
所述金属线的材料采用金、银、铜、铝或是合金的材料。
所述金属丝的形状是丝状或是带状。
所述塑封料可以采用有填料物质或是无填料物质的环氧树脂。
与现有技术相比,本发明的优点在于:
本发明一种固定顶针内绝缘封装结构及其工艺方法,它通过塑封料进行绝缘,工艺简单,绝缘结构制造成本低。本发明散热片和载片台之间的绝缘层厚度可安需求进行调整,其绝缘效果可控。本发明能够解决传统通过陶瓷片绝缘的价格昂贵和绝缘性不可控的限制。
附图说明
图1为本发明一种固定顶针内绝缘封装结构的示意图。
图2~图9为本发明一种固定顶针内绝缘封装结构的工艺方法的各工序流程图。
其中:
引线框架1
引脚1.1
载片台1.2
芯片2
焊料3
焊线4
散热片5
V形槽6
锁胶台阶7
开孔8
模具9
顶针10
塑封料11。
具体实施方式
以下结合附图实施例对本发明作进一步详细描述。
如图1所示,本实施例中的一种固定顶针内绝缘封装结构,它包括引线框架1,所述引线框架1包括载片台1.2和引脚1.1,所述载片台1.2上通过焊料3设置有芯片2,所述芯片2通过焊线4与引线框架1的引脚1.1电性连接,所述引线框架1下方设置有散热片5,所述散热片5背面四周边缘处设置有锁胶台阶7,所述引线框架1、芯片2、焊线4和散热片5外围均包封有塑封料11,所述散热片5背面露出于塑封料11之外,所述散热片5中间设置有一开孔8,所述载片台1.2背面正对散热片5的开孔8位置暴露于塑封料11之外;
所述载片台1.2上设置有V形槽6,所述V形槽6位于芯片2外围。
其工艺方法如下:
步骤一、参见图2,取一引线框架,引线框架包含载片台和引脚,载片台上设有V形槽;
步骤二,参见图3,在步骤一引线框架的载片台上涂覆导电或不导电粘结物质,然后在粘结物质上植入芯片;
步骤三,参见图4,在芯片正面与引脚正面之间进行键合金属线作业,所述金属线的材料采用金、银、铜、铝或是合金的材料,金属丝的形状可以是丝状也可以是带状;
步骤四,参见图5,提供一散热片,散热片中间具有一开孔,散热片背面设有锁胶台阶;
步骤五,参见图6,预置散热片至模具内,模具上对应散热片开孔位置具有一顶针,顶针穿过散热片的开孔并露出散热片上表面;
步骤六、参见图7,将步骤三完成键合金属线作业的引线框架放入模具中,模具的顶针向上顶起载片台,使载片台下表面距离散热片上表面有一定距离;
步骤七、参见图8,向模具内注入塑封料,塑封料可以采用有填料物质或是无填料物质的环氧树脂。注入塑封料后,散热片和载片台之间的间隙中会填充进塑封料,使散热片和载片台之间绝缘;
步骤八、参见图9,将步骤七完成塑封的半成品进行切割或是冲切作业,使原本阵列式的塑封体切割或是冲切独立开来,制得一种固定顶针内绝缘封装结构。
除上述实施例外,本发明还包括有其他实施方式,凡采用等同变换或者等效替换方式形成的技术方案,均应落入本发明权利要求的保护范围之内。
Claims (7)
1.一种固定顶针内绝缘封装结构,其特征在于:它包括引线框架(1),所述引线框架(1)包括载片台(1.2)和引脚(1.1),所述载片台(1.2)上通过焊料(3)设置有芯片(2),所述芯片(2)通过焊线(4)与引线框架(1)的引脚(1.1)电性连接,所述引线框架(1)下方设置有散热片(5),所述引线框架(1)、芯片(2)、焊线(4)和散热片(5)外围均包封有塑封料(11),所述散热片(5)背面露出于塑封料(11)之外,所述散热片(5)中间设置有一开孔(8),所述载片台(1.2)背面正对散热片(5)的开孔(8)位置暴露于塑封料(11)之外。
2.根据权利要求1所述的一种固定顶针内绝缘封装结构,其特征在于:所述载片台(1.2)上设置有V形槽(6),所述V形槽(6)位于芯片(2)外围。
3.根据权利要求1所述的一种固定顶针内绝缘封装结构,其特征在于:所述散热片(5)背面四周边缘处设置有锁胶台阶(7)。
4.一种固定顶针内绝缘封装结构的工艺方法,其特征在于所述方法包括以下步骤:
步骤一、取一引线框架,引线框架包含载片台和引脚;
步骤二,在步骤一引线框架的载片台上涂覆导电或不导电粘结物质,然后在粘结物质上植入芯片;
步骤三,在芯片正面与引脚正面之间进行键合金属线作业;
步骤四,提供一散热片,散热片中间具有一开孔,散热片背面设有锁胶台阶;
步骤五,预置散热片至模具内,模具上对应散热片开孔位置具有一顶针,顶针穿过散热片的开孔并露出散热片上表面;
步骤六、将步骤三完成键合金属线作业的引线框架放入模具中,模具的顶针向上顶起载片台,使载片台下表面距离散热片上表面有一定距离;
步骤七、向模具内注入塑封料,注入塑封料后,散热片和载片台之间的间隙中会填充进塑封料,使散热片和载片台之间绝缘;
步骤八、将步骤七完成塑封的半成品进行切割或是冲切作业,使原本阵列式的塑封体切割或是冲切独立开来,制得一种固定顶针内绝缘封装结构。
5.根据权利要求4所述的一种固定顶针内绝缘封装结构的工艺方法,其特征在于:所述金属线的材料采用金、银、铜、铝或是合金的材料。
6.根据权利要求4所述的一种固定顶针内绝缘封装结构的工艺方法,其特征在于:所述金属丝的形状是丝状或是带状。
7.根据权利要求4所述的一种固定顶针内绝缘封装结构的工艺方法,其特征在于:所述塑封料可以采用有填料物质或是无填料物质的环氧树脂。
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080036057A1 (en) * | 2006-08-10 | 2008-02-14 | Vishay General Semiconductor Llc | Semiconductor device having improved heat dissipation capabilities |
CN104385534A (zh) * | 2014-11-18 | 2015-03-04 | 佛山市蓝箭电子股份有限公司 | 一种塑封模具结构 |
CN105632947A (zh) * | 2015-12-24 | 2016-06-01 | 合肥祖安投资合伙企业(有限合伙) | 一种半导体器件的封装结构及其制造方法 |
CN206412343U (zh) * | 2017-01-25 | 2017-08-15 | 长电科技(宿迁)有限公司 | 一种固定顶针内绝缘封装结构 |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080036057A1 (en) * | 2006-08-10 | 2008-02-14 | Vishay General Semiconductor Llc | Semiconductor device having improved heat dissipation capabilities |
CN104385534A (zh) * | 2014-11-18 | 2015-03-04 | 佛山市蓝箭电子股份有限公司 | 一种塑封模具结构 |
CN105632947A (zh) * | 2015-12-24 | 2016-06-01 | 合肥祖安投资合伙企业(有限合伙) | 一种半导体器件的封装结构及其制造方法 |
CN206412343U (zh) * | 2017-01-25 | 2017-08-15 | 长电科技(宿迁)有限公司 | 一种固定顶针内绝缘封装结构 |
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