CN215069963U - 芯片封装结构中的金属衬底层 - Google Patents

芯片封装结构中的金属衬底层 Download PDF

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CN215069963U
CN215069963U CN202121531996.0U CN202121531996U CN215069963U CN 215069963 U CN215069963 U CN 215069963U CN 202121531996 U CN202121531996 U CN 202121531996U CN 215069963 U CN215069963 U CN 215069963U
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metal substrate
chip
substrate layer
layer
boss
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顾俊晔
付贵平
胡健
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Shanghai Xinyan Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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Abstract

本实用新型涉及一种芯片封装结构中的金属衬底层，金属衬底层用于芯片堆叠结构中同层芯片之间的电气连接，并为上层的芯片提供支撑平台作用，包括透明树脂包封层和包裹在其中的金属衬底结构，金属衬底结构自带焊接凸台，凸台压合芯片焊盘。消除金属衬底层在经过回流焊时的漂移现象和改善金属衬底层的平整性。同时降低了金属衬底层的生产成本。

Description

芯片封装结构中的金属衬底层
技术领域
本实用新型涉及一种芯片封装技术，特别涉及一种芯片封装结构中的金属衬底层。
背景技术
随着芯片领域的应用越来越广，其应用对芯片的尺寸、结构及性能要求越来越高。例如：在功率器件的芯片封装过程中，经常会应用到芯片堆叠结构，夹焊工艺及更高贴芯工艺，如图1的封装结构，其中，1为金属框架或基板，其包含金属管脚及芯片衬底；2为金属焊线，起到芯片与框架或基板的电连接作用；3和7为芯片与衬底的结合材料，其可以为银浆或者膜；4和8为位于3和7上的芯片；5为金属衬底层，作用为实现左右两个芯片之间的电气连接，并为上层的芯片8提供支撑平台作用；6为芯片4表面焊盘上的锡膏；9为最外塑胶注塑成型的塑封体。
现有的金属衬底层5，在芯片4的焊盘上预置锡膏6，经过回流焊固定使芯片4与金属衬底层5连接。锡膏6为半固体状态，所以将金属衬底层5置放在锡膏6上后，左右两侧存在高度差。同时，在经过回流焊时，锡膏6在固化前存在着流动性，所以金属衬底层5会有漂移。结合以上两个原因，对后面的焊线工艺提出了很大的挑战，进而降低了生产的合格率。不同的设计需要不同外观的金属衬底层，其生产模具价格昂贵。
实用新型内容
针对芯片封装设计中预留锡膏导致封装精度低的问题，提出了一种芯片封装结构中的金属衬底层。
本实用新型的技术方案为：一种芯片封装结构中的金属衬底层，金属衬底层用于芯片堆叠结构中同层芯片之间的电气连接，并为上层的芯片提供支撑平台作用，包括透明树脂包封层和包裹在其中的金属衬底结构，金属衬底结构自带焊接凸台，凸台压合芯片焊盘。
优选的，所述金属衬底结构自带焊接凸台高出透明树脂包封层。
优选的，所述金属衬底结构为在带有凹槽的基材上电镀的金属层。
优选的，所述焊接凸台为梯形凸台或圆形凸台。
本实用新型的有益效果在于：本实用新型芯片封装结构中的金属衬底层，消除金属衬底层在经过回流焊时的漂移现象和改善金属衬底层的平整性。同时降低了金属衬底层的生产成本。
附图说明
图1为现有的金属衬底层的封装结构示意图；
图2为本实用新型单颗金属衬底层结构示意图；
图3为本实用新型金属衬底层制备过程一示意图；
图4为本实用新型金属衬底层制备过程二示意图；
图5为本实用新型金属衬底层制备过程三示意图；
图6为本实用新型金属衬底层制备过程四示意图；
图7为本实用新型金属衬底层制备过程五示意图；
图8为采用本实用新型的金属衬底层的封装结构示意图。
附图标识：1、金属框架或基板；2、金属焊线；3、芯片与衬底的结合材料；4、芯片；5、金属衬底层；6、锡膏；7、芯片与衬底的结合材料；8、芯片；9、塑封体、10、金属衬底结构；101、焊接凸台；11、基材；12、透明树脂包封层；13、感光膜；14、树枝刀片。
具体实施方式
下面结合附图和具体实施例对本实用新型进行详细说明。本实施例以本实用新型技术方案为前提进行实施，给出了详细的实施方式和具体的操作过程，但本实用新型的保护范围不限于下述的实施例。
如图2所示一种金属衬底层结构示意图。在透明树脂包封层12内包裹电铸金属衬底结构10，其中仅金属衬底结构10自带的数个焊接凸台101高出透明树脂包封层12，所有焊接凸台101的上平面在一个水平面上。焊接凸台101可根据客户的位置需求随意设计，凸台101可选图中所示梯形凸台，也可是圆形凸台，只要凸台上有与芯片焊盘贴合的平面即可。同时，此金属衬底层通过透明树脂包封层12，起到保护作用并为拾取提供清洗的标识点。
制备过程：如图3所示，在带有凹槽的基材11上在规定位置上电镀一层金属层，即在基材11上预置了带有凸台的数个相同金属衬底结构10。如图4所示通过注塑工艺用透明树脂将金属衬底结构10包封，形成透明树脂包封层12。如图5所示将透明树脂包封层12上层远离金属衬底结构10凸台101的一面贴上感光膜13然后翻转，使金属衬底结构10的带凸台101的面朝上，并通过人工或者机械设备将基材11与透明树脂包封层12分离，并使金属衬底结构10凸台面下其余部分留在透明树脂包封层12内。如图6所示运用切割机的树脂刀片14切割透明树脂包封层12和感光膜13，使矩阵的金属衬底结构10分离成单颗。如图7所示通过紫外线光照机照射感光膜13使其失去粘性，使单颗金属衬底结构10与感光膜13分离开。形成本实用新型的金属衬底层，如图2所示。
本实用新型金属衬底层在基材上电铸成型的金属层，通过注塑工艺，用透明树脂将金属衬底层包封，只有凸点面外露。将透明树脂面贴在光感膜上，手动或机械设备将基材与包封体分离，通过切割机进行切割分离，使其成为单颗个体。
如图8为本实用新型运用示意图，构成的金属衬底层直接运用到芯片中，对比图1和图8，图1中是，锡膏点在芯片表面的焊盘上，然后盖上金属衬底层，进行回流焊，这时由于锡膏的流动性，造成金属焊盘的漂移。图8金属衬底结构是有凸台结构的，与锡膏接触时，其也会与芯片焊盘连接，增加了其结合性，避免漂移。单个个体是从制备后的同一基板上切割出来，保证一批个体一致性好，带焊接梯形凸台101的金属衬底结构是电镀出，改善金属衬底层的平整性。
以上所述实施例仅表达了本实用新型的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对实用新型专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本实用新型构思的前提下，还可以做出若干变形和改进，这些都属于本实用新型的保护范围。因此，本实用新型专利的保护范围应以所附权利要求为准。

Claims (4)

1.一种芯片封装结构中的金属衬底层，金属衬底层用于芯片堆叠结构中同层芯片之间的电气连接，并为上层的芯片提供支撑平台作用，其特征在于，包括透明树脂包封层和包裹在其中的金属衬底结构，金属衬底结构自带焊接凸台，焊接凸台压合芯片焊盘。
2.根据权利要求1所述芯片封装结构中的金属衬底层，其特征在于，所述金属衬底结构自带焊接凸台高出透明树脂包封层。
3.根据权利要求1或2所述芯片封装结构中的金属衬底层，其特征在于，所述金属衬底结构为在带有凹槽的基材上电镀的金属层。
4.根据权利要求3所述芯片封装结构中的金属衬底层，其特征在于，所述焊接凸台为梯形凸台或圆形凸台。
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