CN106783716A - 一种降低易碎基底在半导体制程中破片率的方法 - Google Patents

一种降低易碎基底在半导体制程中破片率的方法 Download PDF

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CN106783716A
CN106783716A CN201611101547.6A CN201611101547A CN106783716A CN 106783716 A CN106783716 A CN 106783716A CN 201611101547 A CN201611101547 A CN 201611101547A CN 106783716 A CN106783716 A CN 106783716A
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epitaxial wafer
manufacture
reducing
metal film
fragment rate
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CN106783716B (zh
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魏鸿基
许燕丽
王江
朱庆芳
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Integrated Circuit Co Ltd Is Pacified By Xiamen City Three
Xiamen Sanan Integrated Circuit Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6835—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during build up manufacturing of active devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Mechanical Treatment Of Semiconductor (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

本发明公开了一种降低易碎基底在半导体制程中破片率的方法，包括以下步骤：1)、在制备性能器件之前，在外延片正面设置保护层；2)、在外延片背面镀上一层金属膜；3)、将外延片与保护层分离；4)、在外延片表面制备所需的性能器件；5)、去除外延片背面的金属膜，并减薄外延片至所需厚度。本发明通过在外延片背面镀上一层金属膜，以此增强外延片的强度，且不会影响前段制程正常作业，从而降低外延片在前段制程中的破片几率，节约生成成本。

Description

一种降低易碎基底在半导体制程中破片率的方法
技术领域
本发明涉及一种半导体制造领域，特别是涉及一种降低易碎基底在半导体制程中破片率的方法。
背景技术
锗基器件与磷化铟基器件由于其不可替代的优势，在半导体产业中有着广泛应用。例如：由于高电子迁移率、高光电转换效率及高抗辐射阈值，锗衬底广泛应用于太阳能电池中。其中锗衬底高效太阳能电池在空间应用比例已超过80％。InP基器件具有高频、低噪声、高效率、抗辐照等特点，成为W波段以及更高频率毫米波电路的首选材料。但锗基与磷化铟基很脆弱，在前段制程中容易破裂,且破片几率随着晶圆尺寸的增加而增长。在晶圆制程中，产线良率与生产成本成反比。故在制程中，降低破片率对降低生产成本而言，至关重要。
发明内容
本发明提供了一种降低易碎基底在半导体制程中破片率的方法，用于解决易碎基底在半导体制程中破片率高的问题。
本发明解决其技术问题所采用的技术方案是：一种降低易碎基底在半导体制程中破片率的方法，包括以下步骤：
1)、在制备性能器件之前，在外延片正面设置保护层；
2)、在外延片背面镀上一层金属膜；
3)、将外延片与保护层分离；
4)、在外延片表面制备所需的性能器件；
5)、去除外延片背面的金属膜，并减薄外延片的厚度。
进一步的，所述步骤5)中，采用研磨工艺去除外延片背面的金属膜。
进一步的，所述步骤5)中，采用研磨工艺减薄外延片的厚度。
进一步的，所述金属膜的厚度为1-2μm。
进一步的，所述金属膜为惰性金属膜。
进一步的，所述步骤1)中，所述保护层为载片，该载片与外延片正面键合。
所述步骤1)中，所述保护层为保护膜，该保护膜粘贴在外延片正面。
进一步的，所述载片为蓝宝石载片。
进一步的，所述载片的厚度为0.3-0.7mm。
相较于现有技术，本发明具有以下有益效果：
通过在外延片背面镀上一层金属膜，以此增强外延片的强度，且不会影响前段制程正常作业，从而降低外延片在前段制程中的破片几率，节约生成成本。
以下结合附图及实施例对本发明作进一步详细说明；但本发明的一种降低易碎基底在半导体制程中破片率的方法不局限于实施例。
附图说明
图1是本发明的外延片键合后的结构示意图；
图2是本发明的外延片镀上金属膜后的结构示意图；
图3是本发明的外延片与载片分离后的结构示意图；
图4是本发明的外延片表面制备所需的性能器件后的结构示意图；
图5是本发明的外延片去除金属膜后的结构示意图；
图6是本发明的外延片减薄厚的结构示意图。
具体实施方式
实施例，本发明的一种降低易碎基底在半导体制程中破片率的方法，包括以下步骤：
1)、在制备性能器件之前，在外延片1正面设置保护层，该保护层具体为蓝宝石载片2，将外延片1正面与蓝宝石载片2(所述载片2的类型不局限于蓝宝石)进行键合，如图1所示，用于保护外延片1正面不受步骤2)的影响，即避免外延片1背面电镀金属膜3过程中，外延片1的正面受到污染；所述载片2的厚度为0.3-0.7mm，取较佳值0.7mm；
2)、在外延片1背面采用电镀方式镀上一层惰性金属膜3，如图2所示，该金属膜3覆盖外延片1的整个背面，且其厚度为1-2μm，取较佳值1.5μm；所述金属膜3的材质优选铜或金；
3)、采用芯片基板分离工艺将外延片1与载片2分离，获得只有背面镀有所述金属膜3的外延片1，如图3所示；
4)、在外延片1表面制备所需的性能器件，所述性能器件包括集电极4、基极5、发射极6和绝缘层7，如图4所示；
5)、采用研磨工艺进行第一次研磨，去除外延片1背面的金属膜3，如图5所示；
6)采用研磨工艺进行第二次研磨，减薄外延片1的厚度，将外延片1研磨到所要求的厚度，如图6所示。所述绝缘层7也相应减薄到所需的厚度。
本发明通过电镀方式在易碎基底(即所述外延片1)背面镀上一层惰性金属膜3，来增强外延片1的强度，且不会影响前段制程正常作业，以此降低外延片1在前段制程中的破片几率。
在其它实施例中，所述保护层为保护膜，在步骤1)中，其采用粘贴的方式固定在外延片的正面；在步骤3)中，可直接用手将保护膜从外延片正面撕下来。
上述实施例仅用来进一步说明本发明的一种降低易碎基底在半导体制程中破片率的方法，但本发明并不局限于实施例，凡是依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均落入本发明技术方案的保护范围内。

Claims (9)

1.一种降低易碎基底在半导体制程中破片率的方法，其特征在于，包括以下步骤：
1)、在制备性能器件之前，在外延片正面设置保护层；
2)、在外延片背面镀上一层金属膜；
3)、将外延片与保护层分离；
4)、在外延片表面制备所需的性能器件；
5)、去除外延片背面的金属膜，并减薄外延片至所需厚度。
2.根据权利要求1所述的降低易碎基底在半导体制程中破片率的方法，其特征在于：所述步骤5)中，采用研磨工艺去除外延片背面的金属膜。
3.根据权利要求1所述的降低易碎基底在半导体制程中破片率的方法，其特征在于：所述步骤5)中，采用研磨工艺减薄外延片的厚度。
4.根据权利要求1所述的降低易碎基底在半导体制程中破片率的方法，其特征在于：所述金属膜的厚度为1-2μm。
5.根据权利要求1所述的降低易碎基底在半导体制程中破片率的方法，其特征在于：所述金属膜为惰性金属膜。
6.根据权利要求1所述的降低易碎基底在半导体制程中破片率的方法，其特征在于：所述步骤1)中，所述保护层为载片，该载片与外延片正面键合。
7.根据权利要求1所述的降低易碎基底在半导体制程中破片率的方法，其特征在于：所述步骤1)中，所述保护层为保护膜，该保护膜粘贴在外延片正面。
8.根据权利要求6所述的降低易碎基底在半导体制程中破片率的方法，其特征在于：所述载片为蓝宝石载片。
9.根据权利要求6所述的降低易碎基底在半导体制程中破片率的方法，其特征在于：所述载片的厚度为0.3-0.7mm。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101017836A (zh) * 2006-02-09 2007-08-15 富士通株式会社 半导体器件及其制造方法
CN101533163A (zh) * 2008-03-10 2009-09-16 株式会社日立制作所 图像显示装置
CN102569352A (zh) * 2010-12-27 2012-07-11 同方光电科技有限公司 一种以蓝宝石为基板的氮化物基半导体装置
US20130316498A1 (en) * 2008-12-10 2013-11-28 Denso Corporation Method of manufacturing semiconductor device including insulated gate bipolar transistor and diode
CN103890908A (zh) * 2011-10-18 2014-06-25 富士电机株式会社 固相键合晶片的支承基板的剥离方法及半导体装置的制造方法
CN104979161A (zh) * 2014-04-04 2015-10-14 江苏中科君芯科技有限公司 半导体器件的制作方法及ti-igbt的制作方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101017836A (zh) * 2006-02-09 2007-08-15 富士通株式会社 半导体器件及其制造方法
CN101533163A (zh) * 2008-03-10 2009-09-16 株式会社日立制作所 图像显示装置
US20130316498A1 (en) * 2008-12-10 2013-11-28 Denso Corporation Method of manufacturing semiconductor device including insulated gate bipolar transistor and diode
CN102569352A (zh) * 2010-12-27 2012-07-11 同方光电科技有限公司 一种以蓝宝石为基板的氮化物基半导体装置
CN103890908A (zh) * 2011-10-18 2014-06-25 富士电机株式会社 固相键合晶片的支承基板的剥离方法及半导体装置的制造方法
CN104979161A (zh) * 2014-04-04 2015-10-14 江苏中科君芯科技有限公司 半导体器件的制作方法及ti-igbt的制作方法

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