CN106684033A - 形成连接件衬垫结构、互连结构的方法及其结构 - Google Patents

形成连接件衬垫结构、互连结构的方法及其结构 Download PDF

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Publication number
CN106684033A
CN106684033A CN201610600201.4A CN201610600201A CN106684033A CN 106684033 A CN106684033 A CN 106684033A CN 201610600201 A CN201610600201 A CN 201610600201A CN 106684033 A CN106684033 A CN 106684033A
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China
Prior art keywords
ball
connector
ubm
metalized pads
liners
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CN201610600201.4A
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English (en)
Inventor
张家纶
刘重希
林修任
陈宪伟
郑明达
陈威宇
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN106684033A publication Critical patent/CN106684033A/zh
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Abstract

本发明的实施例提供了形成连接件衬垫结构、互连结构的方法及其结构。在一些实施例中，形成连接件衬垫结构的方法包括形成球下金属化(UBM)衬垫，以及通过将UBM衬垫暴露于等离子体处理来增加UBM衬垫的表面粗糙度。聚合物材料形成在UBM衬垫的第一部分上方，而暴露UBM衬垫的第二部分。

Description

形成连接件衬垫结构、互连结构的方法及其结构
技术领域
本发明的实施例涉及半导体领域，更具体地涉及形成连接件衬垫结构、互连结构的方法及其结构。
背景技术
半导体器件用于各种电子应用中，诸如个人计算机、手机、数码相机和其他电子设备。通常通过以下步骤来制造半导体器件：在半导体衬底上方相继沉积绝缘或介电层、导电层和半导体材料层；以及使用光刻来图案化各个材料层，以在各个材料层上形成电路组件和元件。通常在单个半导体晶圆上制造数十或数百集成电路。通过沿着划割线锯切集成电路来切割单独的管芯。然后，通常以多芯片模块或以其他的封装类型将单独的管芯分别封装。
半导体工业通过不断减小最小化部件尺寸来继续提高各种电子组件(如，晶体管、二极管、电阻器、电容器等)的集成密度，这允许更多的组件集成到给定的面积中。在一些应用中，这些更小的电子组件还需要使用比过去的封装件更少面积的更小的封装件。
已经发展的用于半导体器件的一种类型的更小的封装件是晶圆级封装件(WLP)，其中集成电路被封装到通常包括再分布层(RDL)或后钝化互连件(PPI)的封装件中，该再分布层和后钝化互连件用作封装件的接触衬垫的多输出引线，从而使得可以在比集成电路的接触衬垫更大的间距上建立电接触。作为实例，WLP通常用于封装要求高速度、高密度和更多的引脚数的集成电路(IC)。
发明内容
本发明的实施例提供了一种形成连接件衬垫结构的方法，所述方法包括：形成球下金属化衬垫；通过将所述球下金属化衬垫暴露于等离子体处理来增加所述球下金属化衬垫的表面粗糙度；以及在所述球下金属化衬垫的第一部分上方形成聚合物材料，而暴露所述球下金属化衬垫的第二部分。
本发明的实施例还提供了一种形成互连结构的方法，所述方法包括：形成再分布层；在所述再分布层的一部分上方形成球下金属化衬垫，所述球下金属化衬垫的顶面包括第一表面粗糙度；将所述球下金属化衬垫的顶面的第一表面粗糙度改变至第二表面粗糙度，所述第二表面粗糙度大于所述第一表面粗糙度；在所述球下金属化衬垫的第一部分上方形成聚合物材料；在所述球下金属化衬垫的第二部分上方形成连接件；以及回流所述连接件的材料。
本发明的实施例还提供了一种互连结构，包括：再分布层；球下金属化衬垫，设置在所述再分布层的一部分上方，所述球下金属化衬垫的表面具有0.18μm至0.25μm的表面粗糙度；聚合物材料，设置在所述球下金属化衬垫的所述表面的第一部分上方；金属间化合物，设置在所述球下金属化衬垫的所述表面的第二部分上方；以及连接件，设置在所述金属间化合物上方。
本发明的实施例还提供了一种包括互连结构的封装的半导体器件，包括：再分布层；球下金属化衬垫，设置在所述再分布层的一部分上方，所述球下金属化衬垫的表面具有0.18μm至0.25μm的表面粗糙度；聚合物材料，设置在所述球下金属化衬垫的所述表面的第一部分上方；金属间化合物，设置在所述球下金属化衬垫的所述表面的第二部分上方；以及连接件，设置在所述金属间化合物上方；耦合至所述再分布层的集成电路管芯，其中，所述再分布层的一部分耦合至所述集成电路管芯的接触衬垫。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图7是根据本发明的一些实施例的封装的半导体器件的部分在各个阶段的截面图，其示出了形成连接件衬垫结构和互连结构的方法。
图8是根据一些实施例示出的用于连接件的材料的回流工艺的阶段的示图。
图9示出了根据一些实施例的图7中所示的连接件的顶视图，连接件包括设置在其周围边缘的助焊剂残留物。
图10示出了根据一些实施例的去除助焊剂残留物之后的图9中所示的连接件。
图11示出了根据一些实施例的图10所示的连接件的截面图。
图12示出了根据一些实施例的封装的半导体器件的部分的截面图，封装的半导体器件的部分包括图11中所示的多个连接件。
图13是根据一些实施例示出的封装的半导体器件的截面图。
图14示出了根据一些实施例的封装件上封装件(POP)器件的截面图。
图15是根据本发明的一些实施例示出的形成连接件衬垫结构的方法的流程图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对术语，以描述如图所示的一个元件或部件与另一元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作相应的解释。
本发明公开了形成连接件衬垫结构的方法、形成互连结构的方法、互连结构以及包括连接件衬垫结构和互连结构的封装的半导体器件。连接件衬垫结构和互连结构包括形成在连接件和球下金属化(UBM)衬垫之间的金属间化合物(IMC)，其中，IMC不形成在UBM衬垫的边缘与靠近UBM衬垫的边缘的聚合物材料之间，这提高了可靠性。公开了利用可以用于将一个衬底附着于另一个衬底的目的连接件衬垫结构和互连结构的一些实施例，其中衬底可以是管芯、晶圆、印刷电路板(PCB)、封装衬底等，从而允许管芯-管芯、晶圆-管芯、晶圆-晶圆、管芯或晶圆-印刷电路板、封装衬底类型的封装等。在通篇的各个示图和示出的实施例中，类似的参考数字用于表示类似的元件。
图1至图7是根据本发明的一些实施例的在各个阶段的封装的半导体器件的部分的截面图，其示出了形成连接件衬垫结构101和互连结构100的方法。首先参照图1，在一些实施例中，包括再分布层(RDL)106互连结构100形成在载体102上方。载体102包括用于封装工艺的作为封装一个或更多集成电路管芯152的平台的晶圆、胶带或其他类型的支撑件、衬底或器件。例如，在一些实施例中，在封装工艺之后，载体102稍后被去除。在一些实施例中，载体102包括被包裹设置在其上的集成电路管芯152(未在图1中示出；参见图12)，这将在本文中进一步描述。
RDL106包括形成在多个绝缘材料层104a中的多个导线108和导电通孔110。在图1至图7和图11中示出了一条导线108和一个导电通孔110。但是，多条导线108和多个导电通孔110形成在载体102上方。在一些实施例中，RDL106包括后钝化互连件(PPI)结构，其中，例如，导线108包括PPI线。RDL106也可以包括其他类型的引线。例如，在一些实施例中，RDL106在水平方向上为封装的半导体器件(参见图12中所示的封装的半导体器件150)提供电连接。
再次参照图1，多个绝缘材料层104a可以包括介电材料，诸如SiO2、SiN、等离子体增强的氧化物(PEOX)、等离子体增强的SiN(PE-SiN)、等离子体增强的未掺杂的硅酸盐玻璃(PE-USG)、聚苯并恶唑(PBO)、聚酰亚胺(PI)、环氧树脂、苯并环丁烯(BCB)、模塑料等或它们多层的组合。在一些实施例中，导线108和导电通孔110可以包括在绝缘材料层104a内使用镀敷工艺或其它沉积工艺形成的导电材料，诸如铜、铜合金，或其他金属或导电材料。使用一种或多种光刻工艺图案化多个绝缘材料层104a，可以包括在多个绝缘材料层104a上方形成光刻胶的层(未示出)并且将光刻胶暴露于从其上具有期望的图案的光刻掩模(未示出)反射或穿过该光刻掩模的光或能量。然后，显影光刻胶，并且去除光刻胶的暴露(或未暴露，取决于光刻胶是否是正性或负性光刻胶)部分以形成光刻胶的图案化的层。然后，在用于多个绝缘材料层104a的蚀刻工艺期间，将光刻胶的图案化的层用作蚀刻掩模。然后，使用灰化和/或蚀刻工艺去除光刻胶的层。
在一些实施例中，导线108和导电通孔110可以包括：使用溅射工艺形成的钛或其他的晶种材料的薄层，如包括大约2μm至大约3μm或更小的厚度；和电镀在钛层上方的铜、铜合金或其他金属的层。在其他的实施例中，导线108和导电通孔110可以包括多层结构，诸如涂覆有化学镀镍钯浸金(ENEPIG)的铜层，这包括镍层、镍层上的钯层和钯层上的金层。可以使用浸镀形成金层。导线108和导电通孔110还可以包括其他的材料、尺寸和形成方法。然后，多个绝缘材料层104a形成在导线108和导电通孔110周围。
在一些实施例中，可以衬底并且使用适合导线108和导电通孔110的材料的蚀刻化学物、使用光刻工艺图案化导线108和导电通孔110，这与所描述的用于多个绝缘材料层104a的光刻工艺相似。例如，可以形成为毯式涂层的导电材料并且然后使用光刻工艺蚀刻该导电材料以图案化导线108和导电通孔110。
多个绝缘材料层104b形成在导线108和导电通孔110和多个绝缘材料层104a上方。例如，多个绝缘材料层104b可以包括与所描述的用于多个绝缘材料层104a的材料相似的材料。在本发明的一些附图中，多个绝缘材料层104a和104b统称为绝缘材料104。使用光刻图案化多个绝缘材料层104b以暴露导线108的一部分。
在RDL106上方形成多个UBM衬垫112。图1至图7和图11示出了一个UBM衬垫112；但是，在载体102上方，多个UBM衬垫112形成在RDL106上方。多个UBM衬垫112电耦合并且机械耦合至RDL106的导线108。如图1所示，例如，多个UBM衬垫112的每个都可以耦合至一条导线108。例如，多个UBM衬垫112的每个也都可以耦合至一个导电通孔110(未示出)，或多个UBM衬垫112的每个也都可以耦合至一条导线108和/或一个导电通孔110。
例如，在一些实施例中，使用用于RDL106的导线108和导电通孔110的所描述的镀敷工艺形成包括铜、铜合金或其他金属的多个UBM衬垫112。例如，多个UBM衬垫112可以包括大约5μm至约7μm的厚度。多个UBM衬垫112还可以包括其他的材料、尺寸和形成方法。例如，多个UBM衬垫112形成在位于RDL106上方的多个绝缘材料层104b内。多个UBM衬垫112的每个都适合于具有耦合至其的连接件132(参见图5)。在一些实施例中，多个绝缘材料层104b的上部包括靠近多个UBM衬垫112的边缘136的凹槽113。例如，随后，靠近多个UBM衬垫112的边缘136的凹槽113将由聚合物材料120填充(见图3)。在其他实施例中，凹槽113不包括在靠近多个UBM衬垫112的边缘136的绝缘材料层104b中，这并未示出。
例如，在一些实施例中，使用晶圆级封装(WLP)工艺形成RDL106和多个UBM衬垫112。
再次参照图1，多个UBM衬垫112包括第一表面粗糙度116。在一些实施例中，例如，在形成多个UBM衬垫112之后，多个UBM衬垫112的第一表面粗糙度116具有小于约0.18μm的平均表面粗糙度或Ra。第一表面粗糙度116也可以包括其他数值。例如，在形成多个UBM衬垫112之后，多个UBM衬垫112的第一表面粗糙度116具有初始表面粗糙度。
根据一些实施例，多个UBM衬垫112的第一表面粗糙度116增加至更高水平的粗糙度或大幅增加的表面粗糙度。例如，在一些实施例中，多个UBM衬垫112的顶面的第一表面粗糙度116改变为第二表面粗糙度118(参见图2)，第二表面粗糙度118大于第一表面粗糙度116。
如图1所示，在一些实施例中，为了转变第一表面粗糙度116，多个UBM衬垫112暴露于等离子体处理114。例如，在一些实施例中，等离子体处理114包括在N2存在的情况下，持续时间为约100秒或更少并且室温在约50摄氏度至约100摄氏度。等离子体处理114也可以包括其他处理参数。如图2所示，在一些实施例中，通过等离子体处理114将多个UBM衬垫112的第一表面粗糙度116增加至第二表面粗糙度118。例如，等离子体处理114使UBM衬垫112表面粗糙。例如，在一些实施例中，第二表面粗糙度118具有约0.18μm至约0.25μm的平均表面粗糙度或Ra。例如，第二表面粗糙度118是足以提高后续沉积的聚合物材料120(参见图3)的附着力的数值。第二表面粗糙度118也可以是其他数值。作为一个实例，也可以使用其他方法，诸如通过改变镀敷工艺条件来改变多个UBM衬垫112的第一表面粗糙度116。
如图3所示，然后，聚合物材料120形成在绝缘材料104和多个UBM衬垫112的第一部分122上方。例如，可以使用毯式沉积工艺形成聚合物材料120。如图3中的120’处虚像(例如，在虚线中)所示，在一些实施例中，聚合物材料120基本上共形于并且基本上覆盖互连结构100的整个表面。例如，聚合物材料120包括绝缘材料，诸如PBO、PI、环氧树脂、BCB、模塑料和/或它们的组合。例如，聚合物材料120可以包括位于多个UBM衬垫112上方的约6μm至约8μm的厚度。聚合物材料120还可以包括其他的材料、尺寸和形成方法。
使用光刻工艺图案化聚合物材料120，将聚合物材料120留在互连结构100上方的预定位置中。图案化聚合物材料120以暴露多个UBM衬垫112的第二部分124。留下的聚合物材料120保持在多个UBM衬垫112的第一部分122上，并且使多个UBM衬垫112的第二部分124暴露。聚合物材料120设置在多个UBM衬垫112的第一部分122上方的多个UBM衬垫112的表面上方。在一些实施例中，多个UBM衬垫112的增加的粗糙度(即，第二表面粗糙度118)有利地增加了聚合物材料120和多个UBM衬垫112的第一部分122之间的附着力，从而形成聚合物材料120和多个UBM衬垫112的第一部分122的更坚固的界面。
例如，在一些实施例中，多个UBM衬垫112的第一部分122包括多个UBM衬垫112的边缘区域，并且多个UBM衬垫112的第二部分124包括多个UBM衬垫112的大致中心区域。多个UBM衬垫112的第一部分122和第二部分124也可以包括多个UBM衬垫112的其他区域。
在一些实施例中，形成图3中所示的连接件衬垫结构101的方法包括形成UBM衬垫112和将UBM衬垫112暴露于如图1所示的等离子体处理114。该方法包括在UBM衬垫112的第一部分122上方形成聚合物材料120但是使UBM衬垫112的第二部分124暴露。如图4和图5所示，在一些实施例中，形成连接件衬垫结构101的方法还可以包括在UBM衬垫112的暴露的第二部分124上方形成助焊剂128，这将在接下来进行描述。
如图4所示，在一些实施例中，提供助焊剂模板(stencil)126并且该助焊剂模板靠近互连结构100设置。例如，靠近多个UBM衬垫112的每个放置助焊剂模板126(即，助焊剂模板126中的开口)。靠近多个UBM衬垫112的暴露的第二部分124设置助焊剂模板126中的开口。例如，然后使用诸如将助焊剂128印刷在多个UBM衬垫112上方的方法施加助焊剂128。例如，可以使用平坦、光滑的刀片(诸如刮刀)在助焊剂模板126上方施加助焊剂128。也可以使用其他方法或工具施加助焊剂128。然后，去除助焊剂模板126。
在一些实施例中，助焊剂128包括低活性助焊剂，其在一些实施例中，适合于不损坏或不与多个UBM衬垫112和设置在多个UBM衬垫112的第一部分122上方的聚合物材料120的界面区域反应。助焊剂128不损坏或不与界面区域反应是因为低活性助焊剂128包括不与聚合物材料120反应的材料。在一些实施例中，助焊剂128包括适合于提高多个UBM衬垫112上方的后续形成的连接件132(参见图5)的连接的材料。例如，在一些实施例中，助焊剂128通过使UBM衬垫112表面上的本征氧化物层脱氧来提高连接件132的连接。例如，在一些实施例中，如果存在氧化物，助焊剂128包括适合于帮助并且促进氧化物从多个UBM衬垫112的表面去除的材料。例如，在一些实施例中，在助焊剂128形成在多个UBM衬垫112的第二部分124上方之后，助焊剂128可以包括约10μm或更小的厚度。助焊剂128也可以包括其它性能、材料类型和尺寸。
如图5所示，在施加助焊剂128之前、期间和/或之后，氧化物层134可以形成在多个UMB衬垫112的第二部分124的顶面上方。例如，由于多个UMB衬垫112的暴露的顶面的氧化，所以可以形成氧化物层134。例如，氧化物层134可以包括多个UMB衬垫112和氧的材料，诸如CuO2。例如，在一些实施例中，氧化物层134可以包括本征氧化物。例如，氧化物层134可以包括几μm的厚度，诸如约300埃至约1μm或更小。氧化物层134也可以包括其他材料和尺寸。在一些实施例中，在随后的用于连接件132的回流工艺期间，助焊剂128有利于帮助去除氧化物层134。在一些实施例中，不形成氧化物层134。
在如图4所示应用助焊剂128之后，如图5所示，在一些实施例中，模板130靠近互连结构100放置。例如，在一些实施例中，模板130包括焊料球模板。模板130也可以包括其他类型的模板。例如，模板130靠近多个UBM衬垫112放置。然后，将连接件132的材料施加至(即，刷上或其他的方法)位于多个UBM衬垫112上方的助焊剂128上，穿过模板130中的开口，在多个UBM衬垫112的每个上方形成连接件132。如图6所示，在形成连接件132的材料后，去除模板130。作为另一实例，在一些实施例中，模板130不用于附接连接件132的材料。例如，在一些实施例中，可以使用球安装工艺附接连接件132。作为实例，也可以使用旋涂工艺、焊浴或焊料膏印刷施加连接件132的材料。也可以使用其他方法形成连接件132的材料并且可以包括其他材料。
连接件132的材料包括诸如焊料的共晶材料。本文使用的词语“焊料”包括铅基焊料和无铅焊料两者，诸如：用于铅基焊料的Pb-Sn组分；包括InSb的无铅焊料；锡、银和铜(“SAC”)组分；以及具有公共熔点并且在电应用中形成导电焊料连接的其他的共晶材料。作为实例，对于无铅焊料来说，可以使用具有不同组分的SAC焊料，诸如SAC 105(Sn 98.5％、Ag 1.0％、Cu 0.5％)、SAC 305和SAC 405。诸如焊料球的无铅导电材料也可以由SnCu化合物形成，而不使用银(Ag)。无铅焊料连接件也可以包括锡和银、Sn-Ag，而不使用铜。
在如图5所示形成连接件132的材料之后的一些实施例中，多个UBM衬垫112上方的连接件132在多个UBM衬垫112的第二部分124的大致中心区域耦合。也如图5所示，在形成连接件132的材料之后的一些实施例中，连接件132的材料不耦合至多个UBM衬垫112的第二部分124的边缘区域。
然后，加热连接件132的材料至预定的温度，例如，至连接件132的材料的共晶材料的熔点，诸如约150摄氏度至约270摄氏度，以回流连接件132的材料。如图6所示，可以通过加热互连结构100来加热连接件132材料，这导致助焊剂128与氧化物层134(如果存在)和多个UBM衬垫112的顶面反应，从而造成氧化物层134的去除。如图7所示，持续加热互连结构100直到到达互连件132的材料的共晶材料的熔点，从而导致连接件132的材料的回流和连接件132至多个UBM衬垫112的每个的电耦合和机械耦合。
作为实例，在一些实施例中，连接件132可以包括焊料凸块或焊料球。在一些实施例中，连接件132包括具有为部分球体形状的导电球。例如，在一些实施例中，连接件132可以具有约170μm或更少的高度。连接件132也可以包括其他尺寸和形状。例如，连接件132也可以包括非球体导电连接件。连接件132可以包括在以连接件132作为栅的阵列中，称为“球栅阵列”或“BGA”。连接件132也可以布置为其他形状。
连接件132的材料的回流提高连接件132至UBM衬垫112的附着力并且更完全地将连接件132附接至多个UBM衬垫112。如图7所示，在一些实施例中，回流工艺导致连接件132的材料在UBM衬垫112的第二部分124的中心区域和边缘区域上方耦合。也如图7所示，在一些实施例中，助焊剂128的包括助焊剂残留物128’的部分在回流工艺之后留在连接件132的边缘周围。根据一些实施例，然后使用清洗工艺去除助焊剂残留物128’，这将在本文进一步描述。
图7也示出了在连接件132的共晶材料的回流期间，形成在连接件132和多个UBM衬垫112之间的IMC140。IMC140设置在多个UBM衬垫112的第二部分124上方的多个UBM衬垫112的表面上方。根据本发明的一些实施例，由于多个UBM衬垫112的顶面的增加的第二表面粗糙度118，所以在一些实施例中，IMC140有利地不形成在多个UBM衬垫112的第一部分122和聚合物材料120之间。例如，在一些实施例中，使用具有低活性助焊剂的助焊剂128还有助于减少或防止IMC140的一部分形成在多个UBM衬垫112的第一部分122上方、形成在聚合物材料120和多个UBM衬垫112的第一部分122之间。例如，在一些实施例中，连接件132的材料的回流不包括在多个UBM衬垫112的第一部分122和聚合物材料120之间形成IMC140。
例如，在一些实施例中，IMC140可以包括CuSn，其中连接件132包括Sn。作为实例，在一些实施例中，IMC140可以包括CuSn、Ag3Sn、Cu3Sn、Cu6Sn5。作为实例，在一些实施例中，IMC140可以包括约0.5μm至约2μm的厚度，或在一些实施例中约0.75μm的厚度。例如，IMC140包括足以提高连接件132至多个UBM衬垫112的电连接的材料和尺寸。
图8是根据一些实施例示出的用于连接件132的材料的回流工艺的一些阶段的示图。以秒为单位的时间(秒)示出在图的x轴上，并且以摄氏度为单位的温度示出在图的y轴上。介于零和约60秒之间的时间段包括初始区域141，其中，开始加热连接件132的材料。介于约60秒和130秒之间的时间段包括浸润(soaking)区域142。作为实例，在一些实施例中，浸润区域142的持续时间包括约70秒。随着时间温度增加，连接件132在约240秒加或减20秒处到达停滞(dwell，或称为“间歇”)区域144，在该点处连接件132的共晶材料回流。作为一个实例，在一些实施例中，停滞区域144的持续时间包括约50秒。例如，停滞区域144包括峰值温度146，在此处连接件132的材料熔融。在实例中示出，峰值温度146包括约220摄氏度。在一些实施例中，包括峰值温度146的熔融温度可以具有约200摄氏度至约250摄氏度，作为另一个实例，例如，这取决于用于多个连接件132的材料。峰值温度146以及浸润区域142和停滞区域144的持续时间也可以包括其它数值。在一些实施例中，然后，降低温度，并且连接件132的共晶材料重新固化，将连接件132机械地耦合或电耦合至多个UBM衬垫112的基本上整个暴露的顶面，例如，多个UBM衬垫112的第二部分124上方、IMC140上方。
在回流工艺的浸润区域142期间，为助焊剂128使用低活性助焊剂材料可以防止聚合物材料120和多个UBM衬垫112的第一部分122之间的界面损坏。因此，在一些实施例中，在回流工艺的停滞区域144期间，防止连接件132的材料迁移至聚合物材料120和多个UBM衬垫112的第一部分122之间的界面中。
图9示出了根据一些实施例的附接至图7中所示的多个UBM衬垫112的一个的连接件132顶视图，其包括设置在连接件132的边缘周围的助焊剂残留物128’。UBM衬垫112的边缘136延伸超过连接件132和助焊剂残留物128’。UBM衬垫112的第一部分122朝着UBM衬垫112的边缘136延伸超过第二部分124。根据本发明的一些实施例，使用清洗工艺清洗互连结构100以去除助焊剂残留物128’。例如，在一些实施例中，使用助焊剂清洗机器清洗助焊剂残留物128’。也可以使用其他器件和方法去除助焊剂残留物128’。
图10示出了根据一些实施例的使用清洗工艺去除助焊剂残留物128’之后的图9中所示的连接件132的顶视图。图11是根据一些实施例的图10所示的连接件132的截面图。在用于连接件132的回流工艺期间，通过助焊剂128去除氧化物层134。增加的第二表面粗糙度118提高聚合物材料120和UBM衬垫112的第一部分122之间的附着力，从而使得IMC140有利地不形成在聚合物材料120和UBM衬垫112的第一部分122之间，这提高了可靠性。
图12示出了根据一些实施例的封装的半导体器件150的部分的截面图，该封装的半导体器件包括图11中所示的多个连接件132。互连结构100包括耦合至多个UBM衬垫112的多个连接件132。IMC140形成在多个UBM衬垫112的第二部分124和多个连接件132之间。IMC140有利地不形成在聚合物材料120和多个UBM衬垫120的第一部分122之间。
图12也示出了根据本发明的一些实施例的封装的半导体器件150的一些附加的元件。封装的半导体器件150包括耦合至集成电路管芯152的互连结构100和设置在集成电路管芯152周围和互连结构100下方的成型材料154。在一些实施例中，封装的半导体器件150包括多输出结构。例如，互连结构100的导电引线(如，诸如RDL106的导线108和导电通孔110)的间隔距离可以比集成电路管芯152的导电引线的间隔距离更远。同样地，互连结构100的UBM衬垫112的所占面积(footprint)可以比集成电路管芯152的接触衬垫153所占面积大。在一些实施例中，封装的半导体器件150包括集成多输出(InFO)器件或WLP器件。封装的半导体器件150也可以包括其他类型的封装件。
在一些实施例中，为了封装集成电路管芯152，在提供图1中所示的载体102之后，在互连结构100形成在载体102上方之前，提供集成电路管芯152并且将其耦合至载体102。集成电路管芯152可以包括具有形成在其中或其上的电路的衬底。例如，衬底可以包括掺杂或未掺杂的块状硅、或绝缘体上半导体(SOI)衬底的有源层。集成电路管芯152的衬底的电路可以是适合于特定应用的任何类型的电路。集成电路管芯152可以包括逻辑器件、存储器、处理器或其他类型的器件。作为其他的实例，形成在集成电路管芯152的衬底内或上的电路可以包括各个N型金属氧化物半导体(NMOS)和/或P型金属氧化物半导体(PMOS)器件，诸如晶体管、电容器、电阻器、二极管、光电二极管、熔丝等，将其互连以执行一种或多种功能。该功能可以包括存储结构、逻辑结构、处理结构、传感器、放大器、配电、输入/输出电路等。本领域的普通技术人员将理解，为了示例性目的提供以上实例来进一步解释一些示例性实施例的应用并且不意味着以任何方式限制本发明。其他的电路可以适当地用于给定的应用。通常通过在半导体晶圆上形成多个集成电路管芯15制造集成电路管芯152，并且沿着划割线分割单独的集成电路管芯152。
在一些实施例中，用于集成电路管芯152的封装工艺包括提供载体102和将一个或更多集成电路管芯152附接至载体102。例如，在一些实施例中，在封装多个集成电路管芯152之后，随后去除载体102。
在一些实施例中，贯通孔(未在图12中示出；参见图13中的贯通孔156)也形成在载体102上方。例如，贯通孔156可以镀敷在形成在载体102上的晶种层(未示出)上。在一些实施例中，不包括贯通孔156。在一些实施例中，在多个集成电路管芯152耦合至载体102之前或之后，可以通过镀敷、光刻和减薄蚀刻工艺或其他的方法将多个贯通孔156形成在载体102上方。可以使用电镀工艺，通过在载体102上方沉积晶种层以及在晶种层上方形成用于贯通孔156的具有期望的图案的图案化的掩模来形成多个贯通孔156。穿过图案化的掩模将贯通孔156镀敷至载体102上，并且然后去除图案化的掩模。还去除晶种层的暴露部分。贯通孔156可以包括铜、铜合金或其他的金属或导电材料。例如，数十或数百个贯通孔156可以包括在用于每一个集成电路管芯152的封装件或封装在一起的集成电路管芯152的组的封装件中。在一些实施例中，多个贯通孔156在垂直方向上为封装的半导体器件150提供电连接。例如，可以设置多个贯通孔156中的每一个，使得它们耦合至互连结构100的导电部分，诸如随后形成的RDL106的导线108和/或导电通孔110。
在一些实施例中，多个集成电路管芯152耦合至多个贯通孔156的一些贯通孔之间的载体102。图中示出了一个集成电路管芯152；在一些实施例中，多个集成电路管芯152耦合至载体102并且同时封装。在一些实施例中，可以使用设置在集成电路管芯152的底面上的管芯附着膜(DAF)(未示出)来将多个集成电路管芯152耦合至载体102。例如，可以使用取放机器或手动将多个集成电路管芯152放置在载体102上。之后，沿着划割线(即，封装件或互连结构100的)分割集成电路管芯152或两个或多个集成电路管芯152，以形成多个封装的半导体器件150。如图12所示，在一些实施例中，集成电路管芯152包括形成在其顶面上的接触衬垫153，其用于电连接至RDL 106的一部分，诸如导电通孔110。
然后，在其中包括贯通孔156的实施例中，成型材料154形成在载体102上方、集成电路管芯152和贯通孔156上方。作为实例，成型材料154可以包括由绝缘材料组成的模塑料，诸如环氧树脂、填充材料、应力释放剂(SRA)、附着力促进剂、其他的材料或它们的组合。在一些实施例中，成型材料154可以包括液体或胶体，并且当施加时，使其在被同时封装的多个集成电路管芯152之间并且围绕贯通孔156流动。然后固化成型材料154或允许其干燥以形成固体。在一些实施例中，可以在成型材料154的固化工艺和等离子体处理工艺期间应用模塑料夹(molding compound clamp)。作为实例，在一些实施例中，随着沉积，成型材料154在多个集成电路管芯152和贯通孔156的顶面上方延伸，并且在施加成型材料154之后，使用诸如化学机械抛光(CMP)工艺、研磨工艺、蚀刻工艺或它们的组合的平坦化工艺来去除成型材料154的顶部。也可以使用其他的方法来平坦化成型材料154。也可以在用于成型材料154的平坦化工艺期间去除集成电路管芯152和/或贯通孔156的顶部。在一些实施例中，可以控制施加的成型材料154的数量使得暴露集成电路管芯152和贯通孔156的顶面。也可以使用其他的方法来形成成型材料154。
然后，互连结构100可以形成在平坦化的成型材料154、集成电路管芯152和贯通孔156上方。在一些实施例中，互连结构100包括RDL106和/或PPI。互连结构100可以包括一个、两个或几个导线层和导电通孔层。互连结构100的一些导线108和/或导电通孔110耦合至集成电路管芯152的接触衬垫153。
在一些实施例中，然后，去除载体102晶圆。在一些实施例中，然后分割多个封装的半导体器件150以形成图12示出的封装的半导体器件150。例如，在一些实施例中，可以使用锯或激光(未示出)来分割封装的半导体器件150，锯可以包括具有金刚石或其他材料的刀片。一个或更多载体102可以用于封装半导体器件。
图13是根据一些实施例的封装的半导体器件150的截面图。例如，图13中示出的封装的半导体器件150已经从图12中示出的封装的半导体器件150的视图颠倒过来。互连结构100包括封装的半导体器件150的第一互连结构100，并且第二互连结构100’已经形成在封装的半导体器件150的与第一互连结构100相对的侧上。在一些实施例中，多个连接件132’耦合至封装的半导体器件150的第二互连结构100’。
在一些实施例中，第二互连结构100’可以包括与用于第一互连结构100(即，图11所示的互连结构100)所描述的元件相似的元件。例如，第二互连结构100’可以包括具有多个导线108’和导电通孔108’的RDL106’。包括具有增加的第二表面粗糙度的表面的UBM衬垫112’可以耦合至一些导线108’和/或导电通孔110’。连接件132’可耦合至每个UBM衬垫112’。在一些实施例中，多个连接件132’未耦合至第二互连结构100’。在一些实施例中，第二互连结构100’可以不包括具增加的第二表面粗糙度的UBM衬垫112’。
例如，多个连接件132和/或多个连接件132’可以用于将封装的半导体器件150耦合至另一器件、另一封装的半导体器件150，或至一个板或端应用中的其它目标上。作为另一实例，多个连接件132和/或多个连接件132’可以用于将封装的半导体器件150的第一互连结构100或第二互连结构100’分别耦合至封装的集成电路。
在一些实施例中，为了形成第二互连结构100’，之前描述的载体102可以包括第一载体102，并且在第一互连结构100形成之后，第二载体(未示出)可以附接至第一互连结构100。去除第一载体102，并且第二互连结构100’形成在集成电路管芯152、贯通孔156和成型材料154的第二侧上方。然后，去除第二载体，并且然后分割多个封装的半导体器件150。例如，在一些实施例中，第一互连结构100和第二互连结构100’在水平方向上为多个封装的半导体器件150提供电连接。在一些实施例中，对于封装的半导体器件150来说，第二互连结构100’可以包括背侧布线，并且第一互连结构100可以包括前侧布线，反之亦然，例如，相对于集成电路管芯152。
本文中描述的使用一个或更多载体102来封装半导体器件的方法仅仅是实例：可以使用封装工艺的不同方法或方法的不同顺序来封装集成电路管芯152。
例如，在一些实施例中，其中包括第二互连结构100’，另一封装的集成电路或半导体器件可以耦合至封装的半导体器件150的第一互连结构100和/或第二互连结构100’。
例如，图14是根据一些实施例的封装件上封装件(POP)器件170的截面图。例如，POP器件170包括从图12中所示的视图颠倒的封装的半导体器件150。POP器件170包括图13中所示的封装的半导体器件150，其已经使用耦合至第二互连结构100’的多个连接件132’来耦合至另一封装的半导体器件160。
在一些实施例中，为了制造POP器件170，在分割图13示出的封装的半导体器件150之前，并且在形成第二互连结构110’之后，提供多个第二封装的半导体器件160，并且使用多个连接件132’将多个第二封装的半导体器件160的每个都耦合至一个第一封装的半导体器件150。通过诸如由操作人员或技术人员手动、使用诸如取放机器的自动化机器或其他方法的方法将多个第二封装的半导体器件160耦合至未分割的多个第一封装的半导体器件150。加热连接件132’的共晶材料，回流共晶材料，并且在共晶材料冷却之后，第二封装的半导体器件160电耦合和机械耦合至第一封装的半导体器件150。然后，分割多个第一封装的半导体器件150，以形成多个POP器件170，其中一个在图14中示出。
第二封装的半导体器件160可以包括衬底162，该衬底包括设置在其上的多个接触衬垫。例如，多个接触衬垫设置在图14中衬底162的顶面和底面上。在一些实施例中，衬底162可以包括形成在其上的并且为第二封装的半导体器件160提供水平连接的一个或更多互连结构(未示出)。衬底162还可以包括形成在其中的多个贯通孔(也未示出)。一个或更多集成电路管芯152b可以耦合至衬底162的顶面。例如，在图14中所示的一些实施例中，第二封装的半导体器件160包括两个垂直堆叠的集成电路管芯152b。在一些实施例中，两个或更多的集成电路管芯152b还可以在第二封装的半导体器件160中水平封装在一起，这并未示出。
在图14中示出的一些实施例中，通过接合引线164将集成电路管芯152b耦合至设置在衬底162的顶面上的多个接触衬垫。在一些实施例中，接合引线164和衬底162中的贯通孔(如果包括)为第二封装的半导体器件160提供垂直电连接。成型材料166设置在集成电路管芯152b、接合引线164和衬底162上方。例如，成型材料166可以包括与用于第一封装的半导体器件150的成型材料154的所描述的材料和形成方法类似的材料和形成方法。
例如，在一些实施例中，第二封装的半导体器件160的一个集成电路管芯或一些集成电路管芯152b可以包括存储器件，诸如动态随机存取存储器(DRAM)器件。集成电路管芯152b也可以包括其他类型的存储器件和/或其他类型的器件。如图14所示，集成电路管芯152b可以封装在引线接合类型的封装件中，或集成电路管芯152b可以封装在其他类型的封装件中并且使用其他类型的封装技术。第二封装的半导体器件160也可以包括与第一封装的半导体器件150相似或相同类型的封装件。例如，第二封装的半导体器件160可以包括具有增加的第二表面粗糙度118的UBM衬垫112。
可以使用设置在POP器件170的底面上的多个连接件132来将POP器件170耦合至其他的器件或物体，例如，多个连接件使用表面安装技术(SMT)工艺耦合至互连结构100。如图14所示，在一些实施例中，POP器件170可以耦合至衬底或PCB182，以形成衬底上的晶圆上芯片(CoWoS)器件180。
在一些实施例中，第一封装的半导体器件150的集成电路管芯152a可以包括逻辑器件或处理器，并且第一封装的半导体器件150的互连结构100包括多输出引线，例如，在一些实施例中，其中，第二集成电路管芯152b包括存储器件，诸如DRAM器件，从而形成InFOPOP器件170。第一集成电路管芯152a、第二集成电路管芯152b、第一封装的半导体器件150和第二封装的半导体器件160还可以包括其他类型的器件，以及本文中描述的包括具有增加的第二表面粗糙度118的多个UBM衬垫112的连接件衬垫结构101也可以在其他类型的应用中实施。
图15是根据本发明的一些实施例的形成连接件衬垫结构101(参见图3)的方法的流程图190。在步骤192中，也如图1所示，形成UBM衬垫112。在步骤194中，如图1和图2所示，UBM衬垫112暴露于等离子体处理114。在步骤196中，如图3所示，聚合物材料120形成在UBM衬垫112的第一部分122上方，而暴露UBM衬垫112的第二部分124。
在一些应用中，可以有利地实施本发明的一些实施例，并且当用于POP器件时，本发明的一些实施例尤其具有益处。作为实例，在一些实施例中，封装的半导体器件可以包括POP器件170、芯片上系统(SOC)器件、CoWoS器件或其他类型的三维集成电路(3DIC)。作为其他的实例，本发明的一些实施例也是有益的并且可以在包括互连结构和多输出结构的其他类型的器件中实施本发明的实施例。例如，一些实施例在球安装应用中和/或连接件安装应用中也具有益处。
本发明的一些实施例包括连接件衬垫结构和互连结构及其形成方法，该连接件衬垫结构和互连结构包括具有由等离子体处理导致的增加的第二表面粗糙度的UBM衬垫。其它实施例包括封装的半导体器件及其封装方法，该封装的半导体器件包括连接件衬垫结构和互连结构，该连接件衬垫结构和互连结构包括具有由等离子体处理导致的增加的第二表面粗糙度的UBM衬垫。
本发明的一些实施例的益处包括提供提高封装器件的连接件衬垫结构和互连结构的可靠性能的低成本方法。UBM衬垫表面的等离子体处理和低活性助焊剂用于防止或减小IMC渗入至聚合物材料和UBM衬垫表面界面。在一些实施例中，等离子体处理使UBM衬垫表面粗糙，其可以提高附着力并且防止或减小聚合物材料和UBM衬垫界面区域之间的分层。例如，在一些实施例中，聚合物材料和UBM衬垫之间的界面更加坚固致使减少可靠性测试失败问题。
在一些实施例中，实现具有多输出结构的改进的可靠性互连结构。例如，在一些实施例中，可以降低用于连接件衬垫结构和互连结构的各个材料层的处理成本。通过实施本发明的一些实施例，可以有利地实现具有高产量的(如，连接件的)球安装工艺。此外，容易在现有的互连结构和封装工艺流程和结构中实施本文所描述的方法和结构。
在一些实施例中，形成连接件衬垫结构的方法包括形成UBM衬垫和通过将UBM衬垫暴露于等离子体处理来增加UBM衬垫的表面粗糙度。聚合物材料形成在UBM衬垫的第一部分上方，而暴露UBM衬垫的第二部分。
在一些实施例中，形成互连结构的方法包括形成RDL，和在RDL的一部分上方形成UBM衬垫。UBM衬垫的顶面具有第一表面粗糙度。该方法包括改变UBM衬垫的顶面的第一表面粗糙度至第二表面粗糙度，第二表面粗糙度大于第一表面粗糙度。聚合物材料形成在UBM衬垫的第一部分上方。连接件形成在UBM衬垫的第二部分上方。回流连接件的材料。
在一些实施例中，互连结构包括RDL和设置在RDL的一部分上方的UBM衬垫。UBM衬垫的表面具有约0.18μm到约0.25μm的表面粗糙度。聚合物材料设置在UBM衬垫的表面的第一部分上方，并且IMC设置在UBM衬垫的表面的第二部分上方。连接件设置在IMC上方。
本发明的实施例提供了一种形成连接件衬垫结构的方法，所述方法包括：形成球下金属化衬垫；通过将所述球下金属化衬垫暴露于等离子体处理来增加所述球下金属化衬垫的表面粗糙度；以及在所述球下金属化衬垫的第一部分上方形成聚合物材料，而暴露所述球下金属化衬垫的第二部分。
根据本发明的一个实施例，其中，所述第一部分包括所述球下金属化衬垫的边缘区域。
根据本发明的一个实施例，其中，所述第二部分包括所述球下金属化衬垫的中心区域。
根据本发明的一个实施例，其中，形成所述聚合物材料包括：形成选自由聚苯并恶唑、聚酰亚胺、环氧树脂、苯并环丁烯、模塑料和它们的组合组成的组中的材料。
根据本发明的一个实施例，其中，形成所述球下金属化衬垫包括：形成铜或铜合金。
本发明的实施例还提供了一种形成互连结构的方法，所述方法包括：形成再分布层；在所述再分布层的一部分上方形成球下金属化衬垫，所述球下金属化衬垫的顶面包括第一表面粗糙度；将所述球下金属化衬垫的顶面的第一表面粗糙度改变至第二表面粗糙度，所述第二表面粗糙度大于所述第一表面粗糙度；在所述球下金属化衬垫的第一部分上方形成聚合物材料；在所述球下金属化衬垫的第二部分上方形成连接件；以及回流所述连接件的材料。
根据本发明的一个实施例，其中，回流所述连接件的材料包括：在所述连接件和所述球下金属化衬垫的第二部分之间形成金属间化合物。
根据本发明的一个实施例，其中，形成所述金属间化合物包括：形成厚度为0.5μm至2μm的金属间化合物。
根据本发明的一个实施例，其中，回流所述连接件的材料不包括：在所述球下金属化衬垫的所述第一部分和所述聚合物材料之间形成所述金属间化合物。
根据本发明的一个实施例，其中，改变所述第一表面粗糙度包括：将所述球下金属化衬垫暴露于等离子体处理。
根据本发明的一个实施例，其中，所述第二表面粗糙度具有的平均表面粗糙度为0.18μm至0.25μm。
根据本发明的一个实施例，其中，所述第一表面粗糙度具有的平均表面粗糙度为小于0.18μm。
根据本发明的一个实施例，其中，形成所述连接件包括：靠近所述球下金属化衬垫放置模板、刷上所述连接件的材料、以及去除所述模板。
本发明的实施例还提供了一种互连结构，包括：再分布层；球下金属化衬垫，设置在所述再分布层的一部分上方，所述球下金属化衬垫的表面具有0.18μm至0.25μm的表面粗糙度；聚合物材料，设置在所述球下金属化衬垫的所述表面的第一部分上方；金属间化合物，设置在所述球下金属化衬垫的所述表面的第二部分上方；以及连接件，设置在所述金属间化合物上方。
根据本发明的一个实施例，其中，所述连接件包括Sn。
根据本发明的一个实施例，其中，所述金属间化合物包括CuSn。
本发明的实施例还提供了一种包括互连结构的封装的半导体器件，包括：再分布层；球下金属化衬垫，设置在所述再分布层的一部分上方，所述球下金属化衬垫的表面具有0.18μm至0.25μm的表面粗糙度；聚合物材料，设置在所述球下金属化衬垫的所述表面的第一部分上方；金属间化合物，设置在所述球下金属化衬垫的所述表面的第二部分上方；以及连接件，设置在所述金属间化合物上方；耦合至所述再分布层的集成电路管芯，其中，所述再分布层的一部分耦合至所述集成电路管芯的接触衬垫。
根据本发明的一个实施例，其中，所述封装的半导体器件还包括成型材料和多个贯通孔，所述成型材料设置在所述集成电路管芯周围和所述互连结构上方，并且所述多个贯通孔设置在所述成型材料内。
根据本发明的一个实施例，其中，所述集成电路管芯包括第一侧和与所述第一侧相对的第二侧，其中，所述互连结构包括靠近所述集成电路管芯的第一侧设置的第一互连结构，并且其中，所述封装的半导体器件包括靠近所述集成电路管芯的所述第二侧设置的第二互连结构。
根据本发明的一个实施例，半导体器件还包括：封装的集成电路，所述封装的集成电路耦合至所述第一互连结构或所述第二互连结构。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种形成连接件衬垫结构的方法，所述方法包括：
形成球下金属化衬垫；
通过将所述球下金属化衬垫暴露于等离子体处理来增加所述球下金属化衬垫的表面粗糙度；以及
在所述球下金属化衬垫的第一部分上方形成聚合物材料，而暴露所述球下金属化衬垫的第二部分。
2.根据权利要求1所述的方法，其中，所述第一部分包括所述球下金属化衬垫的边缘区域。
3.根据权利要求1所述的方法，其中，所述第二部分包括所述球下金属化衬垫的中心区域。
4.根据权利要求1所述的方法，其中，形成所述聚合物材料包括：形成选自由聚苯并恶唑、聚酰亚胺、环氧树脂、苯并环丁烯、模塑料和它们的组合组成的组中的材料。
5.根据权利要求1所述的方法，其中，形成所述球下金属化衬垫包括：形成铜或铜合金。
6.一种形成互连结构的方法，所述方法包括：
形成再分布层；
在所述再分布层的一部分上方形成球下金属化衬垫，所述球下金属化衬垫的顶面包括第一表面粗糙度；
将所述球下金属化衬垫的顶面的第一表面粗糙度改变至第二表面粗糙度，所述第二表面粗糙度大于所述第一表面粗糙度；
在所述球下金属化衬垫的第一部分上方形成聚合物材料；
在所述球下金属化衬垫的第二部分上方形成连接件；以及
回流所述连接件的材料。
7.根据权利要求6所述的方法，其中，回流所述连接件的材料包括：在所述连接件和所述球下金属化衬垫的第二部分之间形成金属间化合物。
8.根据权利要求7所述的方法，其中，形成所述金属间化合物包括：形成厚度为0.5μm至2μm的金属间化合物。
9.一种互连结构，包括：
再分布层；
球下金属化衬垫，设置在所述再分布层的一部分上方，所述球下金属化衬垫的表面具有0.18μm至0.25μm的表面粗糙度；
聚合物材料，设置在所述球下金属化衬垫的所述表面的第一部分上方；
金属间化合物，设置在所述球下金属化衬垫的所述表面的第二部分上方；以及
连接件，设置在所述金属间化合物上方。
10.一种包括根据权利要求9所述的互连结构的封装的半导体器件，还包括：耦合至所述再分布层的集成电路管芯，其中，所述再分布层的一部分耦合至所述集成电路管芯的接触衬垫。
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