CN106653758A - 快闪存储器的制作方法 - Google Patents

快闪存储器的制作方法 Download PDF

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CN106653758A
CN106653758A CN201510714032.2A CN201510714032A CN106653758A CN 106653758 A CN106653758 A CN 106653758A CN 201510714032 A CN201510714032 A CN 201510714032A CN 106653758 A CN106653758 A CN 106653758A
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grid
transistor
memory transistor
functional layer
memory
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CN106653758B (zh
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陈亮
仇圣棻
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Beijing Corp
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Priority to EP16194585.2A priority patent/EP3163606A1/en
Priority to US15/331,467 priority patent/US10418370B2/en
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Abstract

一种快闪存储器的制作方法，首先在存储晶体管栅极堆叠结构外表面及其间的基底表面采用原子层沉积法形成功能层，该功能层厚度均匀，且不会填满间距较小的存储晶体管栅极堆叠结构之间的间隙；后对功能层进行处理使其表面粗糙易吸水；处理后的功能层吸水后，在功能层表面利用化学气相沉积工艺形成介质层，化学气相沉积工艺为高温工艺，在高温下，功能层内吸收的水分蒸发形成向上气流，阻止介质层沉积。该填充性能较差的填充工艺在间距较小的存储晶体管的栅极堆叠结构之间形成了空气隙，空气隙的介电常数小于二氧化硅介质层的介电常数，因而能降低读、写、擦除过程中产生的寄生电容，避免相邻存储晶体管之间相互干扰。

Description

快闪存储器的制作方法
技术领域
本发明涉及半导体技术领域，尤其涉及一种快闪存储器的制作方法。
背景技术
在目前的半导体产业中，集成电路产品主要可分为三大类型：模拟电路、数字电路和数/模混合电路，其中存储器件是数字电路中的一个重要类型。近年来，在存储器件中，快闪存储器(闪存，flash memory)的发展尤为迅速。闪存的主要特点是在不加电的情况下能长期保持存储的信息，因此被广泛应用于各种急需要存储的数据不会因电源中断而消失，有需要重复读写数据的存储器。而且，闪存具有集成度高、存取速度快、易于擦除和重写等优点，因而在微机电系统、自动化控制等多项领域得到了广泛的应用。
随着高密度闪存技术的发展，各类随身电子设备的性能得到了提升，例如以闪存作为数码相机、笔记本电脑或平板电脑等电子设备中的存储器件。因此，降低闪存单元的尺寸，并以此降低闪存存储器的成本是技术发展的方向之一。
然而，随着闪存单元的尺寸减小，相邻闪存单元之间的间距变小，两者之间在读、写、擦除时易出现干扰，这造成闪存的性能不可靠。
发明内容
本发明解决的问题是如何避免相邻闪存单元在读、写、擦除时出现干扰，提高闪存性能可靠性。
为解决上述问题，本发明提供一种快闪存储器的制作方法，包括：
提供基底，所述基底至少包括存储单元区，所述存储单元区具有存储晶体管阵列以及选择晶体管，所述选择晶体管用于选择所述存储晶体管阵列中某一行或某一列存储晶体管；所述存储晶体管阵列包括多个分立的栅极堆叠结构以及位于所述栅极堆叠结构两侧的源漏区，所述选择晶体管包括栅极结构以及位于所述栅极结构两侧的源漏区；其中，所述存储晶体管的栅极堆叠结构之间的间隙小于所述存储晶体管的栅极堆叠结构与所述选择晶体管的栅极结构之间的间隙；
原子层沉积法在所述存储晶体管阵列的多个栅极堆叠结构外表面、多个栅极堆叠结构之间的基底表面、选择晶体管的栅极结构外表面、以及存储晶体管的栅极堆叠结构与选择晶体管的栅极结构之间的基底表面形成功能层；
对所述功能层进行处理使其表面粗糙易吸水；
使所述处理后的功能层表面吸水；
化学气相沉积法在所述吸水后的功能层上形成介质层，所述介质层覆盖所述存储晶体管阵列的多个栅极堆叠结构顶表面、选择晶体管的栅极结构顶表面，填充所述存储晶体管的栅极堆叠结构与选择晶体管的栅极结构之间的间隙，并在所述存储晶体管阵列的多个栅极堆叠结构之间形成空气隙。
可选地，使所述处理后的功能层表面吸水通过：采用去离子水冲洗所述处理后的功能层实现。
可选地，使所述处理后的功能层表面吸水通过：将所述处理后的功能层置于含水环境中1～10天后进行所述沉积介质层步骤实现。
可选地，所述功能层的材质为二氧化硅，对所述功能层处理采用干法刻蚀。
可选地，所述干法刻蚀的气体为NF3，工艺参数为：气体流量10mL/min～50mL/min，功率100W～500W，刻蚀时间5s～10s。
可选地，所述功能层的厚度范围为
可选地，所述化学气相沉积法采用TEOS或硅烷，所述沉积工艺的温度范围为400℃～600℃。
可选地，所述基底还包括外围电路区，所述外围电路区具有若干逻辑晶体管，所述逻辑晶体管包括栅极结构以及位于所述栅极结构两侧的源漏区，所述存储晶体管的栅极堆叠结构之间的间隙小于相邻逻辑晶体管的栅极结构之间的间隙；所述功能层还形成在所述逻辑晶体管的栅极结构外表面以及相邻逻辑晶体管的栅极结构之间的基底表面；所形成的介质层还覆盖所述逻辑晶体管的栅极结构顶表面以及填充相邻逻辑晶体管的栅极结构之间的间隙。
可选地，所述存储晶体管的栅极堆叠结构自下而上包括：隧穿介质层、浮栅、栅间介质层以及控制栅；所述选择晶体管的栅极结构自下而上包括：栅介质层、下栅极、伪栅间介质层以及选择栅。
可选地，所述存储晶体管的栅极堆叠结构还包括位于所述控制栅上的金属硅化物，所述选择晶体管的栅极结构还包括位于所述选择栅上的金属硅化物。
可选地，所述控制栅、选择栅由字线充当。
可选地，所述逻辑晶体管的栅极结构自下而上包括：栅介质层、下栅极、伪栅间介质层以及逻辑栅。
可选地，所述存储晶体管的栅极堆叠结构还包括位于所述控制栅上的金属硅化物。
可选地，所述逻辑栅由字线充当。
与现有技术相比，本发明的技术方案具有以下优点：1)首先在存储晶体管栅极堆叠结构外表面及其间的基底表面采用原子层沉积法形成功能层，该功能层厚度均匀，且厚度较薄，不会填满间距较小的栅极堆叠结构之间的间隙；后对功能层进行处理使其表面粗糙易吸水；处理后的功能层吸水后，在功能层表面利用化学气相沉积工艺形成介质层，化学气相沉积工艺为高温工艺，在高温下，功能层内吸收的水分蒸发形成向上气流，阻止介质层沉积，从而提供了一种填充性能较差的介质层填充工艺。该填充性能较差的填充工艺能在间距较小的存储晶体管的栅极堆叠结构之间形成空气隙(air gap)，空气隙的介电常数小于二氧化硅介质层的介电常数，因而能降低读、写、擦除过程中产生的寄生电容，避免相邻存储晶体管之间相互干扰。
2)可选方案中，使处理后的功能层表面吸水可以通过：a)采用去离子水冲洗所述处理后的功能层实现，或b)将所述处理后的功能层置于含水大气中1～10天后进行所述沉积介质层步骤实现。上述提供了两种使处理后的功能层吸水的方案。
3)可选方案中，功能层的材质为二氧化硅，对所述功能层处理采用干法刻蚀，上述干法刻蚀可以通过控制气流、功率及刻蚀时间，使得功能层表面稍加刻蚀后粗糙、孔隙大、易吸水。
4)可选方案中，功能层的厚度范围为该厚度较小，不会影响现有器件的尺寸。
附图说明
图1至图6是本发明一实施例的快闪存储器在不同制作阶段的结构示意图。
具体实施方式
如背景技术中所述，现有技术中随着尺寸减小，相邻闪存单元之间的间距变小，两者之间在读、写、擦除时易出现干扰，这会造成闪存的性能不可靠。发明人经过分析，发现其产生的原因是：为对相邻闪存单元的栅极堆叠结构进行电绝缘，两者之间填充了介质层，上述介质层材质一般为二氧化硅，这造成读、写、擦除操作充放电过程中，寄生电容过大，因而未被操作的单元容易出现被干扰现象，改变其存储状态。
基于上述分析，本发明在制作快闪存储器，具体地，在沉积填充介质层时，利用上述沉积工艺中的高温将功能层内吸收的水分蒸发形成水蒸气，水蒸气蒸发形成向上气流，阻止介质层沉积，即采用一种填充性能差的填充工艺，使得介质层填充过程中在相邻闪存单元的栅极堆叠结构之间形成空气隙，以降低寄生电容，从而避免相邻存储单元之间的干扰。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图1至图6是本发明一实施例的快闪存储器在不同制作阶段的结构示意图。以下结合图1至图6，详细介绍一实施例的快闪存储器的制作方法。
首先，参照图1所示，提供基底10，基底10包括存储单元区Ⅰ与外围电路区Ⅱ；存储单元区Ⅰ具有存储晶体管阵列以及选择晶体管体，选择晶体管用于选择存储晶体管阵列中某一行或某一列存储晶体管，外围电路区Ⅱ具有若干逻辑晶体管；存储晶体管阵列包括多个分立的栅极堆叠结构101以及位于栅极堆叠结构101两侧的源漏区(未图示)，选择晶体管包括栅极结构102以及位于栅极结构102两侧的源漏区(未图示)，逻辑晶体管包括栅极结构103以及位于栅极结构103两侧的源漏区(未图示)。
基底10可以为半导体衬底，例如硅、绝缘体上硅(SOI)等。
具体地，参照图1所示，存储单元区Ⅰ的存储晶体管的栅极堆叠结构101密度较大，相邻两者之间的间隙较小。存储晶体管的栅极堆叠结构101与选择晶体管的栅极结构102之间的间隙、选择晶体管的栅极结构102与逻辑晶体管的栅极结构103之间的间隙、相邻逻辑晶体管的栅极结构103之间的间隙都较大。
继续参照图1所示，本实施例中，存储晶体管的栅极堆叠结构101自下而上包括：隧穿介电层101a、浮栅101b、栅间介电层101c以及控制栅101d。一个实施例中，隧穿介电层101a的材质为二氧化硅，浮栅101b的材质为掺杂多晶硅，栅间介电层101c的材质为二氧化硅、氮化硅、二氧化硅(ONO)的三层结构，控制栅101d的材质也为掺杂多晶硅。
选择晶体管的栅极结构102自下而上包括：栅介电层102a、下栅极102b、伪栅间介电层102c以及选择栅102d。伪栅间介电层102c中具有开口，使得下栅极102b与选择栅102d连接，两者之间电导通。一个实施例中，栅介电层102a的材质为二氧化硅，下栅极102b的材质为掺杂多晶硅，伪栅间介电层102c的材质为二氧化硅、氮化硅、二氧化硅(ONO)的三层结构，选择栅102d的材质也为掺杂多晶硅。
逻辑晶体管的栅极结构103自下而上包括：栅介电层103a、下栅极103b、伪栅间介电层103c以及逻辑栅103d。伪栅间介电层103c中也具有开口，使得下栅极103b与逻辑栅103d连接，两者之间电导通。一个实施例中，栅介电层103a的材质为二氧化硅，下栅极103b的材质为掺杂多晶硅，伪栅间介电层103c的材质为二氧化硅、氮化硅、二氧化硅(ONO)的三层结构，逻辑栅103d的材质也为掺杂多晶硅。
在具体制作过程中，一个实施例中，上述栅极堆叠结构101、栅极结构102、103的制作方法包括以下步骤包括：
隧穿介电层101a与栅介电层102a、103a在同层中形成，或先在半导体衬底上热氧化或沉积一层二氧化硅，该二氧化硅的厚度满足：选择晶体管的栅介电层102a厚度(或逻辑晶体管的栅介电层103a的厚度)与隧穿介电层101a厚度的差值；接着采用图形化光刻胶覆盖存储单元区Ⅰ中预定形成选择晶体管区域以及外围电路区Ⅱ的二氧化硅，以此为掩模，干法刻蚀预定形成存储晶体管区域的二氧化硅，暴露出半导体衬底表面，之后灰化去除残留的光刻胶；在保留的二氧化硅以及暴露的半导体衬底表面再沉积一层二氧化硅，该层二氧化硅的厚度满足隧穿介电层101a的需求。如此，在存储单元区Ⅰ中预定形成存储晶体管区域形成第一厚度的二氧化硅、存储单元区Ⅰ其它区域以及外围电路区Ⅱ形成第二厚度的二氧化硅。
接着在第一厚度与第二厚度的二氧化硅上衬底自下而上依次沉积第一掺杂多晶硅层，二氧化硅、氮化硅、二氧化硅(ONO)的三层结构；后干法刻蚀在ONO三层结构中形成开口以暴露第一掺杂多晶硅层，该开口位于预定形成选择晶体管、逻辑晶体管的栅极堆叠结构处；接着在ONO三层结构以及开口内沉积第二掺杂多晶硅层。
之后在第二掺杂多晶硅层上沉积硬掩模层，材质例如为二氧化硅，图形化形成图形化的硬掩模层。接着以此为掩膜，干法刻蚀第二掺杂多晶硅层、ONO三层结构、第一掺杂多晶硅层以及二氧化硅，以形成存储晶体管的多个分立的栅极堆叠结构101、选择晶体管的栅极结构102、以及逻辑晶体管的栅极结构103。
上述刻蚀形成栅极堆叠结构101、以及栅极结构102、103时，对第二掺杂多晶硅层的刻蚀同时形成了字线。
接着，分别对存储单元区Ⅰ与外围电路区Ⅱ的半导体衬底进行离子注入以对应形成存储晶体管、选择晶体管以及逻辑晶体管的源漏区(未图示)。
上述离子注入包括浅离子注入与深离子注入。浅离子注入以存储晶体管的栅极堆叠结构101、选择晶体管的栅极结构102、以及逻辑晶体管的栅极结构103为掩膜；浅离子注入后，分别在存储晶体管的栅极堆叠结构101、选择晶体管的栅极结构102，以及逻辑晶体管的栅极结构103两侧形成侧墙(未标示)，以上述侧墙为掩膜进行深离子注入。浅离子注入与深离子注入过程中，都可以在半导体衬底表面形成缓冲氧化层11。上述缓冲氧化层11材质例如为二氧化硅，在浅离子注入与深离子注入过程中保护半导体衬底表面。
之后仍参照图1所示，在存储晶体管的栅极堆叠结构101、选择晶体管的栅极结构102以及逻辑晶体管的栅极结构103顶部形成金属硅化物12。
在具体实施过程中，先采用酸洗处理，去除掺杂多晶硅表面氧化部分。上述酸洗过程去除了位于上部的侧墙，暴露出了存储晶体管的栅极堆叠结构101选择晶体管的栅极结构102以及逻辑晶体管的栅极结构103侧壁上部部分高度。之后在暴露出的存储晶体管的栅极堆叠结构101、选择晶体管的栅极结构102以及逻辑晶体管的栅极结构103侧壁、剩余的下部侧墙、以及缓冲氧化层11上沉积金属，材质例如为镍。其它实施例中，金属材质也可以为钴、钛或钨。高温硅化后，形成金属硅化物12。之后清洗去除未被硅化的金属。
由于存储晶体管的栅极堆叠结构101宽度较小，因而硅化后，其暴露出的高度全部转化为金属硅化物12。选择晶体管以及逻辑晶体管的栅极结构102、103宽度较大，硅化后，其暴露出的高度自外表面向内部分深度转化为金属硅化物12。
接着，参照图2所示，原子层沉积法在存储晶体管阵列的多个栅极堆叠结构101外表面、相邻栅极堆叠结构101之间的基底表面、选择晶体管的栅极结构102外表面、存储晶体管的栅极堆叠结构101与选择晶体管的栅极结构102之间的基底表面、逻辑晶体管的栅极结构103外表面、选择晶体管的栅极结构102与逻辑晶体管的栅极结构103之间的基底表面、相邻逻辑晶体管的栅极结构103之间的基底表面形成功能层13。
本实施例中，上述多个栅极堆叠结构101之间的基底表面、存储晶体管的栅极堆叠结构101与选择晶体管的栅极结构102之间的基底表面、选择晶体管的栅极结构102与逻辑晶体管的栅极结构103之间的基底表面、相邻逻辑晶体管的栅极结构103之间的基底表面覆盖有缓冲氧化层11，因而，功能层13形成在缓冲氧化层11上。其它实施例中，功能层13也可以直接形成在半导体衬底表面。
在具体实施过程中，功能层13的材质可以为二氧化硅，厚度范围例如为采用原子层沉积法(ALD)，一方面，能在间距较小的存储晶体管栅极堆叠结构101外表面及其间的基底表面形成厚度均匀的功能层13；另一方面，厚度较薄，不会填满该存储晶体管栅极堆叠结构101之间的间隙。
之后，参照图3所示，对功能层13进行处理使其表面粗糙易吸水。
在具体实施过程中，为使功能层13表面粗糙易吸水，可以通过稍加干法刻蚀实现。具体地，通过选择干法刻蚀气体，控制干法刻蚀的气流流量、功率、刻蚀时间，以对功能层13外表面稍加刻蚀，目的是使其表面粗糙。一个实施例中，干法刻蚀的气体为NF3，气体流量10mL/min～50mL/min，功率100W～500W，刻蚀时间5s～10s。
接着，参照图4所示，使处理后的功能层13表面吸水。
在具体实施过程中，本步骤可以通过，如图4所示，采用去离子水冲洗处理后的功能层13实现。其它实施例中，也可以通过：将处理后的功能层13置于含水环境中1～10天，之后再进行后续步骤。上述含水环境例如为超净室，处理后的功能层13吸收大气中的水分。
之后，参照图5与图6所示，化学气相沉积法在吸水后的功能层13上形成介质层14，介质层14覆盖存储晶体管阵列的多个栅极堆叠结构101顶表面、选择晶体管的栅极结构102顶表面、逻辑晶体管的栅极结构103顶表面，填充存储晶体管的栅极堆叠结构101与选择晶体管的栅极结构102之间的间隙、选择晶体管的栅极结构102与逻辑晶体管的栅极结构103之间的间隙、相邻逻辑晶体管栅极结构103之间的间隙，并在存储晶体管阵列的多个栅极堆叠结构101之间形成空气隙15(参照图6所示)。
本步骤中，化学气相沉积法采用TEOS或硅烷，形成二氧化硅介质层14，沉积工艺的温度范围为400℃～600℃，能使得处理后的功能层13吸收的水分增发，水分蒸发形成向上气流，阻止介质层14沉积，从而提供了一种填充性能较差的介质层14填充工艺。
参照图6所示，存储晶体管的栅极堆叠结构101与选择晶体管的栅极结构102之间的间隙、选择晶体管的栅极结构102与逻辑晶体管的栅极结构103之间的间隙、相邻逻辑晶体管的栅极结构103之间的间隙都较大，因而即使介质层14的填充性能较差，也能填充上述间隙；而存储晶体管的相邻栅极堆叠结构101之间间隙较小，介质层14的填充性能较差，仅能覆盖栅极堆叠结构101顶部，而相邻之间的间隙形成了空气隙15。
可以理解的是，上述实施例中，存储单元区Ⅰ的存储晶体管、选择晶体管与外围电路区Ⅱ的逻辑晶体管同时制作，其它实施例中，也可以存储单元区Ⅰ的存储晶体管、选择晶体管，与外围电路区Ⅱ的逻辑晶体管在不同制程中分别制作。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (14)

1.一种快闪存储器的制作方法，其特征在于，包括：
提供基底，所述基底至少包括存储单元区，所述存储单元区具有存储晶体管阵列以及选择晶体管，所述选择晶体管用于选择所述存储晶体管阵列中某一行或某一列存储晶体管；所述存储晶体管阵列包括多个分立的栅极堆叠结构以及位于所述栅极堆叠结构两侧的源漏区，所述选择晶体管包括栅极结构以及位于所述栅极结构两侧的源漏区；其中，所述存储晶体管的栅极堆叠结构之间的间隙小于所述存储晶体管的栅极堆叠结构与所述选择晶体管的栅极结构之间的间隙；
原子层沉积法在所述存储晶体管阵列的多个栅极堆叠结构外表面、相邻栅极堆叠结构之间的基底表面、选择晶体管的栅极结构外表面、以及存储晶体管的栅极堆叠结构与选择晶体管的栅极结构之间的基底表面形成功能层；
对所述功能层进行处理使其表面粗糙易吸水；
使所述处理后的功能层表面吸水；
化学气相沉积法在所述吸水后的功能层上形成介质层，所述介质层覆盖所述存储晶体管阵列的多个栅极堆叠结构顶表面、选择晶体管的栅极结构顶表面，填充所述存储晶体管的栅极堆叠结构与选择晶体管的栅极结构之间的间隙，并在所述存储晶体管阵列的多个栅极堆叠结构之间形成空气隙。
2.根据权利要求1所述的制作方法，其特征在于，使所述处理后的功能层表面吸水通过：采用去离子水冲洗所述处理后的功能层实现。
3.根据权利要求1所述的制作方法，其特征在于，使所述处理后的功能层表面吸水通过：将所述处理后的功能层置于含水环境中1～10天后进行所述沉积介质层步骤实现。
4.根据权利要求1所述的制作方法，其特征在于，所述功能层的材质为二氧化硅，对所述功能层处理采用干法刻蚀。
5.根据权利要求4所述的制作方法，其特征在于，所述干法刻蚀的气体为NF3，工艺参数为：气体流量10mL/min～50mL/min，功率100W～500W，刻蚀时间5s～10s。
6.根据权利要求1所述的制作方法，其特征在于，所述功能层的厚度范围为
7.根据权利要求1所述的制作方法，其特征在于，所述化学气相沉积法采用TEOS或硅烷，所述沉积工艺的温度范围为400℃～600℃。
8.根据权利要求1所述的制作方法，其特征在于，所述基底还包括外围电路区，所述外围电路区具有若干逻辑晶体管，所述逻辑晶体管包括栅极结构以及位于所述栅极结构两侧的源漏区，所述存储晶体管的栅极堆叠结构之间的间隙小于相邻逻辑晶体管的栅极结构之间的间隙；所述功能层还形成在所述逻辑晶体管的栅极结构外表面以及相邻逻辑晶体管的栅极结构之间的基底表面；所形成的介质层还覆盖所述逻辑晶体管的栅极结构顶表面以及填充相邻逻辑晶体管的栅极结构之间的间隙。
9.根据权利要求1所述的制作方法，其特征在于，所述存储晶体管的栅极堆叠结构自下而上包括：隧穿介质层、浮栅、栅间介质层以及控制栅；所述选择晶体管的栅极结构自下而上包括：栅介质层、下栅极、伪栅间介质层以及选择栅。
10.根据权利要求9所述的制作方法，其特征在于，所述存储晶体管的栅极堆叠结构还包括位于所述控制栅上的金属硅化物，所述选择晶体管的栅极结构还包括位于所述选择栅上的金属硅化物。
11.根据权利要求9或10所述的制作方法，其特征在于，所述控制栅、选择栅由字线充当。
12.根据权利要求8所述的制作方法，其特征在于，所述逻辑晶体管的栅极结构自下而上包括：栅介质层、下栅极、伪栅间介质层以及逻辑栅。
13.根据权利要求12所述的制作方法，其特征在于，所述存储晶体管的栅极堆叠结构还包括位于所述控制栅上的金属硅化物。
14.根据权利要求12或13所述的制作方法，其特征在于，所述逻辑栅由字线充当。
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