CN106486441B - 表面贴装电子组件 - Google Patents

表面贴装电子组件 Download PDF

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CN106486441B
CN106486441B CN201610108758.6A CN201610108758A CN106486441B CN 106486441 B CN106486441 B CN 106486441B CN 201610108758 A CN201610108758 A CN 201610108758A CN 106486441 B CN106486441 B CN 106486441B
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substrate
metallization layer
porous silicon
insulating layer
opening
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CN106486441A (zh
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O·奥里
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STMicroelectronics Tours SAS
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STMicroelectronics Tours SAS
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Abstract

本申请涉及表面贴装电子组件。由具有前表面和侧面的硅基底形成表面贴装芯片。该芯片包括将被焊接到外部器件的金属化层。所述金属化层具有覆盖所述基底的前表面的至少一部分的第一部分以及覆盖所述基底的侧面的至少一部分的第二部分。在所述基底中包括多孔硅区域用以将所述金属化层的第二部分与基底的其余部分相分离。

Description

表面贴装电子组件
相关申请的交叉引用
本申请要求提交于2015年8月31日的法国专利申请No.15/58067的优先权权益，其内容在法律所允许的最大程度上作为整体通过引用而并入于此。
技术领域
本公开内容涉及半导体芯片的领域。其更为具体地目的在于表面贴装芯片，也即在至少一个表面上包括金属化层(metallization)的芯片，该金属化层将被焊接到例如印刷电路或其他芯片的外部器件。
背景技术
在特定的应用中，需求如下表面贴装芯片，其中将被焊接到外部器件的金属化层连续有在芯片侧面上的侧向部分。当执行焊接时，部分的焊接材料接合到金属化层的侧向部分，这使得能够可视地检查连接的质量。这种需求例如存在于诸如汽车领域或医疗领域的敏感领域中。
在美国专利申请公开No.2012/0053760(通过引用并入)中描述了一种形成表面贴装芯片的方法的示例，该表面贴装芯片包括在芯片的侧面上连续的金属化层。然而该方法具有缺点并且特别地产生实践中的实施问题。
发明内容
因此，实施例提供了一种表面贴装芯片，其形成在硅基底的内部和顶部上，该硅基底具有前表面和侧面，该芯片包括：将被焊接到外部器件的至少一个金属化层，该金属化层包括覆盖基底的前表面的至少一部分的第一部分和覆盖基底的侧面的至少一部分的第二部分；以及多孔硅区域，被包括在基底中，将金属化层的第二部分与基底的其余部分相分离。
根据实施例，金属化层的第二部分被布置在位于基底的侧面上的沟槽中。
根据实施例，芯片进一步包括：有源区，形成在基底的内部和顶部上并且包含电子电路；以及至少一个接触区域，连接到电子电路并且位于芯片的前表面上，其中金属化层的第一部分连接到接触区域。
根据实施例，绝缘层被布置在基底的前表面和金属化层的第一部分之间。
根据实施例，多孔硅区域在交叠区中与绝缘层相接触。
另一个实施例提供了一种在硅基底的内部和顶部上形成表面贴装芯片的方法，该方法包括步骤：a)从基底的上表面蚀刻开口，该开口限定芯片的侧面的部分；b)形成在基底中从开口的侧壁延伸的多孔硅区域；以及c)形成将被焊接到外部器件的金属化层，该金属化层包括覆盖基底的上表面的至少一部分的第一部分，并且在开口的侧壁的至少一部分之上延伸的第二部分中连续。
根据实施例，该方法进一步包括在步骤c)之后，沿着穿过开口的切割线进行切割的步骤。
根据实施例，在切割步骤期间，切割区具有比开口的宽度更小的宽度。
根据实施例，该方法包括对基底的下表面进行研磨的步骤。
根据实施例，在步骤c)，金属化层的形成包括电化学沉积步骤。
附图说明
在下面结合附图对特定实施例的非限制性描述中将对前述和其他特征以及优势进行详细讨论，其中：
图1A、图1B、图2A、图2B、图3A、图3B、图4A、图4B以及图4C示意性地示出了表面贴装芯片制造方法的实施例的步骤。
具体实施方式
在不同的附图中用相同的参考标号对相同的元素进行指代并且，进一步，各个附图并不按照比例。
在下面的描述中，当提及对绝对位置进行形容的诸如“左”、“右”等术语或者对相对位置进行形容的诸如“之上”、“之下”、“上”、“下”等术语或者对方向进行形容的诸如“水平”、“垂直”等术语时，其参照的是图1B、图2B、图3B、图4B的横截面视图的定向，应理解到，在实践中，所描述的器件可以被不同地定向。除非另外有所指定，否则表述“接近地”、“基本上”以及“在数量级上”意味着在10％之内，优选地在5％之内，或者关于定向限定词，意味着在10度之内，优选地在5度之内。
图1A、图1B、图2A、图2B、图3A、图3B、图4A、图4B以及图4C示意性地示出了表面贴装芯片制造方法的实施例的步骤。图1B、图2B、图3B、图4B为沿着图1A、图2A、图3A、图4A的B-B面的横截面视图。图1A和图2A为沿着图1B和图2B的A-A面的横截面视图。图3A和图4A为顶视图。图4C为根据图4A的B-B面和C-C面切割的透视图。
之后描述的步骤涉及从同一硅基底1同时形成例如相同的多个芯片。为了简化，在附图中仅仅示出了两个相邻芯片的两个部分，这些部分在附图的左手部分和右手部分各自彼此相对。芯片中的每一个都包括，在基底1的内部和顶部上的具有电子电路的有源区3，电子电路包括形成在其中的一个或多个半导体组件(未示出)。除了连接到电子电路的一个或多个接触区域7之外，有源区3的上表面整体地覆盖有绝缘层5。之后描述的步骤更为具体地关注在每个芯片中形成将被焊接到外部器件的至少一个金属化层，该金属化层包括与芯片的一个或多个接触区域7相接触的上部部分和在芯片的侧面上的侧向部分。
图1A和图1B示出了其中从基底晶圆1开始的步骤，在基底晶圆的内部和顶部上预先形成了有源区3、绝缘层5以及接触区域7。在这个阶段，尚未发生将基底晶圆切割为各个芯片。在顶视图中，相邻芯片的有源区3由间隔区9分隔开，每个间隔区具有限定于其内的切割线11。在附图中，仅仅示出了间隔区9的条带的部分和相对应的切割线11的部分。
在所示出的示例中，在包括在间隔区9中且包含切割线11的条带13中，去除了绝缘层5，使得露出基底1的表面。在这个示例中，条带13的宽度比间隔区9的宽度小，并且在顶视图中，条带13严格地包含在间隔区9之内，也就是，条带13的边沿与间隔区9的边沿有距离。由此，在条带13的每一侧上，绝缘层5覆盖在间隔区9的部分中的基底1。
在位于两个相邻芯片之间的条带13的部分中，从基底的上表面在基底1中蚀刻一个或多个局部开口15。在顶视图中，每个开口15被包括在条带13中的切割线11所穿过。芯片在切割线11的方向上的尺度大于沿着切割线的开口15的尺度之和。换句话说，至少一个未蚀刻的间隔17保持在沿着切割线11的芯片之间的条带13中。
在所示出的示例中，可以看见两个开口15，每个都定位在位于附图的左手部分的芯片的接触区域7和位于附图的右手部分的芯片的接触区域7之间。在所示出的示例中，在顶视图中开口15具有矩形形状，但其他的形状是可能的。在这个示例中，开口15垂直地延伸到比被有源部分3占据的基底1的厚度更大的深度处。在这个示例中，开口15并非贯穿开口而是盲开口，也就是其垂直地向下延伸到比基底1的厚度更小的深度。作为变形，开口15可以是贯穿开口。
开口15可以通过等离子体蚀刻方法来形成，例如RIE类型蚀刻(“反应离子蚀刻”)。更普遍地，可以使用任何其他能够在条带13中形成局部开口的方法，例如化学或激光蚀刻。
图2A和图2B示出了在图1A和图1B中示出的步骤之后的步骤，其中从开口15的侧壁和底部在基底1中形成多孔硅区域20。在顶视图中，多孔硅区域20包括在间隔区9之内。更具体地，在顶视图中，每个开口15被多孔硅区域20围绕，其从开口15的侧壁一直延伸到位于绝缘层5之下的基底1的部分中。由此在交叠区22中，多孔硅区域20的部分具有与绝缘层5的下表面相接触的上表面。在所示出的示例中，每个开口15的底部和侧壁全部由多孔硅区域20围绕，因此开口15通过区域20与基底的其余部分绝缘。在这个示例中，交叠区22在每个开口15的层级上出现在切割线11的任何一侧。
多孔硅区域20可以例如通过电化学溶解法来形成。为了达到这点，可以形成覆盖除了开口15之外的、图1A和图1B的构件的上表面的掩模。构件可以接着被插入在与构件的下表面相对的第一电极和与构件的上表面相对的第二电极之间的氢氟酸溶液中。设定电流的流动和具有适合波长的可能的光照，以在开口15的侧壁和底部的层级上引起基底1的部分硅的溶解。由此，在每个开口15的层级上，围绕着开口15的基底区域1被转换为多孔硅。在所示出的示例中，与不同的开口15相关联的多孔硅区域20是分离的。作为变形，可以形成在顶视图中在条带13的整个表面之上延伸的连续的多孔硅区域，这个区域在交叠区22的层级上在绝缘层5之下连续。
一旦多孔硅区域20已经被形成，可以例如通过热氧化提供多孔硅氧化步骤。多孔硅的氧化实现了区域20的绝缘属性的增加。然而这种氧化步骤是可选的。
图3A和图3B示出了在图2A和图2B中示出的步骤之后的步骤，其中形成将被焊接到外部器件的金属化层30。每个金属化层30包括至少一个上部部分30a和侧向部分30b，该至少一个上部部分30a覆盖形成在基底1的内部和顶部上的芯片中的至少一个芯片的上表面或前表面的部分，该侧向部分30b至少覆盖开口15和芯片接壤的侧壁的部分。在每个芯片上，芯片的至少一个接触区域7与金属化层30的上部部分30a相接触。
在所示出的示例中，对于开口15中的每一个开口，形成金属化层30，金属化层30覆盖开口15的侧壁和底部，并且在位于附图的左手部分的芯片的上表面上的第一上部部分30a和位于附图的右手部分的芯片的上表面上的第二上部部分30a中延伸。在所示出的示例中，每个金属化层30具有与位于附图的左手部分的芯片的接触区域7相接触的第一上部部分30a以及与位于附图的右手部分的芯片的接触区域7相接触的第二上部部分30a。
金属化层30例如由电化学沉积方法形成。为了达到这点，可以形成未示出的掩模，这个掩模覆盖图2A和图2B的构件的整个上表面，除了金属化层应沉积的位置。接着可以利用例如溅射方法沉积籽晶层。一旦籽晶层已经被沉积，可以从这个籽晶层执行电化学沉积以形成金属化层30。作为变形，可以相继地执行多个连续的电化学沉积，从而获得包括多个不同金属层的金属化层30。更普遍地，可以使用任何其他适合的沉积方法来形成金属化层30。
图4A、图4B以及图4C示出了在图3A和图3B中示出的步骤之后的步骤，其中基底1例如通过锯切、通过激光或化学切割、通过劈裂或通过任何其他适合的切割方法被沿着切割线11中的每一个切割线切割为各个芯片。在顶视图中，在切割线11上居中的切割条带或者切割区40从两个相邻的芯片之间去除从而分离芯片。开口15的宽度大于切割条带40的宽度。更为具体地，选择开口15的宽度，使得位于芯片侧面上的金属化层30的侧向部分30b在切割期间不被去除。为了达到这点，在所示出的示例中，开口15的宽度L15使得L15-2*e30b>L40，e30b为金属化层30的侧向部分30b的厚度，并且L40为条带40的宽度。
在所示出的示例中，在实际的切割步骤之前，执行将基底1的下表面或后表面进行研磨的预先步骤。在研磨步骤期间，基底1的部分被从基底1的下表面的构件的整个表面去除。在到达有源区3之前中断研磨。例如在涂覆开口15的底部的金属化层部分30的上表面与有源区3的下表面之间的中间层级处中断研磨。由此，在研磨步骤的结束时，开口15显现在基底1的背表面上。作为变形，研磨可以在到达开口15的底部之前中断。在另一个变形中，研磨步骤可以省略。
在切割之后，芯片中的每一个芯片包括至少一个金属化层30，金属化层30具有覆盖芯片的上表面的部分的上部部分30a并且具有覆盖芯片的侧面的部分的侧向部分30b，芯片的至少一个区域7与金属化层30的上部部分30a相接触。每个金属化层30具有通过多孔硅区域20与基底1的其余部分相绝缘的侧向部分30b。金属化层30的上部部分30a的绝缘特别地由绝缘层5来确保。交叠区22确保了在通过绝缘层5的绝缘和通过多孔硅区域20的绝缘之间的绝缘连续性。
每个金属化层30例如由覆盖有锡层的铜层形成。
作为示例，开口15具有在从50μm到100μm的范围中的宽度，金属化层具有在从0.8μm到6μm的范围中的厚度，并且切割条带40具有在从10μm到30μm的范围中的宽度。多孔硅区域20例如具有在从10μm到50μm的范围中的厚度。
上面所描述的方法的优势在于其提供了这样的芯片，即在其前表面上具有将被焊接到外部器件的金属化层30，其中金属化层30在芯片侧面的部分上延伸，其使得能够可视地检查连接的质量。
由此获得的芯片的其他优势在于，在金属化层30的侧向部分30b和基底1之间的绝缘由形成在基底1中的多孔硅区域20获得。因此可以容易地根据应用的需要来调整绝缘厚度。特别地，可以容易地形成具有显著厚度的多孔硅区域20，例如，大于10μm，这尤其能够使得降低金属化层30和基底1之间的电容性耦合。具有显著厚度的多孔硅区域20的存在进一步使得能够在切割步骤期间限制金属化层30和基底1之间的短路的风险。
由上述方法获得的芯片的另一个优势在于，由于开口15的宽度大于切割条带40的厚度这一事实，金属化层30的侧向部分30b可以具有凹陷的形状。更为具体地，在所示出的示例中，金属化层30的侧向部分30b具有布置在位于芯片侧面上的垂直沟槽中的垂直沟道的形状。这个几何形状允许改善焊接材料到芯片侧面的接合。此外，这种几何形状能够使得对焊接的可视控制更为容易。此外，这种几何形状能够使得将焊接材料定位在垂直沟道的内部，由此限制了在相邻金属化层30之间的短路的风险。
上述方法的另一个优势在于，在关于图1A和图1B描述的步骤期间沿着切割线11保持在芯片之间的未蚀刻的间隔17可以接纳对于芯片制造有用的元件，诸如例如使得能够在方法的不同步骤期间简化基底的定位的对准标记，蚀刻控制元件或者电子控制元件。
已经描述了特定的实施例。对于本领域的技术人员来说，将想到各种改变、修改以及改进。特别地，关于图1A和图1B描述的去除在切割线11的任意侧上延伸的条带13中的绝缘层5的步骤是可选的。作为变形，绝缘层5可以保持在层13中，并且开口15可以从绝缘层5的上表面形成。
此外，所描述的实施例并不限于关于图1A和图1B所描述的示例，其中开口15垂直地向下延伸到大于有源区3的厚度且小于基底1的厚度的深度处。作为变形，在关于图1A和图1B所描述的步骤中形成的开口15可以具有小于有源区3的厚度的深度或者可以贯穿通过基底1。
此外，所描述的实施例并不限于上述的示例，其中仅仅基底1的上表面支撑在基底侧面上延伸的金属化层。作为变形，基底的上表面和下表面中的每一个都可以提供有在基底侧面上延伸的金属化层。
作为示例，下表面金属化层和上表面金属化层可以由位于基底的侧面上的金属化层部分进行连接。当芯片的电子电路具有在基底的下表面上的接触区域时，例如，与具有垂直操作的组件的接触，接触可以由此被传送到将被焊接到外部器件的上表面金属化层。上表面接触同样可以采用这种方式朝向将被焊接到例如另一芯片的下表面金属化层传送。
作为变形，下表面金属化层可以独立于上表面金属化层，也就是，并不与上表面金属化层相连接。
这种改变、修改以及改进意在于作为本公开内容的部分，并且意在于囊括在本发明的精神和范围之内。相应地，前面的描述仅仅作为示例，并不意在于进行限制。本发明仅限于如在随附权利要求及其等同物中所限定的。

Claims (14)

1.一种表面贴装集成电路芯片，包括：
基底，具有前表面和侧面；
至少一个金属化层，被配置为将被焊接到外部器件，所述至少一个金属化层包括第一部分和第二部分，所述第一部分覆盖所述基底的所述前表面的至少一部分，所述第二部分覆盖所述基底的所述侧面的至少一部分；
多孔硅区域，被包括在所述基底中，并将所述金属化层的所述第二部分与所述基底的其余部分相分离；以及
绝缘层，被布置在所述基底的所述前表面和所述至少一个金属化层的所述第一部分之间，所述绝缘层与所述多孔硅区域分开地形成，
其中所述至少一个金属化层的所述第二部分具有垂直沟道的形状，所述垂直沟道被布置在位于所述基底的侧面上的垂直沟槽中。
2.根据权利要求1所述的芯片，进一步包括：
有源区，形成在所述基底的所述其余部分的内部和顶部上，并且包含电子电路；以及
至少一个接触区域，连接到所述电子电路并且位于所述基底的所述前表面上，
其中所述至少一个金属化层的所述第一部分连接到所述至少一个接触区域。
3.根据权利要求1所述的芯片，其中所述多孔硅区域在交叠区中与所述绝缘层相接触。
4.一种用于形成表面贴装集成电路芯片的方法，包括步骤：
a)从基底的上表面蚀刻开口，所述开口限定所述表面贴装集成电路芯片的侧面的部分；
b)形成在所述基底中从所述开口的侧壁延伸的多孔硅区域；以及
c)形成被配置为将被焊接到外部器件的金属化层，所述金属化层包括覆盖所述基底的上表面的至少一部分的第一部分，并且在所述开口的所述侧壁的至少一部分之上延伸的第二部分中延伸，
其中所述方法还包括：在所述基底的上表面上形成绝缘层，其中所述金属化层的所述第一部分在所述绝缘层之上延伸，并且所述绝缘层与所述多孔硅区域分开地形成，并且其中所述金属化层的所述第二部分具有垂直沟道的形状，所述垂直沟道被布置在位于所述开口的所述侧壁上的垂直沟槽中。
5.根据权利要求4所述的方法，进一步包括，在步骤c)之后，沿着穿过所述开口的切割线进行切割。
6.根据权利要求5所述的方法，其中所述切割包括去除具有比所述开口的宽度更小的宽度的切割区。
7.根据权利要求4所述的方法，进一步包括对所述基底的下表面进行研磨。
8.根据权利要求4所述的方法，其中形成所述金属化层包括执行电化学沉积步骤。
9.一种集成电路芯片，包括：
半导体基底，包括具有电路的有源区；
金属接触，在所述半导体基底上方并且与所述有源区的所述电路电连接；
所述半导体基底的多孔硅区域，沿着所述半导体基底的侧边沿；
金属层，具有与所述金属接触相接触的第一部分并且具有从所述第一部分延伸到所述半导体基底的所述侧边沿上并且与所述多孔硅区域相接触的第二部分；以及
绝缘层，在所述半导体基底的顶部上并且围绕所述金属接触，其中所述金属层的所述第一部分在所述绝缘层之上延伸，并且所述绝缘层与所述多孔硅区域分开地形成，并且其中所述金属层的所述第二部分具有垂直沟道的形状，所述垂直沟道被布置在位于所述半导体基底的侧边沿上的垂直沟槽中。
10.根据权利要求9所述的芯片，其中所述多孔硅区域的部分在所述绝缘层的外围边沿之下延伸。
11.一种用于形成集成电路芯片的方法，包括：
在两个相邻的有源区之间在半导体晶圆中形成开口；
在每个所述有源区中在所述半导体晶圆上提供金属接触；
将盲开口的侧壁处的所述半导体晶圆的部分转换成多孔硅；
形成金属化层，所述金属化层包括第一部分和第二部分，所述第一部分与用于所述有源区的金属接触相接触，所述第二部分在所述第一部分之间延伸到所述开口中并且沿着所述开口的侧壁与所述多孔硅相接触；以及
经由通过所述开口进行切割来分割所述半导体晶圆，从而将所述半导体晶圆分离为第一芯片和第二芯片，所述金属化层的所述第二部分提供用于所述第一芯片和所述第二芯片中的每一个芯片的侧部电接触，
其中所述方法还包括：在所述半导体晶圆上形成围绕所述金属接触的绝缘层，其中所述金属化层的所述第一部分在所述绝缘层之上延伸，并且所述绝缘层与所述多孔硅分开地形成，并且其中所述金属化层的所述第二部分具有垂直沟道的形状，所述垂直沟道被布置在位于所述开口的所述侧壁上的垂直沟槽中。
12.根据权利要求11所述的方法，进一步包括在分割之前对所述半导体晶圆的下表面进行研磨。
13.根据权利要求11所述的方法，其中形成所述金属化层包括执行电化学沉积步骤。
14.根据权利要求11所述的方法，其中所述绝缘层在交叠处覆盖所述多孔硅的部分。
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3040532B1 (fr) * 2015-08-31 2017-10-13 St Microelectronics Tours Sas Puce a montage en surface
FR3069102A1 (fr) * 2017-07-13 2019-01-18 Stmicroelectronics (Tours) Sas Procede de fabrication de puces isolees lateralement
WO2020146994A1 (zh) * 2019-01-15 2020-07-23 深圳市汇顶科技股份有限公司 芯片及芯片的制造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10207467A (ja) * 1997-01-27 1998-08-07 Citizen Electron Co Ltd 表面実装型電磁発音体及びその製造方法
US6569698B2 (en) * 2000-12-07 2003-05-27 Harvatek Corp. Focusing cup on a folded frame for surface mount optoelectric semiconductor package
US8344499B2 (en) * 2010-05-24 2013-01-01 Alpha & Omega Semiconductor, Inc Chip-exposed semiconductor device
CN104319340A (zh) * 2014-11-05 2015-01-28 安徽荃富信息科技有限公司 一种led灯用防潮支架

Family Cites Families (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3640806A (en) * 1970-01-05 1972-02-08 Nippon Telegraph & Telephone Semiconductor device and method of producing the same
US3962052A (en) * 1975-04-14 1976-06-08 International Business Machines Corporation Process for forming apertures in silicon bodies
US4096619A (en) * 1977-01-31 1978-06-27 International Telephone & Telegraph Corporation Semiconductor scribing method
US4437141A (en) 1981-09-14 1984-03-13 Texas Instruments Incorporated High terminal count integrated circuit device package
RU2082258C1 (ru) * 1991-08-14 1997-06-20 Сименс АГ Схемная структура с по меньшей мере одним конденсатором и способ ее изготовления
JPH0613366A (ja) * 1992-04-03 1994-01-21 Internatl Business Mach Corp <Ibm> 多孔性シリコン膜およびデバイスを作成するための浸漬走査方法およびシステム
US5637916A (en) 1996-02-02 1997-06-10 National Semiconductor Corporation Carrier based IC packaging arrangement
JP2956606B2 (ja) 1996-08-21 1999-10-04 日立エーアイシー株式会社 端面スルーホール配線板
KR100237051B1 (ko) 1996-12-28 2000-01-15 김영환 버텀리드 반도체 패키지 및 그 제조 방법
US6255156B1 (en) * 1997-02-07 2001-07-03 Micron Technology, Inc. Method for forming porous silicon dioxide insulators and related structures
US6153489A (en) * 1997-12-22 2000-11-28 Electronics And Telecommunications Research Institute Fabrication method of inductor devices using a substrate conversion technique
JP3877410B2 (ja) 1997-12-26 2007-02-07 三洋電機株式会社 半導体装置の製造方法
JP2000294719A (ja) 1999-04-09 2000-10-20 Hitachi Ltd リードフレームおよびそれを用いた半導体装置ならびにその製造方法
JP3429246B2 (ja) 2000-03-21 2003-07-22 株式会社三井ハイテック リードフレームパターン及びこれを用いた半導体装置の製造方法
JP4477202B2 (ja) 2000-07-12 2010-06-09 ローム株式会社 半導体装置およびその製造方法
ITMI20011965A1 (it) 2001-09-21 2003-03-21 St Microelectronics Srl Conduttori di un contenitore del tipo no-lead di un dispositivo semiconduttore
SG102639A1 (en) * 2001-10-08 2004-03-26 Micron Technology Inc Apparatus and method for packing circuits
US6608366B1 (en) 2002-04-15 2003-08-19 Harry J. Fogelson Lead frame with plated end leads
US7153754B2 (en) * 2002-08-29 2006-12-26 Micron Technology, Inc. Methods for forming porous insulators from “void” creating materials and structures and semiconductor devices including same
JP4864307B2 (ja) * 2003-09-30 2012-02-01 アイメック エアーギャップを選択的に形成する方法及び当該方法により得られる装置
DE10351028B4 (de) * 2003-10-31 2005-09-08 Infineon Technologies Ag Halbleiter-Bauteil sowie dafür geeignetes Herstellungs-/Montageverfahren
JP2008505434A (ja) * 2004-04-27 2008-02-21 テル アビブ ユニバーシティ フューチャー テクノロジー ディベロップメント リミティド パートナーシップ インターレース型のマイクロコンテナ構造に基づく３−ｄマイクロ電池
US20060043534A1 (en) * 2004-08-26 2006-03-02 Kirby Kyle K Microfeature dies with porous regions, and associated methods and systems
DE102005004160B4 (de) * 2005-01-28 2010-12-16 Infineon Technologies Ag CSP-Halbleiterbaustein, Halbleiterschaltungsanordnung und Verfahren zum Herstellen des CSP-Halbleiterbausteins
WO2007082075A2 (en) * 2006-01-11 2007-07-19 The Regents Of The University Of California Optical sensor for detecting chemical reaction activity
US7635899B2 (en) * 2007-01-11 2009-12-22 International Business Machines Corporation Structure and method to form improved isolation in a semiconductor device
US7955893B2 (en) * 2008-01-31 2011-06-07 Alpha & Omega Semiconductor, Ltd Wafer level chip scale package and process of manufacture
US20100133693A1 (en) 2008-12-03 2010-06-03 Texas Instruments Incorporated Semiconductor Package Leads Having Grooved Contact Areas
US8362606B2 (en) * 2010-07-29 2013-01-29 Alpha & Omega Semiconductor, Inc. Wafer level chip scale package
US8163629B2 (en) 2010-08-05 2012-04-24 Infineon Technologies Ag Metallization for chip scale packages in wafer level packaging
JP5675504B2 (ja) * 2010-08-06 2015-02-25 ルネサスエレクトロニクス株式会社 半導体装置、電子装置、及び半導体装置の製造方法
US8850131B2 (en) 2010-08-24 2014-09-30 Advanced Micro Devices, Inc. Memory request scheduling based on thread criticality
FR2969376B1 (fr) * 2010-12-16 2013-09-27 St Microelectronics Crolles 2 Procédé de fabrication de puces de circuits intégrés
DE102011010248B3 (de) * 2011-02-03 2012-07-12 Infineon Technologies Ag Ein Verfahren zum Herstellen eines Halbleiterbausteins
DE102011101035B4 (de) * 2011-05-10 2014-07-10 Infineon Technologies Ag Ein Verfahren zum Herstelllen eines Anschlussgebiets an einer Seitenwand eines Halbleiterkörpers
US8906782B2 (en) * 2011-11-07 2014-12-09 Infineon Technologies Ag Method of separating semiconductor die using material modification
US9466662B2 (en) * 2012-12-28 2016-10-11 Intel Corporation Energy storage devices formed with porous silicon
KR102154112B1 (ko) * 2013-08-01 2020-09-09 삼성전자주식회사 금속 배선들을 포함하는 반도체 장치 및 그 제조 방법
TWI566409B (zh) * 2014-08-26 2017-01-11 元太科技工業股份有限公司 電晶體及其製作方法
US9536679B2 (en) * 2015-01-06 2017-01-03 Johnny Duc Van Chiem Trenched super/ultra capacitors and methods of making thereof
FR3040532B1 (fr) * 2015-08-31 2017-10-13 St Microelectronics Tours Sas Puce a montage en surface

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10207467A (ja) * 1997-01-27 1998-08-07 Citizen Electron Co Ltd 表面実装型電磁発音体及びその製造方法
US6569698B2 (en) * 2000-12-07 2003-05-27 Harvatek Corp. Focusing cup on a folded frame for surface mount optoelectric semiconductor package
US8344499B2 (en) * 2010-05-24 2013-01-01 Alpha & Omega Semiconductor, Inc Chip-exposed semiconductor device
CN104319340A (zh) * 2014-11-05 2015-01-28 安徽荃富信息科技有限公司 一种led灯用防潮支架

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