FR2969376B1 - Procédé de fabrication de puces de circuits intégrés - Google Patents

Procédé de fabrication de puces de circuits intégrés

Info

Publication number
FR2969376B1
FR2969376B1 FR1060639A FR1060639A FR2969376B1 FR 2969376 B1 FR2969376 B1 FR 2969376B1 FR 1060639 A FR1060639 A FR 1060639A FR 1060639 A FR1060639 A FR 1060639A FR 2969376 B1 FR2969376 B1 FR 2969376B1
Authority
FR
France
Prior art keywords
integrated circuit
circuit chips
producing integrated
producing
chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR1060639A
Other languages
English (en)
Other versions
FR2969376A1 (fr
Inventor
Laurent-Luc Chapelon
Julien Cuzzocrea
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Crolles 2 SAS
Original Assignee
STMicroelectronics Crolles 2 SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Crolles 2 SAS filed Critical STMicroelectronics Crolles 2 SAS
Priority to FR1060639A priority Critical patent/FR2969376B1/fr
Priority to US13/315,441 priority patent/US8518802B2/en
Publication of FR2969376A1 publication Critical patent/FR2969376A1/fr
Application granted granted Critical
Publication of FR2969376B1 publication Critical patent/FR2969376B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Dicing (AREA)
FR1060639A 2010-12-16 2010-12-16 Procédé de fabrication de puces de circuits intégrés Expired - Fee Related FR2969376B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR1060639A FR2969376B1 (fr) 2010-12-16 2010-12-16 Procédé de fabrication de puces de circuits intégrés
US13/315,441 US8518802B2 (en) 2010-12-16 2011-12-09 Process for fabricating integrated-circuit chips

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1060639A FR2969376B1 (fr) 2010-12-16 2010-12-16 Procédé de fabrication de puces de circuits intégrés

Publications (2)

Publication Number Publication Date
FR2969376A1 FR2969376A1 (fr) 2012-06-22
FR2969376B1 true FR2969376B1 (fr) 2013-09-27

Family

ID=44343014

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1060639A Expired - Fee Related FR2969376B1 (fr) 2010-12-16 2010-12-16 Procédé de fabrication de puces de circuits intégrés

Country Status (2)

Country Link
US (1) US8518802B2 (fr)
FR (1) FR2969376B1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130137475A (ko) * 2012-06-07 2013-12-17 삼성전자주식회사 기판 처리방법 및 그에 사용되는 서포트 기판
US20140038357A1 (en) * 2012-08-06 2014-02-06 Apple Inc. Singulated ic stiffener and de-bond process
FR3040532B1 (fr) * 2015-08-31 2017-10-13 St Microelectronics Tours Sas Puce a montage en surface
US10700012B2 (en) * 2017-04-14 2020-06-30 Qualcomm Incorporated Porous silicon dicing

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6107213A (en) 1996-02-01 2000-08-22 Sony Corporation Method for making thin film semiconductor
US5691248A (en) * 1995-07-26 1997-11-25 International Business Machines Corporation Methods for precise definition of integrated circuit chip edges
US6331208B1 (en) 1998-05-15 2001-12-18 Canon Kabushiki Kaisha Process for producing solar cell, process for producing thin-film semiconductor, process for separating thin-film semiconductor, and process for forming semiconductor
US6326279B1 (en) 1999-03-26 2001-12-04 Canon Kabushiki Kaisha Process for producing semiconductor article
JP2001015721A (ja) 1999-04-30 2001-01-19 Canon Inc 複合部材の分離方法及び薄膜の製造方法
JP4329183B2 (ja) 1999-10-14 2009-09-09 ソニー株式会社 単一セル型薄膜単結晶シリコン太陽電池の製造方法、バックコンタクト型薄膜単結晶シリコン太陽電池の製造方法および集積型薄膜単結晶シリコン太陽電池の製造方法
AU781761B2 (en) 2000-03-09 2005-06-09 Interuniversitair Micro-Elektronica Centrum (Imec) Method for the formation and lift-off of porous silicon layers
US6551905B1 (en) 2000-10-20 2003-04-22 Trw Inc. Wafer adhesive for semiconductor dry etch applications
JP2004134672A (ja) 2002-10-11 2004-04-30 Sony Corp 超薄型半導体装置の製造方法および製造装置、並びに超薄型の裏面照射型固体撮像装置の製造方法および製造装置
JP2004221125A (ja) * 2003-01-09 2004-08-05 Sharp Corp 半導体装置及びその製造方法
US20050052219A1 (en) 2003-09-04 2005-03-10 Butler Douglas Blaine Integrated circuit transistor body bias regulation circuit and method for low voltage applications
US20060043534A1 (en) * 2004-08-26 2006-03-02 Kirby Kyle K Microfeature dies with porous regions, and associated methods and systems
JP4349278B2 (ja) * 2004-12-24 2009-10-21 セイコーエプソン株式会社 半導体装置の製造方法
EP1739736A1 (fr) 2005-06-30 2007-01-03 Interuniversitair Microelektronica Centrum ( Imec) Procede de fabrication d'un dispositif à semi-conducteur
JP4321574B2 (ja) 2006-02-27 2009-08-26 セイコーエプソン株式会社 ノズル基板の製造方法、液滴吐出ヘッドの製造方法、液滴吐出ヘッドおよび液滴吐出装置
US8030119B2 (en) 2008-03-08 2011-10-04 Crystal Solar, Inc. Integrated method and system for manufacturing monolithic panels of crystalline solar cells
US7935571B2 (en) 2008-11-25 2011-05-03 Freescale Semiconductor, Inc. Through substrate vias for back-side interconnections on very thin semiconductor wafers
JP2011181822A (ja) 2010-03-03 2011-09-15 Elpida Memory Inc 半導体装置の製造方法

Also Published As

Publication number Publication date
US20120153425A1 (en) 2012-06-21
FR2969376A1 (fr) 2012-06-22
US8518802B2 (en) 2013-08-27

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20150831