CN106469700A - 同轴金属柱 - Google Patents
同轴金属柱 Download PDFInfo
- Publication number
- CN106469700A CN106469700A CN201610397873.XA CN201610397873A CN106469700A CN 106469700 A CN106469700 A CN 106469700A CN 201610397873 A CN201610397873 A CN 201610397873A CN 106469700 A CN106469700 A CN 106469700A
- Authority
- CN
- China
- Prior art keywords
- metal
- layer
- axle center
- coaxial
- post
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000002184 metal Substances 0.000 title claims abstract description 176
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 176
- 239000000463 material Substances 0.000 claims abstract description 35
- 238000005538 encapsulation Methods 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 claims abstract description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 30
- 239000003989 dielectric material Substances 0.000 claims description 16
- 238000009826 distribution Methods 0.000 claims description 15
- 239000007769 metal material Substances 0.000 claims description 10
- 238000004806 packaging method and process Methods 0.000 claims description 7
- 239000011248 coating agent Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 5
- 230000008878 coupling Effects 0.000 claims description 3
- 238000010168 coupling process Methods 0.000 claims description 3
- 238000005859 coupling reaction Methods 0.000 claims description 3
- 238000005520 cutting process Methods 0.000 claims description 3
- 238000007772 electroless plating Methods 0.000 claims description 3
- 230000005611 electricity Effects 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 239000010410 layer Substances 0.000 claims description 2
- 238000012545 processing Methods 0.000 claims description 2
- 230000008054 signal transmission Effects 0.000 abstract description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 13
- 229910052802 copper Inorganic materials 0.000 description 13
- 239000010949 copper Substances 0.000 description 13
- 238000010586 diagram Methods 0.000 description 3
- 101100247631 Metacordyceps chlamydosporia rdc2 gene Proteins 0.000 description 2
- 238000005253 cladding Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 101100412055 Arabidopsis thaliana RD19C gene Proteins 0.000 description 1
- 102100022716 Atypical chemokine receptor 3 Human genes 0.000 description 1
- 101000678890 Homo sapiens Atypical chemokine receptor 3 Proteins 0.000 description 1
- 101000666856 Homo sapiens Vasoactive intestinal polypeptide receptor 1 Proteins 0.000 description 1
- 101150054209 RDL2 gene Proteins 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- ALKZAGKDWUSJED-UHFFFAOYSA-N dinuclear copper ion Chemical compound [Cu].[Cu] ALKZAGKDWUSJED-UHFFFAOYSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
Classifications
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
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Abstract
本发明公开了一种同轴金属柱,包括轴心金属柱、介电层和外层金属层,轴心金属柱设置于封装基材的上层金属垫的上表面;介电层包覆于轴心金属柱的外侧表面;外层金属层包覆于介电层的外侧表面。本发明使用同轴金属柱(coaxial metal pillar)作为芯片封装的电路板侧(PCB side)接点,同轴金属柱应用于电路讯号传输时,外层金属可以隔离噪声干扰,而保持金属柱对讯号传送之完整性。此外,本发明还公开了前述同轴金属柱的制作方法。
Description
技术领域
本发明涉及揭露一种同轴金属柱,特别是设置于芯片封装的电路板侧(PCB side),适合于电子讯号传输时,具有噪声屏蔽,保持信号传输完整性(signal integrity)的同轴金属柱。
背景技术
参照图1,芯片封装单元电性耦合于外部的系统电路板11。系统电路板11的底表面具有多个金属垫113;芯片封装单元具有多个焊球123电性耦合于系统电路板11之金属垫113。芯片封装单元包括:一基材12、一介电层122和一芯片13,基材12具有多个上层金属垫121;介电层122设置于基材12之上表面;芯片13设置于基材12之底部。
图1所示习知技艺的缺点为噪声干扰,在更密集的设计,电路与电路愈靠近,噪声干扰的状况愈严重。
发明内容
针对现有技术的上述不足,根据本发明的实施例,希望提供一种设置于芯片封装的电路板侧(PCB side),适合于电子讯号传输时,具有噪声屏蔽,保持信号传输完整性(signal integrity)的同轴金属柱,并提供前述同轴金属柱的制作方法。
根据实施例,本发明提供的一种同轴金属柱,包括轴心金属柱、介电层和外层金属层,轴心金属柱设置于封装基材的上层金属垫的上表面;介电层包覆于轴心金属柱的外侧表面;外层金属层包覆于介电层的外侧表面。
根据一个实施例,本发明前述同轴金属柱中,轴心金属柱底部电性耦合于金属垫的上表面。
根据一个实施例,本发明前述同轴金属柱中,金属垫为封装基材的电路系统的表面链接端点。
根据一个实施例,本发明前述同轴金属柱中,电路系统进一步包括第一底部电路重新分配层、上层金属垫、第二底部电路重新分配层和下层金属垫,第一底部电路重新分配层设置于同轴金属柱的底部,埋设于第一介电层中;上层金属垫设置于第一底部电路重新分配层的上方,具有第一密度,适合将封装基材电性耦合至外部的系统电路板;第二底部电路重新分配层设置于第一底部电路重新分配层的下方,埋入至第二介电层中;下层金属垫设置于第二底部电路重新分配层下方,具有第二密度;第二密度高于第一密度,适合于芯片安置用。
根据一个实施例,本发明前述同轴金属柱中,外部的系统电路板包括轴心金属垫和环形金属垫,轴心金属垫设置于外部的系统电路板上;环形金属垫环绕于轴心金属垫的外围,电性独立于轴心金属垫;当封装基材与外部的系统电路板连接时,轴心金属垫对应连接同轴金属柱的轴心金属柱,环形金属垫对应连接同轴金属柱的外层金属层。
根据实施例,本发明提供的一种同轴金属柱的制作方法,包括如下工艺步骤:
准备封装基材,表面具有上层介电层,多个上层金属垫裸露于上方,具有一个密度适于将芯片封装单元电性耦合至外部的系统电路板;封装基材具有下层介电层,多个下层金属垫裸露于下方,适于芯片安置用;
涂布种子层,于上金属垫的上表面与上层介电层的上表面;
涂布第一光阻层,于种子层的上表面;
图案化第一光阻层,制作多个第一沟槽;
电镀金属(例如铜)于第一沟槽内,制作多个金属柱;
移除第一光阻层;
移除金属柱与金属柱之间的种子层;
涂布第二光阻层,于介电层的上表面与金属柱的上表面;
图案化第二光阻层,制作多个第二沟槽,第二沟槽环绕特定的金属柱;
填充介电材料于第二沟槽内,包覆裸露的金属柱;
移除顶部多余材料,使第二光阻层、介电材料以及金属柱具有相同的高度;
移除第二光阻层;
涂布第三光阻层;
图案化第三光阻层,制作多个第三沟槽,第三沟槽环绕已被介电材料包覆之特定的金属柱;
无电电镀金属材料(例如铜)层,包覆于介电材料的裸露外表面与轴心金属柱的上表面;
移除第三光阻层;
移除覆盖于介电材料上表面与轴心金属柱上表面的金属材料层。
根据一个实施例,本发明前述同轴金属柱的制作方法中,进一步包括如下工艺步骤:
至少一片芯片电性耦合至下层金属垫;
底部填充材料填充于芯片与基材之间的空间;
切割得到多个芯片封装单元。
相对于现有技术,本发明使用同轴金属柱(coaxial metal pillar)作为芯片封装的电路板侧(PCB side)接点,同轴金属柱应用于电路讯号传输时,外层金属可以隔离噪声干扰,而保持金属柱对讯号传送之完整性。
附图说明
图1为习知技艺之横截面结构示意图。
图2A-2C为根据本发明实施例之同轴金属柱的横截面结构示意图。
图3-21为根据本发明实施例之同轴金属柱的制作方法的工艺流程图。
具体实施方式
下面结合附图和具体实施例,进一步阐述本发明。这些实施例应理解为仅用于说明本发明而不用于限制本发明的保护范围。在阅读了本发明记载的内容之后,本领域技术人员可以对本发明作各种改动或修改,这些等效变化和修改同样落入本发明权利要求所限定的范围。
本发明以下实施例以铜(copper)导线制成同轴金属柱作为范例说明。本发明以下实施例提供的同轴金属柱包括轴心铜金属柱、外层包覆介电层、再包覆外层金属层于介电层外部;轴心铜金属柱电性耦合于外部的系统电路板的电路讯号传输线。介电层包覆于轴心铜金属柱之外侧表面。第二铜金属材料层,再包覆于介电层之外侧表面,电性耦合至外部的系统电路板的零电位,即是接地(ground),构成一个同轴金属柱。
图2A-2C为本发明实施例之示意图。
参照图2A,系统电路板21具有同轴金属垫210。同轴金属垫210设置于系统电路板21之底表面,包括轴心金属垫211和环形金属垫212;其中,环形金属垫212环绕于轴心金属垫211之外围。轴心金属垫211经由系统电路板21上的电路(图中未表示)电性耦合至电子系统之讯号线。环形金属垫212经由系统电路板21上的电路(图中未表示)电性耦合至电子系统之接地线。
图2B为图2A中同轴金属垫210之仰视图。参照图2B,环形金属垫212环绕于轴心金属垫211之外围。环形金属垫212具有轴心金属垫211之讯号遮蔽功能。
图2C为本发明之同轴金属柱之截面结构图。
参照图2A,封装基材22上方为电路板侧(PCB side)具有多个上层金属垫121,提供封装单元电性耦合至外部系统电路板用。同轴金属柱310设置于特定的上层金属垫121之上表面。
同轴金属柱310包括轴心金属柱125、介电层225与金属材料层325。轴心金属柱125底部电性耦合至特定的上层金属垫121。介电层225包覆于轴心金属柱125之外侧表面。铜金属材料层325包覆于介电层225之侧表面。
封装基材22具有第一重新分配电路RDC1埋设于第一介电层D1、D2中。第二重新分配层RDL2具有第二重新分配电路RDC2埋设于第二介电层D3、D4中。上层金属垫121设置于封装基材22之上层,电性耦合至第二重新分配电路RDC2。
至少一片芯片13设置于封装基材22之下方,即是封装基材22的芯片侧(chip side);芯片13电性耦合至封装基材22之下层金属垫221。底部填充材料(underfill)126填充于芯片13与封装基材22之间的空间。封装材料(molding compound)127包覆于芯片13之外侧周边。
上层介电层122设置于封装基材22之上表面,裸露上层金属垫121之上表面中央区域,提供后续制作金属柱(metal pillars)之用。
图3-21为本发明同轴金属柱之制作方法
一同轴金属柱的制作方法,包括:
参照图3,准备封装基材22,该封装基材22,包括:复数个上层金属垫121自上层介电层122裸露出来;
参照图4,涂布种子层(seed layer)123于上层金属垫121之上表面与介电层122之上表面;
参照图5,涂布第一光阻层(PR1)于种子层之上表面;
参照图6,图案化第一光阻层(PR1),制作多个第一沟槽124;
参照图7,电镀金属,如:铜金属,于第一沟槽124内,制作多个金属柱125;
参照图8,移除第一光阻层(PR1);
参照图9,移除金属柱125与金属柱125之间的种子层;
参照图10,涂布第二光阻层(PR2)于介电层122之上表面与金属柱125之上表面;
参照图11,图案化第二光阻层(PR2),制作多个第二沟槽224,并使特定的金属柱得以裸露;
参照图12,填充介电材料225于第二沟槽224内;包覆裸露的金属柱;
参照图13,移除顶部多余材料,使第二光阻层(PR2)、介电材料225以及金属柱125,具有相同的高度;
参照图14,移除第二光阻层(PR2);
参照图15,涂布第三光阻层(PR3);
参照图16,图案化第三光阻层(PR3),制作多个第三沟槽324,使已被介电材料225包覆之特定的金属柱125得以裸露;
参照图17,无电电镀铜金属,制作一铜金属材料层325与325T;其中,铜金属材料层325包覆于介电材料之外侧表面,铜金属材料层325T包覆于轴心金属柱125与介电材料225之上表面;
参照图18,移除第三光阻层(PR3);
参照图19,移除轴心金属柱125上表面与介电材料225上表面之铜金属材料层325T;
参照图20,至少一片芯片13,电性耦合至下层金属垫221之底表面;底部填充材料(underfill),填充于芯片13与封装基材22之间的空间;以及
参照图21,切割得到多个芯片封装单元。
Claims (7)
1.一种同轴金属柱,其特征是,包括轴心金属柱、介电层和外层金属层,轴心金属柱设置于封装基材的上层金属垫的上表面;介电层包覆于轴心金属柱的外侧表面;外层金属层包覆于介电层的外侧表面。
2.如权利要求1所述的同轴金属柱,其特征是,轴心金属柱底部电性耦合于金属垫的上表面。
3.如权利要求1所述的同轴金属柱,其特征是,金属垫为封装基材的电路系统的表面链接端点。
4.如权利要求3所述的同轴金属柱,其特征是,电路系统进一步包括第一底部电路重新分配层、上层金属垫、第二底部电路重新分配层和下层金属垫,第一底部电路重新分配层设置于同轴金属柱的底部,埋设于第一介电层中;上层金属垫设置于第一底部电路重新分配层的上方,具有第一密度,适合将封装基材电性耦合至外部的系统电路板;第二底部电路重新分配层设置于第一底部电路重新分配层的下方,埋入至第二介电层中;下层金属垫设置于第二底部电路重新分配层下方,具有第二密度;第二密度高于第一密度,适合于芯片安置用。
5.如权利要求4所述的同轴金属柱,其特征是,外部的系统电路板包括轴心金属垫和环形金属垫,轴心金属垫设置于外部的系统电路板上;环形金属垫环绕于轴心金属垫的外围,电性独立于轴心金属垫;当封装基材与外部的系统电路板连接时,轴心金属垫对应连接同轴金属柱的轴心金属柱,环形金属垫对应连接同轴金属柱的外层金属层。
6.一种同轴金属柱的制作方法,其特征是,包括如下工艺步骤:
准备基材,表面具有上层介电层;多个上层金属垫裸露于上方,具有一个密度适于将基材电性耦合至外部的系统电路板;具有下层介电层,多个下层金属垫裸露于下方,适于芯片安置用;
涂布种子层,于上金属垫的上表面与上层介电层的上表面;
涂布第一光阻层,于种子层的上表面;
图案化第一光阻层,制作多个第一沟槽;
电镀金属于第一沟槽内,制作多个金属柱;
移除第一光阻层;
移除金属柱与金属柱之间的种子层;
涂布第二光阻层,于介电层的上表面与金属柱的上表面;
图案化第二光阻层,制作多个第二沟槽,第二沟槽环绕特定的金属柱;
填充介电材料于第二沟槽内,包覆裸露的金属柱;
移除顶部多余材料,使第二光阻层、介电材料以及金属柱具有相同的高度;
移除第二光阻层;
涂布第三光阻层;
图案化第三光阻层,制作多个第三沟槽,第三沟槽环绕已被介电材料包覆之特定的金属柱;
无电电镀金属材料层,包覆于介电材料的裸露表面与轴心金属柱的上表面;
移除第三光阻层;
移除覆盖于介电材料上表面与轴心金属柱上表面的金属材料层。
7.如权利要求6所述的同轴金属柱的制作方法,其特征是,进一步包括如下工艺步骤:
至少一片芯片,电性耦合至下层金属垫;
底部填充材料,填充于芯片与基材之间的空间;
切割得到多个芯片封装单元。
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CN102543927A (zh) * | 2010-12-14 | 2012-07-04 | 欣兴电子股份有限公司 | 嵌埋穿孔中介层的封装基板及其制造方法 |
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US11640934B2 (en) * | 2018-03-30 | 2023-05-02 | Intel Corporation | Lithographically defined vertical interconnect access (VIA) in dielectric pockets in a package substrate |
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US9837347B2 (en) | 2017-12-05 |
TW201719685A (zh) | 2017-06-01 |
CN106469700B (zh) | 2019-10-15 |
US20170047281A1 (en) | 2017-02-16 |
TWI685001B (zh) | 2020-02-11 |
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