CN106449539B - Preventing offsetting labeling type semiconductor device architecture - Google Patents

Preventing offsetting labeling type semiconductor device architecture Download PDF

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Publication number
CN106449539B
CN106449539B CN201610637882.1A CN201610637882A CN106449539B CN 106449539 B CN106449539 B CN 106449539B CN 201610637882 A CN201610637882 A CN 201610637882A CN 106449539 B CN106449539 B CN 106449539B
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lead item
pin area
welding
welding ends
bending part
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CN106449539A (en
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张雄杰
何洪运
程琳
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Suzhou Good Ark Electronics Co Ltd
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Suzhou Good Ark Electronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/3701—Shape
    • H01L2224/37011—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005—Shape
    • H01L2224/4007—Shape of bonding interfaces, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005—Shape
    • H01L2224/4009—Loop shape
    • H01L2224/40091—Arched
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/8434—Bonding interfaces of the connector
    • H01L2224/84345—Shape, e.g. interlocking features
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/8438—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/84385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

A kind of preventing offsetting labeling type semiconductor device architecture of the present invention, including it is located at the intracorporal first lead item of epoxy packages, the second lead item, connection sheet and diode chip for backlight unit；Region is equipped with one first bending part between the Support and pin area of first lead item, so that the Support of first lead item is lower than pin area；Region is equipped with one second bending part between the welding section and pin area of second lead item, so that the welding section of the second lead item is lower than pin area；Third bending part is equipped between the first welding ends and the second welding ends of connection sheet, so that the first welding ends is lower than the second welding ends；Epoxy packages body lower surface has a lug boss, and the thickness of the pin area is greater than the thickness of the lug boss；Several through-holes are provided between the third bending part and the second welding ends.Diode device structure of the present invention eliminates a possibility that pin floating degree is lower than lower limit, and product caused by product yield caused by hanging degree value ultra-specification lower limit loses and fails to judge when so as to avoid unit exception is abnormal.

Description

Preventing offsetting labeling type semiconductor device architecture
Technical field
The present invention relates to a kind of diode component more particularly to a kind of preventing offsetting labeling type semiconductor device architectures.
Background technique
Existing semiconductor device structure is usually limited to connection sheet infinite place or using simple groove structure, and disadvantage is only The limit in a direction can be done to connection sheet, the purpose of limit is to avoid the connection sheet deviation in entering furnace welding process to cause to connect Tie point in contact pin, which deflects away from chip welding section, leads to product electrical property failure.When device design requirement need to do connection sheet it is higher When precision limits, existing structure is unable to reach requirement, and the purpose of limit is to avoid the connection sheet deviation in entering furnace welding process Causing the tie point in connection sheet to deflect away from chip welding section leads to product electrical property failure.
Secondly, for the technology stability that guarantee stamp-mounting-paper diode product is mounted in client rs PC B, product shape is usually required Design the pin floating degree of 0.05 ~ 0.2mm.Traditional handicraft guarantees the hanging degree mainly by clubfoot reforming device mold；Again It is secondary, when designing and developing connection chip architecture semiconductor product, in order to promote the electric conductivity of high power device while guarantee relatively thin Product thickness, connection sheet is usually designed as slab construction, when the area of slab construction greatly to a certain extent when, interiors of products Form large thin-wall structure.Interiors of products is easy to appear injection molding stomata in molding process, these stomatas can lead to product electricity Therefore how property or reliability failures, research and develop a kind of semiconductor package convenient for positioning, can solve the above problem, become for The direction that those skilled in the art make great efforts.Therefore, a kind of preventing offsetting labeling type semiconductor device architecture how is researched and developed, can solve Problem is stated, the direction made great efforts for those skilled in the art is become.
Summary of the invention
It is an object of the present invention to provide a kind of preventing offsetting labeling type semiconductor device architecture, which is eliminated Pin floating degree is lower than a possibility that lower limit, product caused by hanging degree value ultra-specification lower limit when so as to avoid unit exception Yield loss and product caused by failing to judge are abnormal；And in entering furnace welding process connection sheet deviation is avoided to cause the company in connection sheet Contact deflect away from chip welding section cause product electrical property failure and encapsulation injection molding in leads to the problem of stomata, improve product electrically with Reliability substantially increases yield.
In order to achieve the above objectives, the technical solution adopted by the present invention is that: a kind of preventing offsetting labeling type semiconductor device architecture, Including being located at the intracorporal first lead item of epoxy packages, the second lead item, connection sheet and diode chip for backlight unit, the first lead item one End is the Support connecting with diode chip for backlight unit, and described diode chip for backlight unit one end is electrically connected by solder(ing) paste with the Support, the The one lead other end is pin area, electric current transmission end of the pin area of the first lead item as the semiconductor devices；
Second lead one end is the welding section connecting with the first welding ends of the connection sheet, the second lead item The other end is pin area, electric current transmission end of the pin area of the second lead item as the rectifier；
Second welding ends of connection sheet is electrically connected with the diode chip for backlight unit other end by solder(ing) paste；
Region is equipped with one first bending part between the Support and pin area of the first lead item, so that first draws The Support of lines is lower than pin area；
Region is equipped with one second bending part between the welding section and pin area of the second lead item, so that second draws The welding section of lines is lower than pin area；
Third bending part is equipped between the first welding ends and the second welding ends of the connection sheet, so that the first welding End is lower than the second welding ends；
Epoxy packages body lower surface has a lug boss, and the thickness of the pin area is greater than the thickness of the lug boss Degree；
Several through-holes are provided between the third bending part and the second welding ends；
The welding section two sides of the second lead item are equipped with block；
Second bending part and the second welding ends angle are 145 °；
The area of the welding section of the second lead item is greater than the area of first welding ends.
Since above-mentioned technical proposal is used, the present invention has following advantages and effect compared with prior art:
Preventing offsetting labeling type semiconductor device architecture of the present invention, epoxy packages body lower surface has a lug boss, described The thickness of pin area is greater than the thickness of the lug boss, i.e. the matching of pin thickness size and ontology locating dimension eliminates pin A possibility that hanging degree is lower than lower limit, product yield caused by hanging degree value ultra-specification lower limit when so as to avoid unit exception Product caused by losing and failing to judge is abnormal；Secondly, it avoids the connection sheet deviation in entering furnace welding process from causing in connection sheet Tie point, which deflects away from chip welding section, leads to product electrical property failure, substantially increases；And the promotion of connection sheet limit accuracy is so that core The performance of piece is given full play to, and can be substituted original large scale crystal grain with smaller size crystal grain, be further decreased manufacturing cost； Again, it is provided with several through-holes between the second bending part and welding section, avoids in encapsulation injection molding and leads to the problem of stomata With the connection sheet deviation in furnace welding process, to improve product electrical property and reliability.
Detailed description of the invention
Attached drawing 1 is preventing offsetting labeling type semiconductor device architecture partial schematic diagram of the present invention；
Attached drawing 2 is the present invention looks up structural representation of attached drawing 1；
Attached drawing 3 is preventing offsetting labeling type semiconductor device architecture schematic diagram of the present invention.
In the figures above: 1, first lead item；2, the second lead item；3, connection sheet；31, the first welding ends；32, the second weldering Connect end；4, diode chip for backlight unit；5, Support；61, pin area；62, pin area；7, welding section；8, block；9, the first bending part； 10, the second bending part；11, third bending part；12, epoxy packages body；13, lug boss；14, through-hole.
Specific embodiment
The invention will be further described with reference to the accompanying drawings and embodiments:
Embodiment: a kind of preventing offsetting labeling type semiconductor device architecture as shown in attached drawing 1 ~ 3, including is located at epoxy packages First lead item 1, the second lead item 2, connection sheet 3 and diode chip for backlight unit 4,1 one end of first lead item in body 12 are and two The Support 5 that pole pipe chip 4 connects, described 4 one end of diode chip for backlight unit are electrically connected by solder(ing) paste with the Support 5, and first draws 1 other end of lines is pin area 61, electric current transmission end of the pin area 61 of the first lead item 1 as the semiconductor devices；
Described second lead item, 2 one end is the welding section 7 connecting with the first welding ends 31 of the connection sheet 3, this second 2 other end of lead item is pin area 62, and the pin area 62 of the second lead item 2 is transmitted as the electric current of the semiconductor devices End；
3 second welding ends 32 of connection sheet is electrically connected with 4 other end of diode chip for backlight unit by solder(ing) paste；
Region is equipped with one first bending part 9 between the Support 5 and pin area 61 of the first lead item 1, so that The Support 5 of first lead item 1 is lower than pin area 61；
Region is equipped with one second bending part 10 between the welding section 7 and pin area 6 of the second lead item 2, so that The welding section 7 of second lead item 2 is lower than pin area 62；
7 two sides of welding section of the second lead item 2 are equipped with block 8；12 lower surface of epoxy packages body is convex with one Portion 13 is played, the thickness C of the pin area 61,62 is greater than the thickness B of the lug boss；Locating dimension A, pin area 61,62 thickness It spends C, the thickness B of lug boss meets following formula: when C-B > hanging degree lower specification limit, pin floating degree ultra-specification can be avoided completely Lower limit.
Third bending part 11 is equipped between the first welding ends 31 and the second welding ends 32 of the connection sheet 3, so that First welding ends is lower than the second welding ends.
Several through-holes 14 are provided between the third bending part 11 and the second welding ends 32；
The area of the welding section 7 of above-mentioned second lead item 2 is greater than the area of first welding ends 31.
Above-mentioned second bending part 10 and 32 angle of the second welding ends are 145 °
When using above-mentioned preventing offsetting labeling type semiconductor device architecture, epoxy packages body lower surface has a lug boss, The thickness of the pin area is greater than the thickness of the lug boss, i.e. the matching of pin thickness size and ontology locating dimension eliminates Pin floating degree is lower than a possibility that lower limit, product caused by hanging degree value ultra-specification lower limit when so as to avoid unit exception Yield loss and product caused by failing to judge are abnormal；Secondly, it avoids the connection sheet deviation in entering furnace welding process from causing connection sheet On tie point deflect away from chip welding section and lead to product electrical property failure, substantially increase yield；And connection sheet limit accuracy mentions It rises so that the performance of chip is given full play to, original large scale crystal grain can be substituted with smaller size crystal grain, further decreased Manufacturing cost；Again, it is provided with several through-holes between the second bending part and welding section, avoids in encapsulation injection molding and generates gas The problem of hole and the connection sheet deviation in furnace welding process, to improve product electrical property and reliability.
The above embodiments merely illustrate the technical concept and features of the present invention, and its object is to allow person skilled in the art Scholar cans understand the content of the present invention and implement it accordingly, and it is not intended to limit the scope of the present invention.It is all according to the present invention Equivalent change or modification made by Spirit Essence, should be covered by the protection scope of the present invention.

Claims (1)

1. a kind of preventing offsetting labeling type semiconductor device architecture, including be located in epoxy packages body (12) first lead item (1), Second lead item (2), connection sheet (3) and diode chip for backlight unit (4), first lead item (1) one end are connected with diode chip for backlight unit (4) The Support (5) connect, described diode chip for backlight unit (4) one end are electrically connected by solder(ing) paste with the Support (5), first lead item (1) other end is pin area (61), and the pin area (61) of the first lead item (1) is transmitted as the electric current of the semiconductor devices End；
Described second lead item (2) one end is the welding section (7) connecting with the first welding ends (31) of the connection sheet (3), should Second lead item (2) other end is pin area (62), and the pin area (62) of the second lead item (2) is used as the semiconductor devices Electric current transmission end；
(3) second welding ends (32) of connection sheet is electrically connected with diode chip for backlight unit (4) other end by solder(ing) paste；Its feature exists In:
Region is equipped with one first bending part (9) between the Support (5) and pin area (61) of the first lead item (1), thus So that the Support (5) of first lead item (1) is lower than pin area (61)；
Region is equipped with one second bending part (10) between the welding section (7) and pin area (62) of the second lead item (2), thus So that the welding section (7) of the second lead item (2) is lower than pin area (62)；
Third bending part (11) are equipped between the first welding ends (31) and the second welding ends (32) of the connection sheet (3), thus So that the first welding ends is lower than the second welding ends；
Epoxy packages body (12) lower surface has a lug boss (13), and the thickness of the pin area (61,62) is greater than described The thickness of lug boss；
Several through-holes (14) are provided between the third bending part (11) and the second welding ends (32)；
Welding section (7) two sides of the second lead item (2) are equipped with block (8)；
The area of the welding section (7) of the second lead item (2) is greater than the area of first welding ends (31)；Second folding Crook (10) and the second welding ends (32) angle are 145 °.
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