CN220138312U - Compact dual chip power device - Google Patents
Compact dual chip power device Download PDFInfo
- Publication number
- CN220138312U CN220138312U CN202321645962.3U CN202321645962U CN220138312U CN 220138312 U CN220138312 U CN 220138312U CN 202321645962 U CN202321645962 U CN 202321645962U CN 220138312 U CN220138312 U CN 220138312U
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- China
- Prior art keywords
- chip
- packaging body
- connecting sheet
- carrier plate
- epoxy packaging
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- 230000009977 dual effect Effects 0.000 title claims description 8
- 239000004593 Epoxy Substances 0.000 claims abstract description 58
- 238000004806 packaging method and process Methods 0.000 claims abstract description 46
- 238000005452 bending Methods 0.000 claims abstract description 12
- 238000003466 welding Methods 0.000 claims description 24
- 230000035882 stress Effects 0.000 description 6
- 230000017525 heat dissipation Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000007774 longterm Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000004064 recycling Methods 0.000 description 1
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
A compact dual-chip power device comprises an epoxy packaging body, a first chip, a second chip and a chip carrier plate; the first connecting piece is arranged above the first chip, and the second connecting piece is arranged between the first chip and the second chip; the upper surface of the first chip is a positive electrode surface and is electrically connected with the lower surface of the first connecting sheet, and the lower surface of the first chip is a negative electrode surface and is electrically connected with the upper surface of the second connecting sheet; the upper surface of the second chip is a negative surface and is electrically connected with the lower surface of the second connecting sheet, and the lower surface of the second chip is a positive surface and is electrically connected with the upper surface of the chip carrier plate; the lower surfaces of the chip carrier plate, the first connecting sheet and the second connecting sheet, which extend out of one end of the epoxy packaging body, are flush with the lower surface of the epoxy packaging body; at least one upward bending structure is formed on the chip carrier plate, so that the lower surface of one end of the chip carrier plate, which is positioned in the epoxy packaging body, is higher than the lower surface of the epoxy packaging body. The power device occupies a small planar space.
Description
Technical Field
The utility model relates to the technical field of semiconductor power devices, in particular to a compact double-chip power device.
Background
Power devices are a common semiconductor device and play an important role in circuit control, so with the continuous development of the electronic industry, the requirements on the power devices are also higher and higher.
The existing power device product generally needs to adopt a chip with a larger size, and in order to realize the parallel circuit function, two large-size chips need to be carried at the same time; in the existing product, in order to meet the heat radiation performance requirement and the reliability requirement of the product, the two large-size chips are fixedly arranged on the same plane side by side, however, the PCB plane space occupied by the layout is relatively large, and the miniaturization design of the terminal product is not facilitated.
In view of the above, it is desirable to provide a power device that occupies a small space in a plane, and can meet the requirements of heat dissipation performance and reliability of the product.
Disclosure of Invention
The utility model aims to provide a compact double-chip power device.
The technical scheme adopted by the utility model is as follows: the compact double-chip power device comprises an epoxy packaging body, a first chip, a second chip and a chip carrier plate, wherein the first chip, the second chip and the chip carrier plate are coated in the epoxy packaging body, and the first chip, the second chip and the chip carrier plate are sequentially overlapped from top to bottom; the first connecting piece is arranged above the first chip, and the second connecting piece is arranged between the first chip and the second chip;
the upper surface of the first chip is a positive electrode surface which is electrically connected with the lower surface of the first connecting sheet, the lower surface of the first chip is a negative electrode surface which is electrically connected with the upper surface of the second connecting sheet; the upper surface of the second chip is a negative electrode surface which is electrically connected with the lower surface of the second connecting sheet, the lower surface of the second chip is a positive electrode surface which is electrically connected with the upper surface of the chip carrier plate;
one end of the chip carrier plate far away from the second chip extends outwards from the epoxy packaging body to serve as a first pin, one end of the first connecting sheet far away from the first chip extends outwards from the epoxy packaging body to serve as a second pin, and one end of the second connecting sheet far away from the first chip extends outwards from the epoxy packaging body to serve as a third pin;
the lower surfaces of the chip carrier plate, the first connecting sheet and the second connecting sheet, which extend out of one end of the outer part of the epoxy packaging body, are all flush with the lower surface of the epoxy packaging body; at least one upward bending structure is formed on the chip carrier plate, so that the lower surface of one end of the chip carrier plate, which is positioned in the epoxy packaging body, is higher than the lower surface of the epoxy packaging body.
According to a further technical scheme, the first pin and the second pin are arranged on the same side of the epoxy packaging body, and the third pin is arranged on the other side of the epoxy packaging body.
According to a further technical scheme, the chip carrier plate comprises a horizontal first welding part and a horizontal first middle part, the first welding part is arranged corresponding to the lower surface of the second chip, a bending structure is arranged between the first welding part and the first middle part, and the first welding part is higher than the first middle part; the first connecting piece comprises a horizontal second welding part and a horizontal second middle part, the second welding part is arranged corresponding to the upper surface of the first chip, a bending structure is arranged between the second welding part and the second middle part, and the second welding part is lower than the second middle part.
According to a further technical scheme, at least one notch is formed in each of the first connecting sheet and the second connecting sheet.
According to a further technical scheme, the notch of the first connecting sheet is arranged on the area of the first connecting sheet in the epoxy packaging body, and the notch of the second connecting sheet is arranged on the area of the second connecting sheet in the epoxy packaging body.
According to a further technical scheme, the first connecting sheet, the second connecting sheet and the chip carrier plate are respectively provided with at least one groove in the area in the epoxy packaging body.
The utility model has the beneficial effects that: compared with the parallel arrangement in the prior art, the compact double-chip power device has the advantages that the occupied planar space is greatly reduced through the layout design that the first chip and the second chip are stacked up and down, and the product miniaturization is facilitated;
in addition, by arranging the first connecting sheet and the second connecting sheet corresponding to the two chips, the circuit can be conducted, and meanwhile, the auxiliary heat dissipation effect can be achieved, so that the heat dissipation performance requirement of a product is met, meanwhile, the stress formed by directly stacking the two chips can be buffered, and the durability and the reliability of the product are improved;
in addition, through forming the upward bending structure on the chip carrier plate, the connecting end of the chip carrier plate and the second chip is positioned at a higher position, so that the two chips are positioned in the middle area of the epoxy packaging body, the binding force between each part and the epoxy packaging body can be enhanced, layering is avoided, structural stress generated in the packaging process can be reduced, and the reliability of the product in a long-term high-low temperature cyclic use environment is improved.
Drawings
FIG. 1 is a cross-sectional view from a side view of an embodiment of the present utility model;
fig. 2 is a schematic structural diagram of an embodiment of the present utility model in a top view.
In the above figures: 1. an epoxy encapsulation; 21. a first chip; 22. a second chip; 3. a chip carrier; 41. a first connecting piece; 42. a second connecting piece; 51. a first pin; 52. a second pin; 53. a third pin; 61. a first welded portion; 62. a first intermediate portion; 63. a second welded portion; 64. a second intermediate portion; 71. a notch; 72. a groove.
Description of the embodiments
The utility model is further described below with reference to the accompanying drawings and examples:
the present utility model will be described in detail with reference to the drawings, wherein modifications and variations are possible in light of the teachings of the present utility model, without departing from the spirit and scope of the present utility model, as will be apparent to those of skill in the art upon understanding the embodiments of the present utility model.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. Singular forms such as "a," "an," "the," and "the" are intended to include the plural forms as well, as used herein.
The terms "first," "second," and the like, as used herein, do not denote a particular order or sequence, nor are they intended to be limiting, but rather are merely used to distinguish one element or operation from another in the same technical term.
As used herein, "connected" or "positioned" may refer to two or more components or devices in physical contact with each other, or indirectly, or in operation or action with each other.
As used herein, the terms "comprising," "including," "having," and the like are intended to be open-ended terms, meaning including, but not limited to.
The term (terms) as used herein generally has the ordinary meaning of each term as used in this field, in this disclosure, and in the special context, unless otherwise noted. Certain terms used to describe the disclosure are discussed below, or elsewhere in this specification, to provide additional guidance to those skilled in the art in light of the description of the disclosure.
The terms "front", "rear", "upper", "lower", "left", "right" and the like used herein are directional terms, and are merely used to describe positional relationships among the structures in the present application, and are not intended to limit the scope of the present application and the specific direction in actual implementation.
As shown in the embodiments of fig. 1 and fig. 2, a compact dual-chip power device is provided, which includes an epoxy package 1, and a first chip 21, a second chip 22 and a chip carrier 3 that are wrapped in the epoxy package 1, wherein the first chip 21, the second chip 22 and the chip carrier 3 are stacked in sequence from top to bottom; the semiconductor package further comprises a first connecting sheet 41 and a second connecting sheet 42, wherein the first connecting sheet 41 is arranged above the first chip 21, and the second connecting sheet 42 is arranged between the first chip 21 and the second chip 22.
Therefore, the power device realizes the parallel function of a circuit through the layout design of stacking the first chip 21 and the second chip 22 up and down under the condition of stacking the 2 chips, and compared with the parallel arrangement in the prior art, the planar size of the product is reduced by about 40%, the occupied planar space is greatly reduced, and the miniaturization of the product is facilitated.
The upper surface of the first chip 21 is a positive electrode surface, which is electrically connected to the lower surface of the first connecting piece 41, and the lower surface of the first chip 21 is a negative electrode surface, which is electrically connected to the upper surface of the second connecting piece 42; the upper surface of the second chip 22 is a negative electrode surface, which is electrically connected to the lower surface of the second connecting piece 42, and the lower surface of the second chip 22 is a positive electrode surface, which is electrically connected to the upper surface of the chip carrier 3.
One end of the chip carrier 3 far away from the second chip 22 extends outwards from the epoxy package 1 as a first pin 51, one end of the first connecting piece 41 far away from the first chip 21 extends outwards from the epoxy package 1 as a second pin 52, and one end of the second connecting piece 42 far away from the first chip 21 extends outwards from the epoxy package 1 as a third pin 53.
Therefore, the first connecting sheet 41 and the second connecting sheet 42 are arranged corresponding to the two chips, so that the circuit is conducted, an auxiliary heat dissipation effect is achieved, the heat dissipation performance requirement of a product is met, meanwhile, the stress formed by directly stacking the two chips can be buffered, and the durability and the reliability of the product are improved.
The lower surfaces of the chip carrier 3, the first connecting piece 41 and the second connecting piece 42, which extend out of the outer end of the epoxy packaging body 1, are all flush with the lower surface of the epoxy packaging body 1; an upward bending structure is formed on the chip carrier 3, so that the lower surface of one end of the chip carrier 3 located in the epoxy packaging body 1 is higher than the lower surface of the epoxy packaging body 1.
Therefore, by forming the upward bending structure on the chip carrier plate 3, the connecting end of the chip carrier plate 3 and the second chip 22 is positioned at a higher position, so that the two chips are positioned in the middle area of the epoxy packaging body 1, the binding force between each component and the epoxy packaging body 1 can be enhanced, layering is avoided, the structural stress generated in the packaging process can be reduced, and the reliability of the product in a long-term high-low temperature recycling environment is improved.
In the compact dual-chip power device, the positive surface of the first chip 21 is electrically connected to the second pin 52 outside the epoxy package 1 through the first connecting sheet 41, the positive surface of the second chip 22 is electrically connected to the first pin 51 outside the epoxy package 1 through the chip carrier 3, and the negative surfaces of the first chip 21 and the second chip 22 are electrically connected to the third pin 53 outside the epoxy package 1 through the second connecting sheet 42, so that the compact dual-chip power device is further connected to an external circuit through the three pins in actual use.
In this embodiment, the first pins 51 and the second pins 52 are disposed on the same side of the epoxy package 1, and the third pins 53 are disposed on the other side of the epoxy package 1, so that a better stable structure is formed in the epoxy package 1.
In this embodiment, the chip carrier 3 includes a horizontal first welding portion 61 and a horizontal first middle portion 62, where the first welding portion 61 is disposed corresponding to the lower surface of the second chip 22 and is welded to the second chip 22, and a bending structure is disposed between the first welding portion 61 and the first middle portion 62, so that the first welding portion 61 is higher than the first middle portion 62; the first connecting piece 41 includes a horizontal second welding portion 63 and a horizontal second middle portion 64, the second welding portion 63 is disposed corresponding to the upper surface of the first chip 21, and is welded to the first chip 21, and a bending structure is disposed between the second welding portion 63 and the second middle portion 64, so that the second welding portion 63 is lower than the second middle portion 64; therefore, the bonding force between the chip carrier 3 and the first connecting sheet 41 and the epoxy packaging body 1 can be enhanced, delamination is avoided, and the structural stability under long-time working is ensured.
In this embodiment, the first connecting piece 41 has a notch 71 in the area inside the epoxy package 1, the second connecting piece 42 has two notches 71 in the area inside the epoxy package 1, and the chip carrier 3 has a notch 71 in the area inside the epoxy package 1; therefore, the problem that the chip of the packaging structure with compact design bears larger mechanical stress and thermal stress in the process can be solved.
In this embodiment, the first connecting piece 41, the second connecting piece 42, and the chip carrier 3 are respectively provided with a groove 72 in the area of the epoxy packaging body 1; therefore, the problem that the chip of the packaging structure with compact design bears larger mechanical stress and thermal stress in the process can be solved.
In summary, the compact dual-chip power device achieves the technical effect of reducing the occupied planar space on the basis of meeting the heat radiation performance requirement and the reliability requirement of the product, and is convenient for miniaturization of the terminal product.
The above embodiments are provided to illustrate the technical concept and features of the present utility model and are intended to enable those skilled in the art to understand the content of the present utility model and implement the same, and are not intended to limit the scope of the present utility model. All equivalent changes or modifications made in accordance with the spirit of the present utility model should be construed to be included in the scope of the present utility model.
Claims (6)
1. A compact dual chip power device, characterized by:
the packaging structure comprises an epoxy packaging body (1), and a first chip (21), a second chip (22) and a chip carrier plate (3) which are coated in the epoxy packaging body (1), wherein the first chip (21), the second chip (22) and the chip carrier plate (3) are sequentially overlapped from top to bottom; the chip comprises a first chip (21), a first connecting piece (41) and a second connecting piece (42), wherein the first connecting piece (41) is arranged above the first chip (21), and the second connecting piece (42) is arranged between the first chip (21) and the second chip (22);
the upper surface of the first chip (21) is a positive electrode surface which is electrically connected with the lower surface of the first connecting sheet (41), the lower surface of the first chip (21) is a negative electrode surface which is electrically connected with the upper surface of the second connecting sheet (42); the upper surface of the second chip (22) is a negative electrode surface, the negative electrode surface is electrically connected with the lower surface of the second connecting sheet (42), the lower surface of the second chip (22) is a positive electrode surface, and the positive electrode surface is electrically connected with the upper surface of the chip carrier plate (3);
one end of the chip carrier plate (3) far away from the second chip (22) extends outwards from the interior of the epoxy packaging body (1) to serve as a first pin (51), one end of the first connecting sheet (41) far away from the first chip (21) extends outwards from the interior of the epoxy packaging body (1) to serve as a second pin (52), and one end of the second connecting sheet (42) far away from the first chip (21) extends outwards from the interior of the epoxy packaging body (1) to serve as a third pin (53);
the lower surfaces of the chip carrier plate (3), the first connecting sheet (41) and the second connecting sheet (42) respectively extend out of one end of the outer side of the epoxy packaging body (1) are all flush with the lower surface of the epoxy packaging body (1); at least one upward bending structure is formed on the chip carrier plate (3), so that the lower surface of one end of the chip carrier plate (3) positioned in the epoxy packaging body (1) is higher than the lower surface of the epoxy packaging body (1).
2. The compact dual chip power device as defined in claim 1, wherein: the first pin (51) and the second pin (52) are arranged on the same side of the epoxy packaging body (1), and the third pin (53) is arranged on the other side of the epoxy packaging body (1).
3. A compact dual chip power device as defined in claim 2, wherein: the chip carrier plate (3) comprises a horizontal first welding part (61) and a horizontal first middle part (62), the first welding part (61) is arranged corresponding to the lower surface of the second chip (22), a bending structure is arranged between the first welding part (61) and the first middle part (62), and the first welding part (61) is higher than the first middle part (62); the first connecting piece (41) comprises a horizontal second welding part (63) and a horizontal second middle part (64), the second welding part (63) is arranged corresponding to the upper surface of the first chip (21), a bending structure is arranged between the second welding part (63) and the second middle part (64), and the second welding part (63) is lower than the second middle part (64).
4. The compact dual chip power device as defined in claim 1, wherein: at least one notch (71) is arranged on each of the first connecting piece (41) and the second connecting piece (42).
5. The compact dual chip power device as defined in claim 4, wherein: the notch (71) of the first connecting sheet (41) is arranged on the area of the first connecting sheet (41) positioned inside the epoxy packaging body (1), and the notch (71) of the second connecting sheet (42) is arranged on the area of the second connecting sheet (42) positioned inside the epoxy packaging body (1).
6. The compact dual chip power device as defined in claim 1, wherein: the first connecting sheet (41), the second connecting sheet (42) and the chip carrier plate (3) are respectively provided with at least one groove (72) on the area which is respectively positioned in the epoxy packaging body (1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321645962.3U CN220138312U (en) | 2023-06-27 | 2023-06-27 | Compact dual chip power device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321645962.3U CN220138312U (en) | 2023-06-27 | 2023-06-27 | Compact dual chip power device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220138312U true CN220138312U (en) | 2023-12-05 |
Family
ID=88947962
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202321645962.3U Active CN220138312U (en) | 2023-06-27 | 2023-06-27 | Compact dual chip power device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN220138312U (en) |
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2023
- 2023-06-27 CN CN202321645962.3U patent/CN220138312U/en active Active
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